JP3251810B2 - Mounting method of integrated circuit device - Google Patents

Mounting method of integrated circuit device

Info

Publication number
JP3251810B2
JP3251810B2 JP13521895A JP13521895A JP3251810B2 JP 3251810 B2 JP3251810 B2 JP 3251810B2 JP 13521895 A JP13521895 A JP 13521895A JP 13521895 A JP13521895 A JP 13521895A JP 3251810 B2 JP3251810 B2 JP 3251810B2
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
electrode
film
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP13521895A
Other languages
Japanese (ja)
Other versions
JPH08330361A (en
Inventor
恒一 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13521895A priority Critical patent/JP3251810B2/en
Publication of JPH08330361A publication Critical patent/JPH08330361A/en
Application granted granted Critical
Publication of JP3251810B2 publication Critical patent/JP3251810B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、集積回路装置の実装方
法に関し、特に配線基板上の搭載密度を向上させた実装
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an integrated circuit device, and more particularly, to a method for mounting an integrated circuit device on a wiring board with an improved mounting density.

【0002】[0002]

【従来の技術】集積回路技術の進展に伴い、1チップの
集積度が大規模化し、入出力端子数も増大する傾向にあ
る。このような多端子の集積回路にあっては、QFP
(QuadFlat Package)と呼ばれる4辺にリードを有する
樹脂パッケージや、PGA(Pin Grid Array)と呼ばれ
るパッケージ底面にアレイ状の端子を有するパッケージ
が使用されている。
2. Description of the Related Art With the development of integrated circuit technology, the degree of integration of one chip tends to increase, and the number of input / output terminals tends to increase. In such a multi-terminal integrated circuit, QFP
A resin package called “QuadFlat Package” having leads on four sides and a package called PGA (Pin Grid Array) having an array of terminals on the bottom surface of the package are used.

【0003】これらのパッケージは通常の配線基板への
実装手段である半田付けが可能なレベルまでリード間隔
を広げるため、必然的にパッケージが大きくなり、配線
基板上の占有面積が大きいという問題がある。そこでベ
アチップレベルの実装が可能なTAB(Tape Automated
Bonding)方式が採用される場合がある。
[0003] In these packages, since the lead interval is increased to a level at which soldering, which is a means for mounting on a normal wiring board, is possible, the package is inevitably large, and the area occupied on the wiring board is large. . Therefore, TAB (Tape Automated
Bonding) method may be adopted.

【0004】TAB方式は、よく知られたTABテープ
のインナーリードに集積回路チップをボンディングし、
電気的検査を行った後アウターリード部でテープよりカ
ットし、必要であればリードフォーミングして配線基板
に実装している。
In the TAB method, an integrated circuit chip is bonded to inner leads of a well-known TAB tape,
After the electrical inspection, the tape is cut from the tape at the outer lead portion, and if necessary, is lead-formed and mounted on a wiring board.

【0005】図8はTAB方式の基板実装を示した断面
図である。集積回路チップ100はバンプ電極102を
介してTABテープのインナーリード104に接続され
ている。複数のインナーリード104は整列された状態
でサポートリング106により絶縁的に保持されてお
り、アウターリード108が配線基板110の導体配線
112に接続されている。
FIG. 8 is a sectional view showing the mounting of a TAB type substrate. The integrated circuit chip 100 is connected to inner leads 104 of a TAB tape via bump electrodes 102. The plurality of inner leads 104 are insulated and held by the support ring 106 in an aligned state, and the outer leads 108 are connected to the conductor wiring 112 of the wiring board 110.

【0006】このTAB方式は、QFPよりは占有面積
的に小さいものの、チップ100の周辺にリードを張り
出している分、実装面積がチップ面積より広くなってい
る。配線基板の高密度実装が進むとこのリード部分の占
有面積が無視できなくなってきている。
In the TAB method, although the area occupied is smaller than that of the QFP, the mounting area is larger than the chip area because the leads are extended around the chip 100. As the high-density mounting of the wiring board progresses, the area occupied by the leads cannot be ignored.

【0007】[0007]

【発明が解決しようとする課題】上記のように配線基板
の実装密度が上がるにつれて、TAB方式のリード部分
の実装密度も無視できなくなってきている。本発明は上
記事情に鑑みてなされたもので、テープを使用しながら
チップサイズレベルの実装が可能な集積回路の実装方法
を提供しようとするものである。
As described above, as the mounting density of the wiring board increases, the mounting density of the TAB type lead portion cannot be ignored. The present invention has been made in view of the above circumstances, and has as its object to provide a mounting method of an integrated circuit that can be mounted at a chip size level using a tape.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に本発明の集積回路装置の実装方法は、配線基板の集積
回路装置搭載領域内にに複数のバンプ電極を形成する工
程と、可撓性フィルムの主面に中央部より端部に向けて
形成された複数の配線導体と、前記配線導体の各々に形
成され、前記中央部に形成された第1の電極及び前記端
部に形成された第2の電極とを有する配線フィルムの前
記第1の電極を、前記配線基板の対応する前記バンプ電
極に接続する工程と、上面に複数の第3の電極を有する
集積回路装置の下面を接着剤を介して前記配線フィルム
上のほぼ中央部に載置する工程と、前記配線フィルムの
前記端部を前記集積回路装置の周縁に沿って折り曲げ、
前記配線フィルムの前記第2の電極を前記集積回路装置
の対応する第3の電極に接続する工程とを具備するする
ことを特徴としている。
In order to solve the above-mentioned problems, a method of mounting an integrated circuit device according to the present invention comprises the steps of forming a plurality of bump electrodes in an integrated circuit device mounting area of a wiring board; A plurality of wiring conductors formed on the main surface of the conductive film from the center toward the end, and formed on each of the wiring conductors, the first electrode formed on the center, and the end formed on the end. Connecting the first electrode of the wiring film having the second electrode to the corresponding bump electrode of the wiring substrate, and bonding the lower surface of the integrated circuit device having the plurality of third electrodes on the upper surface Placing the wiring film at a substantially central portion on the wiring film via an agent, and bending the end portion of the wiring film along the periphery of the integrated circuit device;
Connecting the second electrode of the wiring film to a corresponding third electrode of the integrated circuit device.

【0009】このとき前記配線基板に前記複数のバンプ
電極を形成する際に、前記バンプ電極の頭部が突出する
厚さの絶縁フィルムを前記バンプ電極領域を避けて前記
基板上に併せて形成することが望ましい。
At this time, when the plurality of bump electrodes are formed on the wiring substrate, an insulating film having a thickness protruding from the bump electrode head is formed on the substrate together with the bump electrode region. It is desirable.

【0010】また本発明の他の実装方法は、可撓性フィ
ルムの主面に中央部より端部に向けて形成された複数の
配線導体と、前記配線導体の各々に形成され、前記中央
部に形成された第1の電極及び前記端部に形成された第
2の電極とを有する配線フィルムの前記第1の電極にバ
ンブ電極を形成する工程と、前記配線フィルムの前記バ
ンプ電極を、配線基板に形成された複数の第3の電極の
各々に対応させて接続する工程と、上面に複数の第4の
電極を有する集積回路装置の下面を接着剤を介して前記
配線フィルムのほぼ中央部に載置する工程と、前記配線
フィルムを前記集積回路装置の周縁に沿って折り曲げ、
前記配線フィルムの対応する前記第2の電極を前記集積
回路装置の第4の電極に接続する工程とを具備するする
ことを特徴としている。
In another mounting method of the present invention, a plurality of wiring conductors are formed on a main surface of a flexible film from a central portion toward an end, and the wiring conductors are formed on each of the wiring conductors. Forming a bump electrode on the first electrode of the wiring film having a first electrode formed on the substrate and a second electrode formed on the end portion; Connecting the plurality of third electrodes formed on the substrate in correspondence with each other, and connecting the lower surface of the integrated circuit device having the plurality of fourth electrodes on the upper surface to the substantially central portion of the wiring film via an adhesive; And bending the wiring film along the periphery of the integrated circuit device,
Connecting the corresponding second electrode of the wiring film to a fourth electrode of the integrated circuit device.

【0011】このとき前記配線フィルムの前記バンプ電
極を、配線基板に形成された複数の第3の電極の各々に
対応させて接続する際に、前記バンプ電極の頭部が露出
する程度の厚さの絶縁フィルムを前記バンプ電極領域を
避けて前記配線フィルムと前記配線基板の間に介在させ
ることが望ましい。
At this time, when connecting the bump electrode of the wiring film to each of the plurality of third electrodes formed on the wiring board, the bump electrode has a thickness such that the head of the bump electrode is exposed. It is preferable that the insulating film is interposed between the wiring film and the wiring board, avoiding the bump electrode region.

【0012】[0012]

【作用】上記のように本発明においては、可撓性フィル
ムによる配線フィルムを予め配線基板に接続する。この
とき接続領域は後に搭載する集積回路チップの裏面に収
まる範囲に設定される。しかる後、集積回路チップを前
記配線フィルム上に搭載し、前記フィルムを折り曲げて
集積回路チップを包みこみ、チップ上面の電極と接続し
ている。これにより集積回路チップの接続領域はそのチ
ップサイズ以内とすることができ、配線基板の実装密度
を向上させることができる。
As described above, in the present invention, a wiring film made of a flexible film is connected to a wiring board in advance. At this time, the connection region is set to a range that fits on the back surface of the integrated circuit chip to be mounted later. Thereafter, the integrated circuit chip is mounted on the wiring film, and the film is bent to wrap the integrated circuit chip and connect to the electrodes on the upper surface of the chip. As a result, the connection area of the integrated circuit chip can be kept within the chip size, and the mounting density of the wiring board can be improved.

【0013】このときバンプ電極の頭部が露出する程度
の厚さの絶縁フィルムを、配線基板と配線フィルムの間
に介在させると、集積回路チップが配線基板にしっかり
と固定されるので、集積回路チップと配線フィルムの配
線導体とのボンディングが良好に行える。
At this time, if an insulating film having such a thickness as to expose the head of the bump electrode is interposed between the wiring board and the wiring film, the integrated circuit chip is firmly fixed to the wiring board. Good bonding between the chip and the wiring conductor of the wiring film can be performed.

【0014】[0014]

【実施例】以下、図面を参照しながら実施例を説明す
る。 (実施例1)図1は本発明の第1の実施例に係る集積回
路装置の実装方法により実装された実装体の模式的な断
面図を示し、図2、図3はその実装工程を段階的に示し
た実装体の断面図である。図4はこの実装に使用される
配線フィルムを模式的に示した平面図(底面図)であ
る。配線は左側1/4領域のみ記載したが、全領域に同
様に形成されることはいうまでもない。
Embodiments will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a schematic cross-sectional view of a mounting body mounted by a mounting method of an integrated circuit device according to a first embodiment of the present invention, and FIGS. FIG. 2 is a cross-sectional view of a mounting body schematically shown. FIG. 4 is a plan view (bottom view) schematically showing a wiring film used for this mounting. Although the wiring is described only in the left quarter region, it goes without saying that the wiring is similarly formed in the entire region.

【0015】即ち配線基板12の配線導体14上に接着
されたポリイミド等の絶縁フィルム16の接続孔の中に
形成された金バンプ18と、ポリイミド等の絶縁フィル
ム20の片面に接着された金メッキ銅配線22とが熱圧
着接合され、集積回路チップ10は絶縁性接着剤24を
介して前記絶縁フィルム20で包み込まれ、集積回路チ
ップ10のバンプ電極26と、金メッキ銅配線22とが
熱圧着接合されている。なお配線導体14は、金バンプ
14に夫々分離されて個々に接続されるが、図の煩雑化
を避けるために、1本の配線のごとく図示されている。
That is, a gold bump 18 formed in a connection hole of an insulating film 16 made of polyimide or the like adhered on the wiring conductor 14 of the wiring board 12 and a gold-plated copper adhered to one surface of an insulating film 20 made of polyimide or the like. The wiring 22 is thermocompression bonded, the integrated circuit chip 10 is wrapped with the insulating film 20 via the insulating adhesive 24, and the bump electrode 26 of the integrated circuit chip 10 and the gold plated copper wiring 22 are thermocompression bonded. ing. The wiring conductors 14 are separated from each other and individually connected to the gold bumps 14, but are illustrated as one wiring in order to avoid complication of the drawing.

【0016】本実施例の実装方法を図2、図3を参照し
て説明する。まずガラスエポキシ系あるいはポリイミド
系等の配線基板基板12の表層に銅の配線導体14が貼
着されている。この基板は内層に配線導体を含む多層基
板であってもよい。この配線導体14の上に接続孔15
が穿孔されたポリイミド絶縁フィルム16が接着されて
いる(図2(a))。この接続孔15は後に搭載される
集積回路チップの搭載領域内に形成される。次に接続孔
15の内部に選択的に金メッキを堆積させて金バンプ1
8を形成する。金バンプ18はポリイミド絶縁フィルム
16の表面より突出するように形成するのが好ましい
(図2(b))。
A mounting method according to this embodiment will be described with reference to FIGS. First, a copper wiring conductor 14 is adhered to a surface layer of a wiring board substrate 12 made of glass epoxy or polyimide. This substrate may be a multilayer substrate including a wiring conductor in an inner layer. A connection hole 15 is formed on the wiring conductor 14.
Is adhered to the perforated polyimide insulating film 16 (FIG. 2A). The connection hole 15 is formed in a mounting area of an integrated circuit chip to be mounted later. Next, gold plating is selectively deposited inside the connection hole 15 to form the gold bump 1.
8 is formed. The gold bumps 18 are preferably formed so as to protrude from the surface of the polyimide insulating film 16 (FIG. 2B).

【0017】続いてポリイミド絶縁フィルム20に銅配
線22が貼着された配線フィルムを準備する。図4にこ
の配線フィルムの平面図を示すが、通常のTABテープ
と同様なプロセスにより製造することができる。銅配線
22の表面には金メッキが施されている。なおこの金メ
ッキは錫メッキに代えてもよい。配線フィルムの中央部
のポリイミドフィルム20には、前記金バンプ18に対
応する開口部30が設けられ、銅配線22が露出するよ
うになっている。ポリイミドフィルムが半透明であるこ
とと、この開口部30を通じて下部の基板が直視できる
ので位置合せも容易である。
Subsequently, a wiring film having a copper wiring 22 adhered to the polyimide insulating film 20 is prepared. FIG. 4 shows a plan view of this wiring film, which can be manufactured by the same process as a normal TAB tape. The surface of the copper wiring 22 is plated with gold. This gold plating may be replaced with tin plating. An opening 30 corresponding to the gold bump 18 is provided in the polyimide film 20 at the center of the wiring film, so that the copper wiring 22 is exposed. Since the polyimide film is translucent and the lower substrate can be directly viewed through the opening 30, alignment is easy.

【0018】個々の銅配線はこの開口部30で終端する
のが一般的であるが、図4の左上コーナー部に示すよう
に、他の縁面と連続的に形成される場合もある。ただし
図3の断面図においては、図の煩雑化を避ける目的で銅
配線22は1本の線のように図示している。この開口部
30と金バンプ18とを位置合わせしてボンデイングツ
ール28を押し当てて熱圧着する(図3(a))。
The individual copper wirings are generally terminated at the openings 30, but may be formed continuously with other edges as shown in the upper left corner of FIG. However, in the cross-sectional view of FIG. 3, the copper wiring 22 is illustrated as a single line in order to avoid complication of the drawing. The opening 30 and the gold bump 18 are aligned, and a bonding tool 28 is pressed to perform thermocompression bonding (FIG. 3A).

【0019】続いて集積回路チップ10を配線フィルム
の中央部に接着剤24を介してマウントする。接着剤2
4はエポキシ系、ポリイミド系等の耐熱性の接着剤を使
用するのが望ましい(図3(b))。
Subsequently, the integrated circuit chip 10 is mounted on the center of the wiring film via an adhesive 24. Adhesive 2
It is desirable to use a heat-resistant adhesive such as an epoxy-based or polyimide-based adhesive 4 (FIG. 3B).

【0020】次に配線フィルムの端部のポリイミドフィ
ルム部20aを保持して、1辺づつチップ10を包み込
むように成形し、チップ10の電極26と、配線フィル
ムの銅配線22とを熱圧着ボンディングする。このとき
集積回路チップ10は、ポリイミドフィルム16を介し
て配線基板12にしっかり固定されているのでボンディ
ングも容易に行える。
Next, while holding the polyimide film portion 20a at the end of the wiring film, it is molded so as to enclose the chip 10 side by side, and the electrode 26 of the chip 10 and the copper wiring 22 of the wiring film are bonded by thermocompression bonding. I do. At this time, since the integrated circuit chip 10 is firmly fixed to the wiring board 12 via the polyimide film 16, bonding can be easily performed.

【0021】このボンディング終了後は他の辺のボンデ
ィングの邪魔にならないようにポリイミドフィルム部2
0aを垂直に折り曲げ、場合によってはこの段階で折り
曲げ部32の近傍でリードカットを行っても良い。リー
ドカットは、ボンディング部、チップに悪影響を及ぼさ
ない手段であれば何れでもよいが、例えばレーザーカッ
トでカットする(図3(c))。
After the completion of the bonding, the polyimide film portion 2 is so formed as not to hinder the bonding of the other side.
Oa may be bent vertically, and in this case, lead cutting may be performed near the bent portion 32 at this stage. The lead cut may be performed by any means that does not adversely affect the bonding portion and the chip. For example, the lead cut is performed by laser cutting (FIG. 3C).

【0022】このリードボンディングを各辺に対して実
施して図1に示すような実装体が得られる。この実装方
法であれば、配線基板12との接続箇所がチップ10の
裏面に収まるので配線基板の実装密度を上げることが可
能になる。配線フィルムの基板との接続箇所は、図4に
示すようにチップの周縁部だけでなく中央部も使用する
ことができるので、配線エリアを広げることが可能とな
る。このチップ中央部もボンディングエリアに利用する
考え方は、チップ上面のボンディングにも適用すること
ができる。
By performing this lead bonding on each side, a package as shown in FIG. 1 is obtained. According to this mounting method, since the connection portion with the wiring board 12 is accommodated on the back surface of the chip 10, the mounting density of the wiring board can be increased. As shown in FIG. 4, not only the peripheral portion of the chip but also the central portion can be used as the connection portion between the wiring film and the substrate, so that the wiring area can be expanded. The concept of using the chip central portion also for the bonding area can be applied to bonding on the upper surface of the chip.

【0023】本実施例では金バンプ18を配線基板10
側に設けたが、配線フィルム側に設けるようにしてもよ
い。 (実施例2)図1に示す実装体の実装方法としては、種
々の変形が考えられる。図5は第1の実施例の図2
(b),図3(a)の工程の変形例である。本実施例で
は、配線フィルムの配線基板10との接続部分には半田
バンプ38が形成されている。この半田バンプは例えば
半田クリームの印刷により形成することができる。
In this embodiment, the gold bump 18 is
Although provided on the wiring film side, it may be provided on the wiring film side. Embodiment 2 Various modifications are conceivable as a mounting method of the mounting body shown in FIG. FIG. 5 shows FIG. 2 of the first embodiment.
FIG. 3B is a modification of the step of FIG. In this embodiment, solder bumps 38 are formed at the connection portions of the wiring film and the wiring board 10. The solder bumps can be formed, for example, by printing solder cream.

【0024】配線基板12の配線導体14上にはソルダ
ーレジスト34が設けられ、接続の為の開口部36が開
口されている。この開口部36に対応する半田バンプ3
8を位置合せして、上部よりホットツール(図示せず)
にて熱圧着することにより接合することができる。位置
合せはポリイミドフィルム20に透孔部を設け、配線基
板側に位置合わせマークを設ける等して適宜行うことが
できる。
A solder resist 34 is provided on the wiring conductor 14 of the wiring board 12, and an opening 36 for connection is opened. The solder bump 3 corresponding to the opening 36
Align 8 and hot tool from top (not shown)
Can be joined by thermocompression bonding. The alignment can be performed as appropriate by providing a through hole in the polyimide film 20 and providing an alignment mark on the wiring board side.

【0025】その後の工程は実施例1に同じであるが、
集積回路チップ側のバンプ電極は、半田バンプ38より
も融点の低い半田(合金)を用いて温度差を持たせるこ
とが望ましい。例えば半田バンプ38にSn系合金を用
いた場合には、チップ電極にはIn系合金を用いる。ま
たこの場合も集積回路チップ10は、ポリイミドフィル
ム34を介して配線基板12にしっかり固定されている
のでボンディングも容易に行える。 (実施例3)図6は第1の実施例の図2(a),
(b),図3(a)の工程のさらに他の変形例である。
本実施例では、配線フィルムの配線導体22上には導電
性樹脂バンプ38が形成されている。このバンプ38は
例えば銀ペーストを印刷、乾燥させ、必要であれば重ね
刷りすることにより形成することができる。
The subsequent steps are the same as in Example 1, but
It is desirable that the bump electrodes on the integrated circuit chip side have a temperature difference using solder (alloy) having a lower melting point than the solder bumps 38. For example, when an Sn-based alloy is used for the solder bump 38, an In-based alloy is used for the chip electrode. Also in this case, since the integrated circuit chip 10 is firmly fixed to the wiring board 12 via the polyimide film 34, bonding can be easily performed. (Embodiment 3) FIG. 6 shows the first embodiment shown in FIG.
(B) is still another modified example of the step of FIG.
In this embodiment, a conductive resin bump 38 is formed on the wiring conductor 22 of the wiring film. The bumps 38 can be formed, for example, by printing and drying a silver paste and, if necessary, by overprinting.

【0026】これを開口部42が穿孔された両面接着テ
ープ40を介して、配線基板12と位置合せ後熱圧着す
る。両面接着テープにより配線フィルムと配線基板12
とが接着されるとともに、導電性樹脂バンプ38が配線
基板12の配線導体14(銅、または銅に金メッキ)に
圧接保持されることにより導通が保たれる。
This is aligned with the wiring board 12 via the double-sided adhesive tape 40 having the opening 42 perforated, and then thermocompression-bonded. Wiring film and wiring board 12 with double-sided adhesive tape
And the conductive resin bumps 38 are pressed against and held by the wiring conductors 14 (copper or gold-plated copper) of the wiring board 12 to maintain conduction.

【0027】このとき両面接着テープ40の基材として
は、例えばポリイミド樹脂が好ましく、接着剤は未硬化
若しくは半硬化状態の熱硬化性樹脂が好ましい。その後
は第1の実施例と同様に集積回路チップを接続するが、
チップ電極10のバンプは、前記両面接着テープの耐熱
温度より低い融点の合金を選択することが望ましい。 (実施例4)実施例1〜3では、集積回路チップ10か
らの配線はすべて配線フィルムを通じて行っていたが、
配線ピッチが狭くなった場合には、配線も細くなり電源
や接地の配線抵抗が問題になる場合がある。
At this time, the base material of the double-sided adhesive tape 40 is preferably, for example, a polyimide resin, and the adhesive is preferably an uncured or semi-cured thermosetting resin. After that, the integrated circuit chip is connected as in the first embodiment.
For the bumps of the chip electrode 10, it is desirable to select an alloy having a melting point lower than the heat resistance temperature of the double-sided adhesive tape. (Embodiment 4) In the first to third embodiments, all wiring from the integrated circuit chip 10 is performed through the wiring film.
When the wiring pitch becomes narrow, the wiring becomes thin, and there is a case where the wiring resistance of the power supply and the ground becomes a problem.

【0028】本実施例はこのような場合の改善策であ
り、配線抵抗を下げたい部分を他の接続手段、例えばワ
イヤボンディングで行った例である。このように部分的
に従来技術を併用しても、相対的に実装密度を向上させ
ることができる。またこの場合も集積回路チップ10
は、ポリイミドフィルム34を介して配線基板12にし
っかり固定されているのでボンディングも容易に行え
る。
The present embodiment is an improvement in such a case, in which the portion where the wiring resistance is desired to be reduced is made by another connection means, for example, wire bonding. As described above, even if the conventional technology is partially used, the mounting density can be relatively improved. Also in this case, the integrated circuit chip 10
Is firmly fixed to the wiring board 12 via the polyimide film 34, so that bonding can be easily performed.

【0029】以上いくつかの実施例を紹介したが、本発
明は上記実施例に限られるものではない。配線フィルム
を先に配線基板に接続した後集積回路チップを搭載し、
配線フィルムでチップを包み込む方法であれば、これら
実施例を組み合わせしてもよく一部を等価な手段に置き
換えることもできる。
Although several embodiments have been described above, the present invention is not limited to the above embodiments. After connecting the wiring film to the wiring board first, mount the integrated circuit chip,
As long as the chip is wrapped in a wiring film, these embodiments may be combined or some of them may be replaced with equivalent means.

【0030】[0030]

【発明の効果】本発明の実装方法をとることにより、配
線基板上の集積回路装置の占有面積をほぼチップ面積に
することができる。従来のTAB方式の場合、集積回路
チップ周辺部分での接続となるが、本発明ではチップ下
面が利用できることで、配線の自由度が増し、適正配線
が可能になる。
According to the mounting method of the present invention, the area occupied by the integrated circuit device on the wiring board can be substantially reduced to the chip area. In the case of the conventional TAB method, the connection is made at the peripheral portion of the integrated circuit chip. However, in the present invention, since the lower surface of the chip can be used, the degree of freedom of wiring increases, and proper wiring becomes possible.

【0031】接続部の確認も、配線基板と配線フィルム
の間、および配線フィルムと集積回路チップの間の両方
とも、接続部が陰に隠れることがなく上面より目視等で
容易に行える。
The connection portion can be easily confirmed visually from the upper surface without hiding the connection portion between the wiring board and the wiring film and between the wiring film and the integrated circuit chip.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例に係る実装方法により接
続された集積回路装置実装体のの断面図。
FIG. 1 is a cross-sectional view of an integrated circuit device mounted body connected by a mounting method according to a first embodiment of the present invention.

【図2】本発明の第1の実施例の実装方法を段階的に示
した実装体の断面図。
FIG. 2 is a cross-sectional view of a mounting body showing a mounting method according to the first embodiment of the present invention step by step.

【図3】図2の次の段階を示した実装体の断面図。FIG. 3 is a cross-sectional view of the mounting body showing the next stage of FIG. 2;

【図4】本発明の第1の実施例に使用される配線フィル
ムの平面(底面)図。
FIG. 4 is a plan (bottom) view of a wiring film used in the first embodiment of the present invention.

【図5】本発明の第2の実施例の実装方法の特徴的な段
階を示した実装体の断面図。
FIG. 5 is a cross-sectional view of a mounting body showing characteristic steps of a mounting method according to a second embodiment of the present invention.

【図6】本発明の第3の実施例の実装方法の特徴的な段
階を示した実装体の断面図。
FIG. 6 is a sectional view of a mounting body showing characteristic steps of a mounting method according to a third embodiment of the present invention.

【図7】本発明の第4の実施例の実装方法の特徴的な段
階を示した実装体の断面図。
FIG. 7 is a sectional view of a mounting body showing characteristic steps of a mounting method according to a fourth embodiment of the present invention.

【図8】従来のTAB実装法を示した実装体の断面図。FIG. 8 is a cross-sectional view of a mounting body showing a conventional TAB mounting method.

【符号の説明】[Explanation of symbols]

10…集積回路チップ、12…基板、14…配線導体、
16…絶縁フィルム、18…金バンプ、20…絶縁フィ
ルム、22…配線導体、24…接着剤、26…バンプ電
10 integrated circuit chip, 12 substrate, 14 wiring conductor,
16 ... insulating film, 18 ... gold bump, 20 ... insulating film, 22 ... wiring conductor, 24 ... adhesive, 26 ... bump electrode

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 H01L 23/12 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/12

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 配線基板の集積回路装置搭載領域内に複
数のバンプ電極を形成する工程と、 可撓性フィルムの主面に中央部より端部に向けて形成さ
れた複数の配線導体と、前記配線導体の各々に形成さ
れ、前記中央部に形成された第1の電極及び前記端部に
形成された第2の電極とを有する配線フィルムの前記第
1の電極を、前記配線基板の対応する前記バンプ電極に
接続する工程と、 上面に複数の第3の電極を有する集積回路装置の下面を
接着剤を介して前記配線フィルム上のほぼ中央部に載置
する工程と、 前記配線フィルムの前記端部を前記集積回路装置の周縁
に沿って折り曲げ、前記配線フィルムの前記第2の電極
を前記集積回路装置の対応する第3の電極に接続する工
程と、 を具備するすることを特徴とする集積回路装置の実装方
法。
A step of forming a plurality of bump electrodes in an integrated circuit device mounting area of a wiring board; a plurality of wiring conductors formed on a main surface of a flexible film from a center to an end; The first electrode of the wiring film, which is formed on each of the wiring conductors and has a first electrode formed at the center and a second electrode formed at the end, is connected to a corresponding one of the wiring substrates. Connecting the lower surface of the integrated circuit device having a plurality of third electrodes on the upper surface to a substantially central portion on the wiring film via an adhesive; Bending the end portion along the periphery of the integrated circuit device, and connecting the second electrode of the wiring film to a corresponding third electrode of the integrated circuit device. To implement integrated circuit devices .
【請求項2】 前記配線基板に前記複数のバンプ電極を
形成する際に、前記バンプ電極の頭部が突出する厚さの
絶縁フィルムを、前記基板上の前記集積回路装置搭載領
域に、前記バンプ電極領域を除いて形成することを特徴
とする請求項1記載の集積回路装置の実装方法。
2. The method according to claim 1, wherein the step of forming the plurality of bump electrodes on the wiring substrate includes the step of forming an insulating film having a thickness protruding from a head of the bump electrode on the integrated circuit device mounting area on the substrate. 2. The method according to claim 1, wherein the electrode is formed excluding the electrode region.
【請求項3】 可撓性フィルムの主面に中央部より端部
に向けて形成された複数の配線導体と、前記配線導体の
各々に形成され、前記中央部に形成された第1の電極及
び前記端部に形成された第2の電極とを有する配線フィ
ルムの前記第1の電極にバンプ電極を形成する工程と、 前記配線フィルムの前記バンプ電極を、配線基板に形成
された複数の第3の電極の各々に対応させて接続する工
程と、 上面に複数の第4の電極を有する集積回路装置の下面を
接着剤を介して前記配線フィルムのほぼ中央部に載置す
る工程と、 前記配線フィルムを前記集積回路装置の周縁に沿って折
り曲げ、前記配線フィルムの前記第2の電極を前記集積
回路装置の対応する第4の電極に接続する工程と、 を具備するすることを特徴とする集積回路装置の実装方
法。
3. A plurality of wiring conductors formed on a main surface of a flexible film from a center to an end, and a first electrode formed on each of the wiring conductors and formed on the center. Forming a bump electrode on the first electrode of the wiring film having a second electrode formed on the end portion; and forming a plurality of bump electrodes on the wiring substrate on the first electrode of the wiring film. A step of mounting a lower surface of an integrated circuit device having a plurality of fourth electrodes on an upper surface at a substantially central portion of the wiring film via an adhesive; Bending a wiring film along the periphery of the integrated circuit device, and connecting the second electrode of the wiring film to a corresponding fourth electrode of the integrated circuit device. Mounting method of integrated circuit device
【請求項4】 前記配線フィルムの前記バンプ電極を、
配線基板に形成された複数の第3の電極の各々に対応さ
せて接続する際に、前記バンプ電極の頭部が露出する程
度の厚さの絶縁フィルムを、前記集積回路装置搭載領域
に対応し前記バンプ電極領域を除いた領域の前記絶縁フ
ィルムと前記配線基板との間に介在させることを特徴と
する請求項3記載の集積回路装置の実装方法。
4. The method according to claim 1, wherein the bump electrode of the wiring film is
When connecting corresponding to each of the plurality of third electrodes formed on the wiring board, an insulating film having a thickness such that the head of the bump electrode is exposed corresponds to the integrated circuit device mounting area. 4. The method according to claim 3, wherein the wiring board is interposed between the insulating film and the wiring board in a region other than the bump electrode region.
JP13521895A 1995-06-01 1995-06-01 Mounting method of integrated circuit device Expired - Fee Related JP3251810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13521895A JP3251810B2 (en) 1995-06-01 1995-06-01 Mounting method of integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13521895A JP3251810B2 (en) 1995-06-01 1995-06-01 Mounting method of integrated circuit device

Publications (2)

Publication Number Publication Date
JPH08330361A JPH08330361A (en) 1996-12-13
JP3251810B2 true JP3251810B2 (en) 2002-01-28

Family

ID=15146596

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP3251810B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250694A (en) * 2006-03-14 2007-09-27 Hitachi Cable Ltd Method of manufacturing tape carrier for mounting semiconductor device
JP6950195B2 (en) * 2017-02-16 2021-10-13 昭和電工マテリアルズ株式会社 Metal joints, joints, semiconductor devices and semiconductor devices

Also Published As

Publication number Publication date
JPH08330361A (en) 1996-12-13

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