JP2986661B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2986661B2 JP2986661B2 JP24901293A JP24901293A JP2986661B2 JP 2986661 B2 JP2986661 B2 JP 2986661B2 JP 24901293 A JP24901293 A JP 24901293A JP 24901293 A JP24901293 A JP 24901293A JP 2986661 B2 JP2986661 B2 JP 2986661B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- multilayer wiring
- semiconductor device
- lead frame
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子のパッケ−ジ
ング技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device packaging technology.
【０００２】[0002]
【従来の技術】近年、半導体素子のパッケ−ジング技術
は、これらが搭載される電子機器の変化に対応して大き
く変化しつつある。電子機器は小型軽量化とともにデジ
タル化が大きく進んできているために、パッケ−ジ技術
もさらなる小型、高密度化が望まれている。2. Description of the Related Art In recent years, the packaging technology of semiconductor devices has been greatly changed in response to changes in electronic devices on which these devices are mounted. Since digitalization of electronic devices has been greatly advanced in addition to miniaturization and weight reduction, further miniaturization and higher density of package technology are desired.
【０００３】以下図面を参照しながら、上記した従来の
パッケ−ジング技術の一例について説明する。An example of the above-mentioned conventional packaging technique will be described below with reference to the drawings.
【０００４】図２は従来のパッケ−ジング技術の１例を
示すものである。図２において、２１はリ−ドフレ−ム
であり、このリ−ドフレ−ム２１の中央部に半導体素子
２２はダイボンド樹脂２３によって固定されている。半
導体素子２２の表面に形成されたＡＬ電極２４は、Ａｕ
またはアルミのワイヤ−２５で各リ−ドに電気的な接続
がなされている。そしてこれ全体をモ−ルド樹脂２６に
よって封止する。FIG. 2 shows an example of a conventional packaging technique. In FIG. 2, reference numeral 21 denotes a lead frame, and a semiconductor element 22 is fixed to a central portion of the lead frame 21 by a die bond resin 23. The AL electrode 24 formed on the surface of the semiconductor element 22 is Au
Alternatively, an electrical connection is made to each lead by an aluminum wire-25. Then, the whole is sealed with a mold resin 26.
【０００５】以上のような構造が半導体素子の一般的な
パッケ−ジング方法であるが、最近では、上記したよう
な理由で図３に示すようなパッケ−ジがでてきている。The above-described structure is a general packaging method for a semiconductor device. Recently, a package as shown in FIG.
【０００６】図３において、樹脂によって作られた多層
配線基板３１の中央部に、少なくとも１つ以上の半導体
素子２２が搭載され、半導体素子２２の表面に形成され
たＡＬ電極２４は、Ａｕまたはアルミのワイヤ−２５に
よって、多層配線基板３１上に形成された配線電極３２
に電気的に接続されている。そして半導体素子２２が複
数個搭載された多層配線基板３１の外周部に形成された
外部電極３３と、リ−ドフレ−ム３４とを接続して外部
リ−ドとする。そして半導体素子２２が搭載された面だ
けに保護用樹脂３５を形成する。In FIG. 3, at least one semiconductor element 22 is mounted at the center of a multilayer wiring board 31 made of resin, and an AL electrode 24 formed on the surface of the semiconductor element 22 is made of Au or aluminum. Wiring 25 formed on the multilayer wiring board 31 by the wire 25
Is electrically connected to Then, an external electrode 33 formed on the outer peripheral portion of the multilayer wiring board 31 on which a plurality of semiconductor elements 22 are mounted and a lead frame 34 are connected to form an external lead. Then, the protective resin 35 is formed only on the surface on which the semiconductor element 22 is mounted.
【０００７】このパッケ−ジの特徴としては以下のこと
が上げられる。 (1) パッケ−ジ内部に配線層を持っているために、複数
個の半導体素子を搭載して相互間で結線することができ
るため、容易にマルチチップモジュ−ル化することがで
きる。The features of this package are as follows. (1) Since a wiring layer is provided inside the package, a plurality of semiconductor elements can be mounted and connected to each other, so that a multi-chip module can be easily formed.
【０００８】(2) 各パッケ−ジングされた複数個の半導
体素子を用いてモジュ−ルを形成するより大幅に実装面
積を低減することができるとともに、信号の高速性を向
上させることができる。(2) The mounting area can be greatly reduced as compared with the case where a module is formed by using a plurality of packaged semiconductor elements, and the high-speed signal can be improved.
【０００９】さて、図３に示したパッケ−ジ多層配線基
板３１の外周部に形成された外部電極３３とリ−ドフレ
−ム３４の接続方法についてもう少し詳しく図４を用い
て説明する。Now, a method of connecting the external electrode 33 formed on the outer peripheral portion of the package multilayer wiring board 31 shown in FIG. 3 to the lead frame 34 will be described in more detail with reference to FIG.
【００１０】多層配線基板３１の外周部に形成された外
部電極３３は、銅電極４１上にニッケル４２、金４３が
めっきされた構造となっている。The external electrode 33 formed on the outer peripheral portion of the multilayer wiring board 31 has a structure in which nickel 42 and gold 43 are plated on a copper electrode 41.
【００１１】またリ−ドフレ−ム３４は、４２アロイも
しくは銅で作られているが、一般的には４２アロイが用
いられており、表面には錫金４４がコ−ティングされて
いる。The lead frame 34 is made of 42 alloy or copper, but generally 42 alloy is used, and tin gold 44 is coated on the surface.
【００１２】このような材料構成のもとで両者を位置合
わせし、パルスヒ−トツ−ル４５によって少なくとも１
辺以上を同時に加熱、加圧して接合する。接合は、両者
の界面にＡｕ−Ｓｎ共晶結合を形成せしめる接合であ
る。[0012] Under such a material composition, both are aligned, and at least one is positioned by the pulse heat tool 45.
At the same time, the sides and above are joined by heating and pressing. The bonding is a bonding that forms an Au-Sn eutectic bond at the interface between the two.
【００１３】[0013]
【発明が解決しようとする課題】しかしながら上記のよ
うな接合方法では以下に示すような問題点がある。However, the above joining method has the following problems.
【００１４】リ−ド４５と外部電極３３とを良好なＡｕ
−Ｓｎ共晶接合を行う場合には、その接合部の温度を少
なくとも３５０℃以上に上げる必要がある。The lead 45 and the external electrode 33 are connected to a good Au
When performing -Sn eutectic bonding, it is necessary to raise the temperature of the bonding part to at least 350 ° C or higher.
【００１５】しかしながら、リ−ドフレ−ム３４の材料
に用いられている４２アロイは、金属材料のなかでも熱
伝導率が悪い。However, the 42 alloy used for the material of the lead frame 34 has a poor thermal conductivity among metal materials.
【００１６】また、本構成のような使い方をする場合に
は、約１５０μｍ程度の厚みの４２アロイ材を用いる。In the case of using this configuration, a 42 alloy material having a thickness of about 150 μm is used.
【００１７】このためパルスヒ−トツ−ル４５から供給
された熱量は、すべてそのまま接合部には到達しない。
よって接合部を３５０℃以上に上げるには、その温度以
上にパルスヒ−トツ−ル４５の温度を上げる必要があ
る。Therefore, all the heat supplied from the pulse heat tool 45 does not directly reach the junction.
Therefore, in order to raise the temperature of the junction to 350 ° C. or higher, it is necessary to raise the temperature of the pulse heat tool 45 to that temperature or higher.
【００１８】しかしながら多層配線基板３１は樹脂で形
成されているために耐熱温度が低く、パルスヒ−トツ−
ル４５の温度をそれほど高くすることはできない。However, since the multilayer wiring board 31 is made of resin, the heat resistance temperature is low, and the pulse heat
The temperature of the nozzle 45 cannot be so high.
【００１９】よって上記のよう構成でＡｕ−Ｓｎ共晶接
合を行う場合には、接合条件は極めて狭く、かつどうし
ても多層配線基板３１の耐熱性を考えて接合温度を低く
設定するために、良好なＡｕ−Ｓｎ共晶接合はできてお
らず、接合安定性、接合信頼性は低い。Therefore, when Au-Sn eutectic bonding is performed in the above-described configuration, the bonding conditions are extremely narrow, and the bonding temperature must be set low in consideration of the heat resistance of the multilayer wiring board 31. Au-Sn eutectic bonding has not been achieved, and bonding stability and bonding reliability are low.
【００２０】[0020]
【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置の製造方法は、有機材料からな
る多層配線基板の周辺に形成された最表面が金よりなる
配線電極と前記配線電極に対応した位置に母材が４２ア
ロイからなり前記母材の表面が高熱伝導率材料、錫の順
で覆われたリードを有するリードフレームとを位置合わ
せする工程と、次に少なくとも１辺以上を同時にパルス
ヒートで加熱、加圧し、前記配線電極とリードフレーム
とを接合する工程と、次に前記多層配線基板の中央部に
１個以上の半導体素子を搭載し、前記半導体素子の電極
と前記配線電極から延在した配線とを電気的に接続する
工程とを備えたものである。In order to solve the above problems , a method of manufacturing a semiconductor device according to the present invention comprises an organic material.
The outermost surface formed around the multilayer wiring board made of gold is made of gold
The base material is 42 A at a position corresponding to the wiring electrode and the wiring electrode.
And the surface of the base material is made of a material having a high thermal conductivity and tin.
Align the leadframe with the leads covered with
And then simultaneously pulse at least one side
Heating and pressing with heat, the wiring electrode and the lead frame
And then at the center of the multilayer wiring board
At least one semiconductor element is mounted, and the electrodes of the semiconductor element are mounted.
And the wiring extending from the wiring electrode is electrically connected.
And a process .
【００２１】[0021]
【作用】本発明は上記した構成によってパルスヒ−トツ
−ル４５から供給される熱は高熱伝導率材料によって効
率よく接合部に供給される。これによってパルスヒ−ト
ツ−ル４５の設定温度と接合部温度とをほぼ同一にする
ことができるために多層配線基板３１に損傷を与えるこ
となく良好なＡｕ−Ｓｎ共晶接合を行うことが可能とな
る。According to the present invention, the heat supplied from the pulse heat tool 45 is efficiently supplied to the joint by the high thermal conductivity material. As a result, the set temperature of the pulse heat tool 45 and the junction temperature can be made substantially the same, so that good Au-Sn eutectic bonding can be performed without damaging the multilayer wiring board 31. Become.
【００２２】[0022]
【実施例】以下、本発明の一実施例を図１を参照しなが
ら説明する。図１は、本発明の一実施例における多層配
線基板３１とリ−ドフレ−ム３４の接合状態を示すもの
である。An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a bonding state of a multilayer wiring board 31 and a lead frame 34 in one embodiment of the present invention.
【００２３】多層配線基板３１の外周部に形成された外
部電極３３は、銅電極４１上にニッケル４２、金４３が
めっきされた構造となっている。The external electrode 33 formed on the outer periphery of the multilayer wiring board 31 has a structure in which nickel 42 and gold 43 are plated on a copper electrode 41.
【００２４】銅電極は厚み約３５μｍであり、ニッケル
めっきは約１０〜２０μｍ、金めっきは１〜２μｍ程度
が形成されており、電極全体の大きさとしては２００〜
３００μｍ幅である。The copper electrode has a thickness of about 35 μm, the nickel plating has a thickness of about 10 to 20 μm, and the gold plating has a thickness of about 1 to 2 μm.
The width is 300 μm.
【００２５】また、リ−ドフレ−ム３４の材質には４２
アロイが用いられており、その表面にはまず銅１１が約
１〜３μｍ程度めっきされ、つぎに錫めっき４４が約
０．５〜１．５μｍ程度めっきされた構成になってい
る。The material of the lead frame 34 is 42
An alloy is used, and the surface thereof is formed by first plating copper 11 to about 1 to 3 μm and then tin plating 44 to about 0.5 to 1.5 μm.
【００２６】このような材料構成のもとで両者を位置合
わせし、パルスヒ−トツ−ル４５によって、少なくとも
１辺以上を同時に加熱、加圧して接合する。接合として
はＡｕ−Ｓｎ共晶接合である。With such a material composition, the two are aligned, and at least one side is simultaneously heated and pressed by the pulse heat tool 45 to join them. The bonding is Au-Sn eutectic bonding.
【００２７】この場合、リ−ドフレ−ム３４は４２アロ
イと熱伝導率が悪いが、その表面にめっきされている銅
めっき１１は熱伝導率がよい（両者の熱伝導率は約３０
倍程度の差があり、銅のほうがよい）。In this case, the lead frame 34 has a poor thermal conductivity of 42 alloy, but the copper plating 11 plated on its surface has a good thermal conductivity (both have a thermal conductivity of about 30).
The difference is about twice, copper is better).
【００２８】このため、パルスヒ−トツ−ル４５から供
給される熱は銅めっき１１を伝わって効率よく接合部に
供給される。そして供給された熱で接合部ではＡｕ−Ｓ
ｎ共晶合金１２を形成して接合される。Therefore, the heat supplied from the pulse heat tool 45 is transmitted to the copper plating 11 and is efficiently supplied to the joint. Then, the supplied heat causes Au—S
An n-eutectic alloy 12 is formed and joined.
【００２９】即ちパルスヒ−トツ−ル４５からの熱は、
効率よく接合部に供給されることになり、接合部に加え
る温度以上にパルスヒ−トツ−ル４５を加熱する必要は
なく、多層配線基板３１に損傷を与えることなく良好な
Ａｕ−Ｓｎ共晶合金を形成することができる。That is, the heat from the pulse heat tool 45 is
Since the pulse heat tool 45 does not need to be heated to a temperature higher than the temperature applied to the junction, the Au-Sn eutectic alloy can be efficiently supplied without damaging the multilayer wiring board 31. Can be formed.
【００３０】具体的には接合条件を設定温度で３８０〜
４２０℃、接合時間で０．１〜０．５ｓｅｃで行うと最
も良好な接合を得ることができる。Specifically, the joining conditions are set at 380 to 380 at a set temperature.
The best bonding can be obtained by performing the bonding at 420 ° C. for a bonding time of 0.1 to 0.5 sec.
【００３１】以上より明かな様に、本発明によれば、接
合条件の範囲も広がるとともに接合安定性、接合信頼性
を大幅に向上させることが可能となる。As is clear from the above, according to the present invention, the range of joining conditions can be widened, and the joining stability and joining reliability can be greatly improved.
【００３２】[0032]
【発明の効果】以上のように本発明は接合部に熱伝導率
のよい材料を一層設けることにより、パルスヒ−トツ−
ルから供給する熱を効率よく接合部に供給することがで
きる。これにより以下に示す効果がある。As described above, according to the present invention, by providing a material having a high thermal conductivity at the joint portion, the pulse heat resistance can be reduced.
The heat supplied from the joint can be efficiently supplied to the joint. This has the following effects.
【００３３】１．パルスヒ−トツ−ルの温度を接合部に
良好なＡｕ−Ｓｎ共晶合金を形成するのに必要な温度以
上に上げる必要はないため、多層配線基板に損傷を与え
ることなく接合することができる。1. Since it is not necessary to raise the temperature of the pulse heat tool to a temperature higher than that necessary to form a good Au-Sn eutectic alloy at the joint, the joining can be performed without damaging the multilayer wiring board.
【００３４】２．多層配線基板に損傷を与えることがな
いため接合安定性が大幅に向上する。2. Since the multilayer wiring board is not damaged, the bonding stability is greatly improved.
【００３５】３．また、良好なＡｕ−Ｓｎ共晶合金を効
率よく形成することが可能なため、接合信頼性を大幅に
向上することができる。3. In addition, since a good Au-Sn eutectic alloy can be efficiently formed, joining reliability can be greatly improved.
【図１】本発明の一実施例におけるＰ−ＱＦＰの接合断
面図FIG. 1 is a cross-sectional view of a P-QFP joint according to an embodiment of the present invention.
【図２】従来における半導体素子のパッケ−ジ構造の断
面図FIG. 2 is a cross-sectional view of a conventional semiconductor device package structure.
【図３】従来における半導体素子のパッケ−ジの一種類
であるＰ−ＱＦＰの構造断面図FIG. 3 is a structural sectional view of a P-QFP, which is one type of a conventional semiconductor device package.
【図４】従来におけるＰ−ＱＦＰの接合断面図FIG. 4 is a cross-sectional view of a conventional P-QFP junction.
１１ 銅めっき １２ Ａｕ−Ｓｎ共晶合金 ２１ リ−ドフレ−ム ２２ 半導体素子 ２３ ダイボンド樹脂 ２４ ＡＬ電極 ２５ ワイヤ ２６ モ−ルド樹脂 ３１ 多層配線基板 ３２ 配線電極 ３３ 外部電極 ３５ 保護樹脂 ４１ 銅電極 ４２ ニッケルめっき ４３ 金めっき ４４ 錫めっき ４５ パルスヒ−トツ−ル DESCRIPTION OF SYMBOLS 11 Copper plating 12 Au-Sn eutectic alloy 21 Lead frame 22 Semiconductor element 23 Die bond resin 24 AL electrode 25 Wire 26 Mold resin 31 Multilayer wiring board 32 Wiring electrode 33 External electrode 35 Protective resin 41 Copper electrode 42 Nickel Plating 43 Gold plating 44 Tin plating 45 Pulse heat tool
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/50 H01L 23/12 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/50 H01L 23/12
Claims (1)
形成された最表面が金よりなる配線電極と前記配線電極
に対応した位置に母材が４２アロイからなり前記母材の
表面が高熱伝導率材料、錫の順で覆われたリードを有す
るリードフレームとを位置合わせする工程と、次に少な
くとも１辺以上を同時にパルスヒートで加熱、加圧し、
前記配線電極とリードフレームとを接合する工程と、次
に前記多層配線基板の中央部に１個以上の半導体素子を
搭載し、前記半導体素子の電極と前記配線電極から延在
した配線とを電気的に接続する工程とを備えたことを特
徴とした半導体装置の製造方法。 Surrounding the multilayer wiring substrate made of claim 1 Organic materials
A wiring electrode formed of gold on the outermost surface and the wiring electrode
The base material is made of 42 alloy at a position corresponding to
Has leads covered with high thermal conductivity material, tin in order
Aligning the lead frame with the
Heat and pressurize at least one side simultaneously with pulse heat,
Joining the wiring electrode and the lead frame;
At least one semiconductor element in the center of the multilayer wiring board.
Mounted, extending from the electrode of the semiconductor element and the wiring electrode
And a step of electrically connecting the wiring to the semiconductor device.
Semiconductor device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24901293A JP2986661B2 (en) | 1993-10-05 | 1993-10-05 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24901293A JP2986661B2 (en) | 1993-10-05 | 1993-10-05 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07106489A JPH07106489A (en) | 1995-04-21 |
| JP2986661B2 true JP2986661B2 (en) | 1999-12-06 |
Family
ID=17186699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24901293A Expired - Fee Related JP2986661B2 (en) | 1993-10-05 | 1993-10-05 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2986661B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013051377A (en) * | 2011-08-31 | 2013-03-14 | Rohm Co Ltd | Chip type solid electrolytic capacitor and manufacturing method of the same |
| JP5868274B2 (en) * | 2012-06-29 | 2016-02-24 | 京セラサーキットソリューションズ株式会社 | WIRING BOARD AND ELECTRONIC DEVICE USING THE SAME |
-
1993
- 1993-10-05 JP JP24901293A patent/JP2986661B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07106489A (en) | 1995-04-21 |
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