JP3914458B2 - Method for manufacturing circuit board having heat sink - Google Patents

Method for manufacturing circuit board having heat sink Download PDF

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Publication number
JP3914458B2
JP3914458B2 JP2002136586A JP2002136586A JP3914458B2 JP 3914458 B2 JP3914458 B2 JP 3914458B2 JP 2002136586 A JP2002136586 A JP 2002136586A JP 2002136586 A JP2002136586 A JP 2002136586A JP 3914458 B2 JP3914458 B2 JP 3914458B2
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JP
Japan
Prior art keywords
circuit board
insulating base
mask layer
base material
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002136586A
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Japanese (ja)
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JP2003332503A (en
Inventor
文彦 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Mektron KK
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Nippon Mektron KK
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Priority to JP2002136586A priority Critical patent/JP3914458B2/en
Publication of JP2003332503A publication Critical patent/JP2003332503A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明はICチップなどの電子部品のための放熱板を有する回路基板製造法に関する。
【0002】
【従来の技術とその問題点】
近年、電子機器の小型化と高機能化は益々促進されてきており、そのために回路基板に対する高密度化の要求が高まってきている。高機能化に伴う信号の高速化、消費電力の増加により回路基板の発熱量は増加する。
【0003】
しかしながら、従来の回路基板は実装密度が向上するに従い回路基板の放熱性は低下するという問題があった。これに対して回路基板に放熱板を設ける対策が考えられるが、回路基板の高密度化の妨げになるばかりか、実装部品点数が増加すると、実装コストも増大し、実装時の歩留まりを下げる要因になる。
【0004】
【課題を解決するための手段】
本発明は、上記従来例の問題を好適に解決するための方法を提供するものであって、放熱板を有する回路基板の製造法において、絶縁べ−ス材の少なくとも一方の面に導電層を有する銅張り板に、前記絶縁べ−ス材の少なくとも後の工程で形成される放熱板に位置する箇所に開口を有する第一のマスク層を形成し、前記第一のマスク層を用いて前記絶縁べ−ス材にレ−ザ−加工、プラズマエッチング加工又はウエットエッチング加工により前記第一のマスク層の反対面に位置する前記導電層に至る溝又は孔を形成し前記溝又は孔にめっきを施した後、前記絶縁べ−ス材の少なくとも前記めっきを施された溝又は孔の周囲に位置する箇所に開口を有する第二のマスク層を形成し、前記第二のマスク層を用いて前記絶縁べ−ス材をレ−ザ−加工、プラズマエッチング加工又はウエットエッチング加工により除去することを特徴とする放熱板を有する回路基板の製造法が採用される。
【0005】
また、本発明の他の方法では、放熱板を有する回路基板の製造法において、絶縁べ−ス材の少なくとも一方の面に導電層を有する銅張り板に、前記絶縁べ−ス材の少なくとも後の工程で形成される放熱板に位置する箇所およびその周囲に開口を有する第一のマスク層を形成し、前記第一のマスク層を用いて前記絶縁べ−ス材にレ−ザ−加工、プラズマエッチング加工又はウエットエッチング加工により前記第一のマスク層の反対面に位置する前記導電層に至る開口部を形成し前記開口部の前記絶縁べ−ス材の前記導電層上の放熱板に位置する箇所を除く箇所に放熱板を形成するための溝又は孔状の開口を有する第二のマスク層を形成し、前記溝又は孔状の開口にめっきを施した後、前記第二のマスク層を除去することを特徴とする放熱板を有する回路基板の製造法も採用される。
【0008】
【発明の実施の形態】
以下、図示の実施例を参照しながら本発明をさらに説明する。図1は、本発明の一実施例による放熱板を有する回路基板の製造工程図を示す。回路基板を製造する際に、同図(1)に示すように絶縁ベース材1、導体層2を有する片面銅張り板等を用い、そして絶縁ベース材1をレーザー加工、プラズマエッチング加工又はウエットエッチング加工により溝又は孔加工を施すための所要のマスク層3を絶縁べース材1の上面に形成する。マスク層3は両面銅張り板等を用いて形成することも出来る。
【0009】
そこで、同図(2)に示すようにマスク層3を用いて絶縁ベース材1をレーザー加工、プラズマエッチング加工又はウエットエッチング加工により溝又は孔4の加工を施す。次に、同図(3)に示すようにめっきを行い、溝又は孔4をめっき5で充填し、マスク層3を除去する。
【0010】
次に、同図(4)に示すように第一の面にレーザー加工、プラズマエッチング加工又はウエットエッチング加工によりめっき5の周囲の絶縁ベース材1を除去するために絶縁べース材1の両端の上面にマスク層6を形成する。
【0011】
その後、同図(5)に示すようにマスク層6を用いて、レーザー加工、プラズマエッチング加工又はウエットエッチング加工によりめっき5の周囲の絶縁ベース材1を除去した後、マスク層6を除去する。これにより、導体層2上にはフィン状又は柱状のめっき5が形成されて放熱板となる。
【0012】
このような放熱板を有する回路基板は図2に示す方法も適用することが可能である。先ず、同図(1)のように絶縁べース材1、導体層2からなる片面銅張り板等を用い、その絶縁べース材1の上面両端に所要のマスク層3を形成する。
【0013】
次いで、同図(2)の如く絶縁べース材1にレーザー加工、プラズマエッチング加工又はウエットエッチング加工を施してそこに大きな孔6を形成した段階で、マスク層3を除去する。そこで、同図(3)のように孔6の部位に再度所要のマスク層7を形成する。
【0014】
次に、同図(4)のようにマスク層7の間にフィン状又は柱状のめっき5を施した後、マスク層7を除去すると、同図(5)のように上記実施例と同様な放熱板有する回路基板を構成することができる。
【0015】
図3は上記実施例に示した放熱板を有する回路基板にICチップなどの電子部品8を実装した例を示し、電子部品8は導体層2Aの側に実装され、回路基板の端子部2Bと接続される。
【0016】
図4は、本発明の他の実施例による放熱板を有する回路基板の製造工程図である。回路基板を製造する際に、同図(1)に示すように第一の導体層11、絶縁ベース材10、導体層12を有する両面面銅張り板を用いる。この場合、第一の導体層11が第二の導体層12よりも厚いことが望ましい。そして、第一の導体層11をウエットエッチング加工により溝又は孔加工を施すためのマスク層13を第一の導体層11の面に形成する。
【0017】
そこで、同図(2)に示すようにマスク層13を用いて第一の導体層11をウエットエッチング加工により溝又は孔14の加工を施す。次に、同図(3)に示すようにマスク層13を除去し、第二の導体層12を用いてマスク層15を設ける。
【0018】
その後、同図(4)に示すようにマスク層15を用いて絶縁ベース材10をレーザー加工、プラズマエッチング加工又はウエットエッチング加工により除去して第一の導体層11の底面を露出させる大きな孔16を形成することにより、第一の導体層11にフィン状又は柱状の放熱部を形成した回路基板を構成できる。
【0019】
図5は上記実施例に示した放熱板を有する回路基板にICチップなどの電子部品8を実装した例を示し、電子部品8は第一の導体層11の底面に実装され、第二の導体層12により形成された端子部15Aと接続される。
【0020】
【発明の効果】
本発明による回路基板は、電子部品を実装する部分に放熱板を有しているから、従来の回路基板では困難であった、実装部品点数を増加させたり回路基板の高密度化を妨げることなく、放熱性を向上できる。
【0021】
また、本発明の他の方法によれば、電子部品を実装する部分の絶縁ベース材を除去しているので、従来の回路基板では困難であった実装後の回路基板の厚さを低減することが可能になり、従来の製造方法では困難であった放熱性および実装性を有する回路基板を安価に安定的に提供できる。
【図面の簡単な説明】
【図1】本発明の一実施例による放熱板を有する回路基板の製造工程図。
【図2】本発明の他の実施例による放熱板を有する回路基板の製造工程図。
【図3】本発明の放熱板を有する回路基板に電子部品を実装した説明図。
【図4】本発明の他の実施例による放熱板を有する回路基板の製造工程図。
【図5】図4の放熱板を有する回路基板に電子部品を実装した説明図。
【符号の説明】
1 絶縁べース材
2 導体層
3 マスク層
4 溝又は孔
5 フィン状又は柱状のめっき
6 マスク層
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a circuit board having a heat sink for an electronic component such as an IC chip.
[0002]
[Prior art and its problems]
In recent years, miniaturization and high functionality of electronic devices have been promoted more and more, and therefore, there is an increasing demand for higher density of circuit boards. The amount of heat generated by the circuit board increases with the increase in signal speed and power consumption associated with higher functionality.
[0003]
However, the conventional circuit board has a problem that the heat dissipation of the circuit board decreases as the mounting density increases. In response to this, measures to provide a heat sink on the circuit board can be considered, but this not only hinders the density of the circuit board, but also increases the number of mounted components, which increases the mounting cost and lowers the yield during mounting. become.
[0004]
[Means for Solving the Problems]
The present invention provides a method for suitably solving the problems of the above-described conventional example, and in the method of manufacturing a circuit board having a heat sink, a conductive layer is provided on at least one surface of an insulating base material. Forming a first mask layer having an opening at a position located on a heat radiating plate formed in at least a later step of the insulating base material, and using the first mask layer insulating base - scan material Les - the - machining, plasma etching or wet etching by forming a groove or hole reaching the conductive layer located on the opposite surface of the first mask layer, plating the grooves or holes Then, a second mask layer having an opening is formed at a location located around at least the plated groove or hole of the insulating base material , and the second mask layer is used. Laser processing of the insulating base material Plasma etching or the preparation of a circuit board having a heat sink, and removing by wet etching is employed.
[0005]
According to another method of the present invention, in the method of manufacturing a circuit board having a heat sink, a copper-clad plate having a conductive layer on at least one surface of the insulating base material is provided at least after the insulating base material. Forming a first mask layer having an opening in and around the location located on the heat sink formed in the step, and using the first mask layer to laser process the insulating base material; An opening reaching the conductive layer located on the opposite surface of the first mask layer is formed by plasma etching or wet etching , and a heat sink on the conductive layer of the insulating base material in the opening is formed. A second mask layer having a groove or hole-like opening for forming a heat sink is formed in a place other than the place where it is located , and after plating the groove or hole-like opening, the second mask A heat sink characterized by removing the layer Preparation of a circuit board which is also employed.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be further described with reference to the illustrated embodiments. FIG. 1 is a manufacturing process diagram of a circuit board having a heat sink according to an embodiment of the present invention. When manufacturing a circuit board, a single-sided copper-clad plate having an insulating base material 1 and a conductor layer 2 is used as shown in FIG. 1A, and the insulating base material 1 is laser processed, plasma etched or wet etched. A required mask layer 3 for forming a groove or a hole is formed on the upper surface of the insulating base material 1 by processing. The mask layer 3 can also be formed using a double-sided copper-clad plate or the like.
[0009]
Therefore, as shown in FIG. 2B, the groove or hole 4 is processed by laser processing, plasma etching processing or wet etching processing of the insulating base material 1 using the mask layer 3. Next, plating is performed as shown in FIG. 3 (3), the grooves or holes 4 are filled with plating 5, and the mask layer 3 is removed.
[0010]
Next, as shown in FIG. 4 (4), both ends of the insulating base material 1 are removed on the first surface in order to remove the insulating base material 1 around the plating 5 by laser processing, plasma etching processing or wet etching processing. A mask layer 6 is formed on the upper surface.
[0011]
Thereafter, as shown in FIG. 5 (5), the mask layer 6 is used to remove the insulating base material 1 around the plating 5 by laser processing, plasma etching processing or wet etching processing, and then the mask layer 6 is removed. Thereby, the fin-like or columnar plating 5 is formed on the conductor layer 2 to become a heat radiating plate.
[0012]
The circuit board having such a heat sink can also apply the method shown in FIG. First, as shown in FIG. 1 (1), a single-sided copper-clad plate made of an insulating base material 1 and a conductor layer 2 is used, and a required mask layer 3 is formed on both ends of the upper surface of the insulating base material 1.
[0013]
Next, as shown in FIG. 2B, the mask layer 3 is removed when the insulating base material 1 is subjected to laser processing, plasma etching processing or wet etching processing to form large holes 6 therein. Therefore, a required mask layer 7 is formed again at the hole 6 as shown in FIG.
[0014]
Next, after applying the fin-like or columnar plating 5 between the mask layers 7 as shown in FIG. 4 (4), the mask layer 7 is removed, and the same as in the above embodiment as shown in FIG. 5 (5). A circuit board having a heat sink can be formed.
[0015]
FIG. 3 shows an example in which an electronic component 8 such as an IC chip is mounted on the circuit board having the heat sink shown in the above embodiment. The electronic component 8 is mounted on the conductor layer 2A side, and the terminal portion 2B of the circuit board and Connected.
[0016]
FIG. 4 is a manufacturing process diagram of a circuit board having a heat sink according to another embodiment of the present invention. When manufacturing a circuit board, a double-sided copper-clad plate having a first conductor layer 11, an insulating base material 10, and a conductor layer 12 is used as shown in FIG. In this case, it is desirable that the first conductor layer 11 is thicker than the second conductor layer 12. Then, a mask layer 13 for forming grooves or holes in the first conductor layer 11 by wet etching is formed on the surface of the first conductor layer 11.
[0017]
Therefore, as shown in FIG. 2B, the first conductor layer 11 is processed into a groove or hole 14 by wet etching using the mask layer 13. Next, as shown in FIG. 3C, the mask layer 13 is removed, and the mask layer 15 is provided using the second conductor layer 12.
[0018]
After that, as shown in FIG. 4 (4), the insulating base material 10 is removed by laser processing, plasma etching processing or wet etching processing using the mask layer 15 to expose the bottom surface of the first conductor layer 11. By forming the circuit board, it is possible to configure a circuit board in which fin-like or columnar heat-radiating portions are formed on the first conductor layer 11.
[0019]
FIG. 5 shows an example in which an electronic component 8 such as an IC chip is mounted on the circuit board having the heat sink shown in the above embodiment. The electronic component 8 is mounted on the bottom surface of the first conductor layer 11 and the second conductor. The terminal portion 15 </ b> A formed by the layer 12 is connected.
[0020]
【The invention's effect】
Since the circuit board according to the present invention has a heat sink at the part where electronic components are mounted, it does not increase the number of mounted parts or hinder the increase in density of the circuit board, which is difficult with a conventional circuit board. , Heat dissipation can be improved.
[0021]
Further, according to another method of the present invention, since the insulating base material in the portion where the electronic component is mounted is removed, it is possible to reduce the thickness of the circuit board after mounting, which is difficult with the conventional circuit board. Therefore, it is possible to stably provide a circuit board having heat dissipation and mountability, which has been difficult with the conventional manufacturing method, at low cost.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a circuit board having a heat sink according to an embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of a circuit board having a heat sink according to another embodiment of the present invention.
FIG. 3 is an explanatory diagram in which electronic components are mounted on a circuit board having a heat sink of the present invention.
FIG. 4 is a manufacturing process diagram of a circuit board having a heat sink according to another embodiment of the present invention.
5 is an explanatory diagram in which electronic components are mounted on a circuit board having the heat dissipation plate of FIG. 4;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Insulation base material 2 Conductor layer 3 Mask layer 4 Groove or hole 5 Fin-like or columnar plating 6 Mask layer

Claims (2)

放熱板を有する回路基板の製造法において、絶縁べ−ス材の少なくとも一方の面に導電層を有する銅張り板に、前記絶縁べ−ス材の少なくとも後の工程で形成される放熱板に位置する箇所に開口を有する第一のマスク層を形成し、前記第一のマスク層を用いて前記絶縁べ−ス材にレ−ザ−加工、プラズマエッチング加工又はウエットエッチング加工により前記第一のマスク層の反対面に位置する前記導電層に至る溝又は孔を形成し前記溝又は孔にめっきを施した後、前記絶縁べ−ス材の少なくとも前記めっきを施された溝又は孔の周囲に位置する箇所に開口を有する第二のマスク層を形成し、前記第二のマスク層を用いて前記絶縁べ−ス材をレ−ザ−加工、プラズマエッチング加工又はウエットエッチング加工により除去することを特徴とする放熱板を有する回路基板の製造法。 In a method of manufacturing a circuit board having a heat sink, the copper base plate having a conductive layer on at least one surface of the insulating base material is positioned on the heat sink formed in at least a subsequent step of the insulating base material. a first mask layer having an opening at a position to be formed, the insulating base using said first mask layer - scan material Les - the - processing, the first mask by plasma etching or wet etching forming a groove or hole reaching the conductive layer located on the opposite surface of the layer, after plating in the grooves or holes, the insulating base - around has been subjected to at least the plating of the scan material grooves or holes Forming a second mask layer having an opening at a position located, and removing the insulating base material by laser processing, plasma etching processing or wet etching processing using the second mask layer; Features and Preparation of a circuit board having a heat radiating plate that. 放熱板を有する回路基板の製造法において、絶縁べ−ス材の少なくとも一方の面に導電層を有する銅張り板に、前記絶縁べ−ス材の少なくとも後の工程で形成される放熱板に位置する箇所およびその周囲に開口を有する第一のマスク層を形成し、前記第一のマスク層を用いて前記絶縁べ−ス材にレ−ザ−加工、プラズマエッチング加工又はウエットエッチング加工により前記第一のマスク層の反対面に位置する前記導電層に至る開口部を形成し前記開口部の前記絶縁べ−ス材の前記導電層上の放熱板に位置する箇所を除く箇所に放熱板を形成するための溝又は孔状の開口を有する第二のマスク層を形成し、前記溝又は孔状の開口にめっきを施した後、前記第二のマスク層を除去することを特徴とする放熱板を有する回路基板の製造法。 In a method of manufacturing a circuit board having a heat sink, the copper base plate having a conductive layer on at least one surface of the insulating base material is positioned on the heat sink formed in at least a subsequent step of the insulating base material. A first mask layer having an opening at and around the portion to be formed, and the insulating base material is laser-processed, plasma-etched, or wet-etched using the first mask layer . An opening reaching the conductive layer located on the opposite surface of one mask layer is formed, and a heat radiating plate is provided at a location excluding a location located on the conductive layer of the insulating base material of the opening. Forming a second mask layer having a groove or hole-like opening for forming, plating the groove or hole-like opening, and then removing the second mask layer. A method of manufacturing a circuit board having a board.
JP2002136586A 2002-05-13 2002-05-13 Method for manufacturing circuit board having heat sink Expired - Fee Related JP3914458B2 (en)

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JP2012074539A (en) * 2010-09-29 2012-04-12 Sumitomo Electric Printed Circuit Inc Flexible printed wiring board, electronic apparatus, method for manufacturing the flexible printed wiring board
TWI446495B (en) * 2011-01-19 2014-07-21 Subtron Technology Co Ltd Package carrier and manufacturing method thereof
DE102012205240B4 (en) * 2012-03-30 2016-08-04 Semikron Elektronik Gmbh & Co. Kg Method for producing a substrate for at least one power semiconductor component, method for producing a power semiconductor module and power semiconductor module
US11295963B2 (en) 2016-11-14 2022-04-05 King Abdullah University Of Science And Technology Microfabrication techniques and devices for thermal management of electronic devices

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