JPS6329544A - Semiconductr integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten design time and to implement high integration density, by providing second power source voltage interconnections, which are electrically connected to first power source voltage interconnections at specified parts, and electrically connecting said second power source voltage interconnections and third power source voltage interconnections, which are formed with different conductor layers and whose inner circuits are extended. CONSTITUTION:Interconnections in basic cells 7 and power source voltage interconnections 15 are formed by the process for forming a first interconnection layer. Power source voltage interconnections 4 and 5 and power source voltage reinforcing interconnections are formed by the process for forming a second interconnection layer. The vicinities of input/output buffer circuits 3 are extended in the same direction as the power source voltage interconnections 4. Auxiliary power source voltage interconnections 5 are connected to the power source voltage interconnections 4 at the specified parts. The power source voltage interconnections 5 are electrically connected to the power source voltage interconnections 15, which are extended on basic cell lines 8. Thus the power source voltage interconnections 5 and 15 can be directly connected without contact with the interconnections in the input/output buffer circuits 3. Therefore, the design time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device that employs a master slice method.

[Conventional technology]

Semiconductor integrated circuit devices that use the mask slicing method are
Many memory functions and logic functions can be formed by changing the wiring pattern (mask pattern in the wiring formation process) applied to the master wafer.

The master wafer has a plurality of basic cells formed by one or more semiconductor elements arranged in a first direction to form a basic cell row. The basic cell is composed of complementary MISFETs including, for example, a p-channel MISFET and an n-channel MISFET. A plurality of basic cell rows are arranged at predetermined intervals in the second direction with wiring regions interposed therebetween. Semiconductor integrated circuit devices employing this type of master slicing method are characterized by being able to complete products in a short time in response to requests from users.

Power supply voltage wiring and reference voltage wiring extend in the peripheral area (chip peripheral area) of the semiconductor integrated circuit device, specifically, above the input/output buffer circuit. Power supply voltage wiring and base i1! The voltage wiring is configured so that it is easy to supply power to the input/output buffer circuit and to predetermined internal circuits, and so as not to limit the layout of the signal wiring. The power supply voltage wiring and the reference voltage wiring are configured with a wiring width large enough to substantially cover the input/output buffer circuit in order to reduce potential fluctuations. For example, a circuit operating voltage of 5 [V] is applied to the power supply voltage wiring. For example, a circuit ground voltage of 0 [V] is applied to the reference voltage wiring, and is arranged on the outer periphery of the power supply voltage wiring.

2. Description of the Related Art In a semiconductor integrated circuit device, a predetermined circuit is usually formed through a two-layer wiring formation process (for example, aluminum wiring). The power supply voltage wiring and the reference voltage wiring are formed in the wiring formation process on the 2Mth day, similarly to the wiring connecting between basic cells or between logic circuits and memory circuits formed in basic cells. In the wiring formation step on the 1Mth day, for example, the wiring in the basic cell, the ff1l voltage wiring and the reference voltage wiring extending on the basic cell column are formed.

A semiconductor integrated circuit device employing the master slice method is described, for example, in Japanese Patent Application No. 121758/1983.

[Problem that the invention seeks to solve]

The present inventor has developed the results of studies on such technology.

It was found that the following problem occurred.

In the aforementioned semiconductor integrated circuit device, power supply voltage wiring and base 11! The voltage wiring extends above the input/output buffer circuit and is formed in the second layer wiring formation process. The wiring within the input/output buffer circuit is formed in the wiring formation process on the 1Mth day. For this reason.

Power supply voltage wiring that extends over the human output buffer circuit.

Each of the reference voltage wiring and the power supply voltage wiring extending on the basic cell row, base 41! The connections between each of the voltage wires become very electrical. That is, in order to avoid contact with the wiring in the human output buffer circuit, it is not possible to easily connect the two in the input/output buffer circuit area, resulting in a problem of increased design time. Furthermore, if an attempt is made to easily connect the two, it becomes necessary to route the power supply voltage wiring and the base voltage wiring extending from the basic cell array so as to bypass the input/output buffer circuit portion. As a result, the area occupied by the wiring increases, resulting in a problem that the degree of integration of the semiconductor integrated circuit device is significantly reduced.

□In particular, in the filling method (embedding method) in which basic cells are spread over the entire surface in advance and basic cells or rows of basic cells are used as wiring areas as necessary, the above-mentioned problem is significant. Logic circuits and memory circuits (active areas) are formed in columns, and it is unclear on which basic cell columns power supply voltage wiring and reference voltage wiring should be extended.
This is because the connecting portion between the two cannot be specified.

An object of the present invention is to provide a technique that can shorten design time and achieve high integration in a semiconductor integrated circuit device that employs a master slice method.

Another object of the present invention is to provide a power source ffi that extends the power supply voltage wiring and internal circuitry extending around the peripheral portion of the semiconductor integrated circuit device.
The purpose of the present invention is to provide a technology that allows easy connection with voltage wiring.

Another object of the present invention is a technique capable of reducing the area occupied by the power supply voltage wiring extending around the peripheral part of a semiconductor integrated circuit device, the power supply voltage wiring extending the internal circuitry, and the power supply voltage wiring extending the internal circuit. Our goal is to provide the following.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device that adopts the master slice method, in addition to the first power supply voltage wiring extending over the output buffer circuit, a wire extending near the input/output buffer circuit in the same direction as the first power supply voltage wiring is A second power supply voltage wiring is provided which is electrically connected to the first power supply voltage wiring at a predetermined portion, and is formed of a different conductive layer from the second power supply voltage wiring and extends an internal circuit. The third power supply voltage wiring is electrically connected to the third power supply voltage wiring.

[For production]

According to the above means, the second power supply voltage wiring connected to the first power supply voltage wiring and the third power supply voltage wiring can be connected without contacting the wiring in the input/output buffer circuit. Therefore, it is possible to easily connect the two and eliminate the need for wiring, thereby shortening the design time and improving the degree of integration.

Hereinafter, the structure of the present invention will be described along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device that employs a stacking method and a master slicing method.

In addition, in the plan, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I]

FIG. 1 (schematic configuration diagram) shows a semiconductor integrated circuit device employing a master slice method, which is Embodiment I of the present invention.

As shown in FIG. 1, a semiconductor integrated circuit device 1 employing the master slice method has a plurality of external terminals (ponding pads) 2 and input/output buffer circuits 3 arranged in the peripheral portion.

Further, in the peripheral part of the semiconductor integrated circuit bag 5!1 and above the input/output buffer circuit 3, the power supply voltage wiring 4 extends so as to substantially cover the input/output buffer circuit 3.

The power supply voltage wiring 4 includes a power supply voltage wiring (Vcc) 4A and a reference voltage wiring (Vss) extending on the outer periphery of the power supply voltage wiring (Vcc) 4A.
It is composed of 4B. For example, a circuit operating voltage of 5 [V] is applied to the power supply voltage wiring 4A. For example, a circuit ground potential OEV] is applied to the reference voltage wiring 4B. The human output buffer circuit 3 is a MISF
It is composed of ET, complementary MISFET, bipolar transistor, etc.

It is a part inside the power supply voltage wiring 4.

An auxiliary power supply voltage wiring 5 extending in the same direction as the power supply voltage wiring 4 is provided near the human output buffer 7 circuit 3 (near the portion other than the input/output buffer circuit). The power supply voltage wiring 5 is the power supply voltage wiring! 1A (Vcc)
SA and the reference voltage wiring (V
ss) 5B. As will be described later, the power supply voltage wiring 4A and it! The 11JX voltage wiring 5A, the reference voltage wiring 4B, and the reference voltage wiring 5B are each electrically connected at a predetermined portion.

In the center of the semiconductor integrated circuit device 1, a plurality of power supply reinforcing wirings are arranged at predetermined intervals in the column direction and extend in the row direction.
116 are provided. The power supply reinforcing wiring 6 includes the power supply voltage reinforcing wiring (Vcc) 6A and the reference voltage reinforcing wiring! (v
ss) 6B as one set.

In the center of the semiconductor integrated circuit device 1, a plurality of basic self cells are arranged. A plurality of basic cells are arranged in the column direction to form a basic cell column 8. This basic cell row 8 is arranged so as to be defined between the power supply reinforcing wirings 6. Basic cell row 8 is.

Multiple lines are arranged in the row direction.

The semiconductor integrated circuit device 1 employing the master slicing method configured as described above is configured in a so-called lining method (or embedding method) in which a plurality of basic self cells are arranged in the column direction and the row direction. The basic self or basic cell row 8 can be configured in a block manner with a logic circuit Logic, a memory circuit ROM, a RAM, and the like. The basic self or basic cell row 8 is used as an allocation aMi area as required. The wiring area is configured to pass wiring connecting between basic cells 7 or between logic circuits and memory circuits. Layering type semiconductor integrated circuit device i! 1 is a logic circuit
, memory circuits ROM, RAM, etc. can be condensed and configured in blocks. Further, logic circuits Logic, memory circuits ROM, RAM, etc. can be sufficiently connected to each other simply by wiring provided within the basic self. In other words, it is a semiconductor integrated circuit bag that uses the filling method! i! 1 can shorten the wiring length and obtain extremely high area usage efficiency.

The wiring provided in the basic cell, which will be described later, is the power supply voltage wiring extending over the basic cell row 8! Each of (15) is formed in the first layer wiring formation process.

The 1Nth wiring formation step uses, for example, aluminum wiring. The power supply voltage wiring 4.5 and the power supply voltage reinforcing wiring 6 are formed in the second layer wiring formation process. Moreover, the husband and wife of the wiring that connects between the basic cells or between the circuits formed by the basic cells are formed in the 1M-th and 2N-th wiring formation steps. In the process of forming the second layer wiring, aluminum wiring, for example, is used as in the process of forming the 1Nth wiring. Further, the wiring formed in the first or second layer wiring formation process is doped with a predetermined additive (Cu.

It may also be composed of an aluminum film containing Si).

The basic self is configured as shown in FIG. 2 (plan view of main parts). The basic self consists of four P-channel MIs.
SFET Qp, ~Q p a and four n-channel M
It is composed of complementary MISFETs consisting of ISFETQnr-Qn4.

The MISFET Qp is an n-type transistor provided on the main surface of an n-type semiconductor substrate 9 in a region surrounded by a field insulating film 11.
It is formed in a type well region 10 and consists of a gate insulating film, a gate electrode 12, and a p' type source and drain region 13. The source or drain region 13 of the MISFETQp is configured integrally with the source or drain region 13 (or drain or source region 13) of another adjacent MISFETQP.

M I S F E T Q n is formed in the p-type well region 10A provided on the main surface of the semiconductor substrate 9 in a region surrounded by the field isolation film 11, and includes a gate insulating film,
It is composed of a gate electrode 12 and an n' type source region and drain region 14. The source region or drain region 14 of MISFETQn is connected to other adjacent MISFETQ
n source region or drain region 14 (or drain region or source region 14). In other words.

The basic self-controller is designed to allow a four-person NAND gate circuit to be constructed.

In addition, in the present invention, the basic self may be made to be able to configure a two-man power NAND gate circuit, a three-man power NAND gate circuit, etc.

t; on the basic cell row 8 is as shown by the dotted line in FIG.
! Ti! The iX voltage wiring 15 extends. The power supply voltage wiring LA15 includes a power supply voltage wiring (Vcc) 15A extending in the column direction on the MISFETQP, and the MISFET QP.
The reference voltage wiring (Vss) 15B extends in the column direction on the FETQn. As mentioned above, the power supply voltage wiring 15 is the first M! It is formed in the second wiring formation process.

Specifically, each of the power supply voltage wiring source voltage wiring LA15 is configured as shown in FIG. 3 (partial reproduction).

As mentioned above, power supply voltage wiring A4 (4A and 4B)
is constructed by extending from the upper part of the input/output buffer circuit 3.

The power supply voltage wiring 5 is configured to extend in the vicinity of the crowd buffer circuit 3 in the same direction as the direction in which the power supply voltage wiring 4 extends. In order to reduce the area occupied by the ffi source voltage wiring 5 as much as possible, the wiring width is considerably smaller than that of the power supply voltage wiring 4. Power supply voltage wiring 4A
The power supply voltage wiring 5A is a wiring formed in the first layer wiring formation process. It is electrically connected at 16A. Reference voltage distribution! 4B and the reference voltage wiring 5B are similarly electrically connected by a wiring 16B formed in the first layer wiring formation process. The husbands of the wirings 16A and 16B are connected to predetermined portions,
Specifically, they are connected in the form of a ladder between every three input/output buffer circuits or every predetermined number of three input/output buffer circuits. By increasing the number of these connections, it is possible to reduce disconnections due to migration, potential fluctuations, etc., so that the power supply voltage wiring 5 can be configured with a smaller wiring width. Each of the wirings 16A and 16B is configured so as not to contact the wiring LA (the wiring formed in the first layer wiring formation process) in the input/output buffer circuit 3.

Further, each of the distribution lines f$16A and 16B may be provided in a predetermined area within the input/output cover sofa circuit 3 within a range that does not contact the wiring within the input/output cover sofa circuit 3.

The power supply voltage wiring 5 (5A, 5B) is directly and substantially linearly connected to the power supply voltage wiring 15 (15A, 15B) extending on the basic cell row 8. That is, the power supply voltage wiring 5 is connected to the power supply voltage wiring 15 in a small area between the input/output buffer circuit 3 and the basic cell row 8 (lower part of the power supply voltage wiring 5). In other words, the connection between the two.

This is done so that it does not come into contact with the wiring inside the input/output buffer circuit 3.

In this way, apart from the power supply voltage wiring 4 extending above the input/output buffer circuit 3, the power supply voltage wiring 4 extends near the input/output buffer circuit 3 in the same direction as the power supply voltage wiring 4. An auxiliary power source @voltage wiring A5 is provided, which is electrically connected to the power supply voltage wiring 5 at a predetermined portion with the power supply voltage wiring 5, and a power voltage wiring LA15 extending over the basic cell array 8 (internal circuit). By electrically connecting it, it can be connected directly and linearly without touching the wiring inside the input/output buffer circuit 3.
Since the power supply voltage wirings 5 and 15 can be connected, the two can be easily connected. In other words, not to mention the artificial wiring layout design.

Automatic wiring layout design by computer (D
Since A) can be easily performed, the design time can be shortened. Moreover, the connection between the two is directly and linearly performed without contacting the wiring in the human output para-flash circuit 3. l! Since it is possible to eliminate the need to route the source voltage wiring 15 by detouring it, the area occupied by the wiring can be reduced and the degree of integration of the semiconductor integrated circuit device can be improved.

A basic cell row 8A (portion indicated by a dotted line) shown in FIG. 3 is a portion of the basic cell row 8 formed as a wiring slope. This basic cell row (wiring region) 8A is configured so that the wiring a16c formed in the first layer wiring formation process (or the second layer wiring formation process) extends.

In addition, in the present invention, the above-mentioned auxiliary m! The ffi pressure wiring 5 may also be configured.

Further, the present invention may configure the power supply voltage wiring a4 extending over the human output buffer circuit 3 by the reference voltage wiring 4B and the power supply voltage wiring 4A extending slightly from its outer periphery. good.

[Example II] This example (2) is based on the power supply voltage wirings 4 and 5 of Example I.
This is another embodiment of the present invention in which the area required for is reduced.

A semiconductor integrated circuit device employing the master slicing method, which is Embodiment 2 of the present invention, is shown in FIG. 4 (partial schematic diagram).

The semiconductor integrated circuit device 1 of Example II is constructed as shown in FIG. In other words, input/output cover sofa circuit 3
The power supply voltage wiring 4A inside the power supply voltage wiring 4 extending above the input/output buffer circuit 3 and the power supply voltage wiring 5 extending near the input/output buffer circuit 3. ! ! The source voltage wiring 5A is integrally constructed. In other words, electric i1JXm voltage wiring 4A
is configured so that a part of the C voltage ('rXm voltage wiring 5A portion) extends to the outside of the human output buffer circuit 3.

The semiconductor integrated circuit device 1 employing the master slicing method configured in this manner can obtain substantially the same effects as those of the first embodiment. In addition, by integrally configuring the power supply voltage wiring 4A and the power supply voltage wiring 5A, there is no need for a separate dimension between the two, so the area occupied by the power supply voltage wiring a4 and 5 can be reduced, and semiconductor integration can be achieved. The degree of integration of the circuit device 1 can be further improved.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to a semiconductor integrated circuit device that employs a stacking method or a master slicing method;
A wiring area is provided between the basic cell columns.

The present invention can be applied to a semiconductor integrated circuit device that employs a master slice method.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are as follows.

In a semiconductor integrated circuit device that adopts the master slice method, the second power supply voltage wiring and the third power supply voltage wiring connected to the second power supply voltage wiring can be connected without touching the wiring in the human output buffer circuit. so you can connect
The two can be easily connected and the need for routing wiring can be eliminated, thereby shortening the 5t9 measurement time and increasing the degree of integration.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device adopting a mask slicing method according to a first embodiment of the present invention. FIG. 2 is a plan view of a main part of the basic cell shown in FIG. 1. FIG. , a partial schematic diagram of the semiconductor integrated circuit device shown in FIG. 1, and FIG. 4 is a partial schematic diagram of a semiconductor integrated circuit device employing the mask slicing method, which is Embodiment 2 of the present invention. In the figure, l: semiconductor integrated circuit device, 3: input/output buffer circuit, 4.4A, 5.5A, 15.15A...
Power supply voltage wiring, 4B, 5B, ISB... Base voltage wiring, 6... Electric S voltage reinforcement wiring, 7... Basic cell,
8: Basic cell row, 16A to 16C: Wiring. 7, 100゛.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device employing a master slice method, a first power supply voltage wiring to which a fixed potential is applied extends above a plurality of input/output buffer circuits arranged in the peripheral area. and is formed of the same conductive layer as the first power supply voltage wiring and extends in the same direction near the input/output buffer circuit,
A second power supply voltage wiring electrically connected to the first power supply voltage wiring at a predetermined portion is provided, the second power supply voltage wiring is formed of a different conductive layer from the second power supply voltage wiring and extends within the internal circuit; A semiconductor integrated circuit device comprising a third power supply voltage wiring electrically connected to the second power supply voltage wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein the second power supply voltage wiring has a smaller wiring width than the first power supply voltage wiring. 3. A patent claim characterized in that the first power supply voltage wiring and the second power supply voltage wiring are electrically connected by a wiring formed of the same conductive layer as the third power supply voltage wiring. The semiconductor integrated circuit device according to scope 1. 4. The third power supply voltage wiring is configured to extend over a basic cell row formed by arranging a plurality of basic cells in a predetermined direction.
2. The semiconductor integrated circuit device described in 2.