JPH07153926A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the development period and to raise the degree of integration by raising the degree of freedom of the connection between primitive cells and wiring. CONSTITUTION:For primitive cells 41, connecting terminals 610 having a plurality of connection positions in their row direction are formed by the use of first wiring arranged in a wiring channel region 5. The electrodes 4G of elements constituting the primitive cells 41 are drawn out up to the wiring channel region 5, and there these connecting terminals 610 are connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an application specific (ASIC) semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device adopting a gate array system or a standard cell system standardizes a basic element structure as a primitive cell, and various kinds of patterns can be obtained by simply changing a wiring pattern connecting the plurality of primitive cells. A logical function can be formed. The primitive cell is n
Channel MOSFET (Metal Oxide Semiconduct
or Filde Effect Transistor) and p channel M
It has an OSFET. That is, the primitive cell is composed of so-called CMOS. The primitive cell can form a specific logic function, for example, a logic circuit such as an inverter circuit, a NAND gate circuit, a flip-flop circuit, and a latch circuit. If the wiring channel method is adopted,
A plurality of the primitive cells are arranged in a column direction, and a plurality of the primitive cells are arranged in a row direction with a wiring channel region interposed.

The intra-cell wiring connecting the inside of the primitive cell and the outside-cell wiring connecting the outside of the primitive cell are
It is automatically formed in an automatic placement and routing system using a computer. For example, when using a two-layer structure aluminum wiring, the wiring extending in the column direction of the cell inner wiring and the cell outer wiring is formed by the first layer aluminum wiring. The latter outside-cell wiring is arranged in the wiring channel region, and a plurality of outside-cell wirings are arranged in this wiring channel region. The wiring extending in the row direction of the extra-cell wiring is formed by the second layer aluminum wiring. A plurality of the out-cell wirings are arranged in the column direction on the wiring channel region and the primitive cell.

Development of a semiconductor integrated circuit device having such a structure is carried out by automatically arranging primitive cells and wirings according to a predetermined logic by using an automatic layout and wiring system. The connection between the primitive cell and the outside-cell wiring is performed by connecting the outside-cell wiring to the connection terminals (input / output pins, grid in the automatic placement and routing system) of the primitive cell.

[0005]

However, the following points have not been taken into consideration in the above-described semiconductor integrated circuit device.

In order to reduce the cell area of the primitive cell, the number of wire connection terminals is reduced, and moreover, the wire connection terminal is arranged in the central portion of the primitive cell due to the restriction of the layout of the power supply wiring. The power supply wiring is formed of a first layer wiring extending in the column direction on the primitive cells, and the power supply wiring supplies an operation power supply and a reference power supply to the primitive cells. By adopting such a layout, when connecting the connection connecting terminals of the primitive cell to the cell outside wiring (first layer wiring) in the wiring channel area, the power supply wiring is extended along the primitive cell in the row direction. A second layer wiring that crosses is interposed.

For this reason, firstly, when the wiring outside the cell is connected to the connection connection terminal of the primitive cell, the second layer wiring (through wiring) that crosses this primitive cell cannot be formed. Secondly, similarly, when the wiring outside the cell is connected to the connection connection terminal of the primitive cell, the first layer wiring as the wiring inside the cell cannot be passed through this portion. In either case, detour wiring is required, which not only reduces the degree of freedom in development but also reduces the efficiency of use of primitive cells. A decrease in the degree of freedom in development lengthens the development period, and a decrease in the efficiency of use of primitive cells decreases the degree of integration.

The present invention has been made to solve the above problems, and in a semiconductor integrated circuit device for a specific application, the degree of freedom of connection between a primitive cell and a wiring is improved. , The purpose is to provide a technology capable of shortening the development period and improving the degree of integration.

[0009]

In order to achieve such an object, according to the present invention, a plurality of primitive cells are arranged in a column direction along a wiring channel region and extend in the wiring channel region in the column direction. A plurality of first wirings arranged in the row direction, and a plurality of second wirings extending in the row direction on the wiring channel region and the primitive cells and formed in an upper layer of the first wirings in the column direction. In a special-purpose semiconductor integrated circuit device for arranging and forming a predetermined logic function by changing a connection pattern of a first wiring and a second wiring connected to the primitive cell, in the primitive cell, in the wiring channel region. It is characterized in that a connection terminal for connection formed of the arranged first wiring and having a plurality of connection positions in the column direction is provided. The connection terminal is connected to a portion where an electrode of an element forming a primitive cell is extended to a wiring channel region.

[0010]

According to the present invention, in a semiconductor integrated circuit device for a specific application, even if one of the first wiring and the second wiring is connected to one of the connection terminals of the wiring connection terminal outside the cell, the wiring connection is made. The second wiring can be passed through the region of the other one connection position of the terminal. Further, since the connection connection terminals of the primitive cell are arranged in the wiring channel region, the in-cell wiring, which is the first wiring, can pass through the central portion of the primitive cell. As a result, detour wiring can be reduced and the degree of freedom in development can be improved.
Moreover, the use efficiency of the primitive cell can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

This embodiment adopts a gate array system,
Further, it is an embodiment in which the present invention is applied to a semiconductor integrated circuit device adopting a wiring channel system. FIG. 1 shows a plan layout of a semiconductor integrated circuit device which adopts a gate array method and a wiring channel method.

The semiconductor integrated circuit device 1 is mainly composed of a semiconductor substrate made of single crystal silicon. The semiconductor substrate is formed in a flat rectangular shape. In the most peripheral area of this semiconductor substrate, a plurality of external terminals (bonding pads) 2
Are arranged. In the peripheral area of the semiconductor substrate,
A plurality of input / output circuits (buffer circuits) 3 are arranged in a region inside the region in which the external terminals 2 are arranged.

The central region of the semiconductor substrate constitutes a logic circuit region. In this logic circuit area, a plurality of standardized primitive cells 41 are arranged. Primitive cell 41
Are arranged in the column direction (horizontal direction in FIG. 1), and the primitive cells 41 arranged in the plurality form the primitive cell row 4. In addition, this primitive cell column 4 has a wiring channel region (wiring formation region) 5 interposed therebetween in the row direction (see FIG.
Multiple lines are arranged in the middle and vertical directions.

The primitive cell 41 is a logic circuit having a predetermined logic function, for example, an inverter circuit, a NAND.
A gate circuit, a flip-flop circuit, a latch circuit, or the like can be formed. FIG. 2 shows a planar layout of an example of the primitive cell 41. The primitive cell 41 includes two p-channel MISFETs (Metal Insulator Semiconductors).
onductor Filde Effect Transistor) 42 and 2
The n-channel MISFETs 43 are provided. The two p-channel MISFETs 42 of the primitive cell 41 share one source region or drain region of both, and the two p-channel MISFETs 42 are electrically connected in series. Each of the two p-channel MISFETs 42 is mainly composed of a gate insulating film (not shown), a gate electrode 4G, and a pair of p-type semiconductor regions 4P used as a source region and a drain region. In this embodiment, the gate electrode 4G is formed of a polycrystalline silicon film. The gate electrode 4G is a composite film having a polycrystalline silicon film and a refractory metal silicide film (MoSi film, WSi film, etc.) provided on the surface thereof,
It may be formed of other so-called gate material such as a single layer refractory metal silicide film.

Similarly, two n's of the primitive cell 41 are
The channel MISFET 43 shares one of the source region and the drain region of the two, and has two n-channel MISFEs.
T43 is electrically connected in series. Each of the two n-channel MISFETs 43 is mainly composed of a gate insulating film, a gate electrode 4G, and a pair of n-type semiconductor regions 4N used as a source region and a drain region.

When a two-layer wiring structure, for example, a two-layer wiring structure of aluminum wiring (or aluminum alloy wiring) is adopted, in the wiring channel region 5, the first layer wirings 614, 615 extending in the column direction, etc. A plurality of can be arranged in the row direction. The first layer wirings 614, 615, etc. arranged in the wiring channel region 5 form external cell wirings that connect the primitive cells 41. Second layer wiring 62
0, 621, 623, etc. extend in the row direction and are arranged in the column direction in the upper part of the wiring channel region 5 and the upper part of the primitive cell 41. Similarly, the second layer wirings 620, 621, 623, etc. form the outside-cell wiring. In addition, the p-channel MIS in the primitive cell 41
Connection between transistors, such as connection between the FET 42 and the n-channel MISFET 43, is performed by the first layer wiring or the second layer wiring.

The first layer wiring 615 and the like and the second layer wiring 623 and the like are electrically connected through a connection hole (through hole or via hole) 72.

Power supply lines 612 and 613 are arranged above the primitive cell 41. The power supply wiring 612 extends in the column direction above the p-channel MISFET 42. The power supply wiring 612 supplies operating power. The power supply wiring 613 extends in the column direction above the n-channel MISFET 43. The power supply wiring 613 supplies a reference power supply.

In the semiconductor integrated circuit device 1 configured as described above, the connection connecting terminals 610 mainly for the outside-cell wiring of the primitive cell 41 are arranged in the wiring channel region 5. The connection connection terminal 610 is the first layer wiring 614.
And the like are formed by the first wiring layer which is the same wiring layer. The connection connection terminal 610 is formed in an elongated shape in the column direction similarly to the first layer wiring 614 and the like, and the second layer wiring 62 is formed.
It has connection positions (input / output pins or grids in an automatic placement and routing system) at the same pitch as the pitch where 0, 621, 623, etc. are arranged. One wire connection terminal 610 has two or more connection positions in at least the column direction (this embodiment has two connection positions).

The connection connection terminal 610 is connected in a portion where the ends of the gate electrodes 4G of the p-channel MISFET 42 and the n-channel MISFET 43 of the primitive cell 41 are extended to the wiring channel region 5 and overlapped with this region. The connection connection terminal 610 and the gate electrode 4G are electrically connected through the connection hole 71.

In other words, the connection connecting terminal 610 is the primitive cell 4 in the wiring channel region 5 in other words.
It is formed by using the first layer wiring 610 on the first side.

By providing the connection terminals 610 extending to the wiring channel region 5 in the primitive cell 41, firstly, the second layer wirings 620 and 6 are formed.
The connection of 21 can be connected directly without the need for bypass wiring.
Secondly, even if there is a second layer wiring 623 that passes above the primitive cell 41, this second layer wiring 6
The primitive cell 41 located under 23 can be connected through another wiring. Further, thirdly, the connection between the adjacent primitive cells 41 can be easily performed by the connection connection terminal 611 obtained by extending the connection connection terminal 610 in the column direction.

Next, a method of forming the semiconductor integrated circuit device 1 adopting the above-mentioned gate array method will be briefly described with reference to FIG. 3 (flow chart).

First, a net list is created (101). The netlist is created by converting the circuit information of the logic function mounted on the semiconductor integrated circuit device 1 into the information that can be handled by the automatic placement and routing system.

Second, using an automatic placement and routing system,
Cells are automatically arranged based on the netlist (102). As the cells, the primitive cell 41 and the input / output circuit 3 are arranged. The automatic placement of these cells is performed based on the information stored as the floor plan (103), and at this time, the cell information is read from the cell library (104). The cell library stores information on the primitive cells 41 in which the above-mentioned connection terminals 610 are overlapped with the wiring channel region 5, information on the input / output circuit 3, and the like.

When the logic circuit is automatically placed, fourth, automatic wiring is performed in the automatic placement and routing system (1
05). That is, the first layer wiring 614 and the like, the second layer wiring 620 and the like are arranged. As a result, the chip layout is completed (106).

Then, sixthly, a manufacturing mask is created based on the information completed by the automatic placement and routing system (107), and a manufacturing process is performed using this mask (108).

As a result of the series of steps, the semiconductor integrated circuit device 1 adopting the gate array method is completed.

As described above, in the semiconductor integrated circuit device 1 adopting the gate array system, the connection connecting terminals 6 are provided.
Even if one of the first layer wiring and the second layer wiring outside the cell 620 or the like is connected to one connection position of No. 10, the second line is formed in the area of the other connection position of the connection terminal 610. The layer wiring 623 and the like can be passed. Further, since the connection connection terminal 610 of the primitive cell 41 is arranged in the wiring channel region 5, the cell inner wiring which is the first layer wiring can pass through the central portion of the primitive cell 41. As a result, the number of bypass wirings can be reduced, the degree of freedom in development can be improved, and the use efficiency of the primitive cell 41 can be improved.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made without departing from the scope of the invention. For example, according to the present invention, in the primitive cell 41 shown in FIG.
The connection terminal 610 for connection on the left side of 0 may be arranged shifted in the row direction by one pitch (corresponding to the pitch of the first layer wiring).

Further, the present invention can be applied not only to the gate array method but also to a semiconductor integrated circuit device adopting other methods such as a master slice method, a standard cell method, a custom method and an ASIC method.

[0033]

As described above, according to the present invention,
In the semiconductor integrated circuit device for a specific application, by improving the degree of freedom of connection between the primitive cell and the wiring, the development period can be shortened and the degree of integration can be improved.

[Brief description of drawings]

FIG. 1 is a plan layout view of a semiconductor integrated circuit device that employs a gate array system according to an embodiment of the present invention.

FIG. 2 is a layout diagram of a primitive cell of the semiconductor integrated circuit device.

FIG. 3 is a flowchart showing a method for forming the semiconductor integrated circuit device.

[Explanation of symbols]

 1 Semiconductor Integrated Circuit Device 4 Primitive Cell Column 41 Primitive Cell 42,43 MISFET 4G Gate Electrode 4P, 4N Semiconductor Region 5 Wiring Channel Region 610, 611 Connection Terminals 614, 615 First Layer Wiring 620, 621, 623 Second Layer wiring

Claims (2)

[Claims] 1. A plurality of primitive cells are arranged in a column direction along a wiring channel region, a plurality of first wirings extending in the column direction are arranged in the wiring channel region, and a plurality of first wirings are arranged in a row direction. A plurality of second wirings extending in the row direction on the upper and the primitive cells and formed in the upper layer of the first wirings are arranged in the column direction, and the first wirings and the second wirings connected to the primitive cells are arranged. In a special-purpose semiconductor integrated circuit device for forming a predetermined logic function by changing a wiring pattern, a plurality of wiring lines formed in the primitive cell by a first wiring arranged in the wiring channel region and arranged in a column direction are provided. A semiconductor integrated circuit device for specific use, which is provided with a terminal for wire connection having a connection position. 2. The connection-specific connection terminal according to claim 1 is connected to a portion where an electrode of an element forming a primitive cell is drawn out to a wiring channel region, and a semiconductor integrated circuit for a specific application. apparatus.