JPH07106521A - Cell base designed semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To insert a bypass capacitor without increasing the chip size by a method wherein capacitor cells are arranged on a wiring region using cell base design technique. CONSTITUTION:A power source wire 21 and a GND wire 22, and function blocks 23 to 27 of a constitution realizing a logic circuit function inside are formed. Respective terminals of the function blocks 23 to 27 are automatically connected based on circuit connection data by a CAD tool, and LSIs of a cell base design are formed. Capacitor cells 40 to 43 are arranged in the wiring region. In a partial enlarged part where the capacitor cells 40 to 43 are arranged, between function blocks 1 and 2, a capacitor 3 is arranged connected with a power source wiring 4 and a GND wire 5. Thus, a bypassing capacitor can be arranged in LSIs without increasing the chip size, and the noise-proof performance of the circuit device can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell-based design semiconductor integrated circuit device designed by a standard cell design method or a cell-based design method, and more particularly to a cell-based design semiconductor integrated circuit device having a capacitance element for noise reduction. .

[0002]

2. Description of the Related Art As semiconductor integrated circuit devices have become smaller and faster, the influence of noise generated during operation has become a serious problem in recent years. That is, in order for the logic circuit in the semiconductor integrated circuit device to switch at high speed, it is necessary to charge and discharge the load capacitance connected to the output of the logic circuit at high speed. As a result, a very large pulsed current flows through the power supply wiring and the GND wiring of the semiconductor integrated circuit (hereinafter abbreviated as LSI) during switching of the logic circuit, and the resistance of the power supply wiring and the GND wiring of the LSI and the lead frame of the package. Moreover, the power source or the GND potential fluctuates significantly due to the inductance component. Such potential fluctuations not only cause a decrease in switching speed, but may also cause malfunction of the circuit.

In order to solve the above problems,
Several methods of inserting a bypass capacitor between the power supply wiring and the GND wiring have been proposed. For example, Japanese Patent Application Laid-Open No. 2-295161 (hereinafter referred to as reference example a) discloses a technique for realizing a bypass capacitor by incorporating a capacitive element in a semiconductor layer in which an epitaxial growth technique of an LSI is epitaxially grown. ing. Further, Japanese Patent Laid-Open No. 61-61437 (hereinafter referred to as Reference Example b) discloses a technique for realizing a bypass capacitor by using a transistor for a logic circuit in an unused area of a master slice type LSI. 60-1
Japanese Patent No. 61655 (hereinafter referred to as reference example c) discloses a technique of forming a bypass capacitor under a power supply wiring or a GND wiring that connects each of the power supply pad and the GND pad to the internal logic circuit.

In the master slice type LSI disclosed in the reference example b, referring to FIG. 4 which shows a circuit diagram of a cell when a bypass capacitor is realized, this master slice type LSI realizes a logic gate. The channel length L of the MOS transistor is thin because the underlying MOS transistor is used in common. Further, since the gate potential of the P-channel transistor is connected to the power supply, it is impossible to effectively realize the capacitance between the gate and the substrate. Therefore, a cell having such a structure cannot realize a very large capacity, and an upper wiring is required to connect the gate to the power source, which reduces the cell usage rate.

[0005]

However, in these prior arts, in the LSI in which the cells which are constructed by the cell-based design method and which are exclusively designed by the optimized transistor size are arranged in high integration, Since the capacity value that can be realized by the cell is small, an additional occupied area is required to insert the bypass capacitor, which has a drawback of increasing the chip size.

[0006]

A cell-based design semiconductor integrated circuit device of the present invention supplies a first power supply and a second power supply to perform a logic function operation, and substantially eliminates power supply noise generated during the logic function operation. A plurality of function block cells having the predetermined logic function including a basic cell capacitor element connected between the first and second power supplies so as to eliminate the above-mentioned problem. Then, wiring regions formed on the semiconductor substrate are arranged so as to sandwich or surround the block cells, and the function block cells and the block cells are connected to each other and arranged in the wiring region as needed. Cell-based design semiconductor integrated circuit device configured by a cell-based design method for realizing a desired circuit function by forming a plurality of wiring patterns Oite a structure having the function block inter-cell or are arranged between the block cell the first and second connected capacitor cells consisting of the capacitive element is.

Further, in the capacitive element of the cell-based designed semiconductor integrated circuit device of the present invention, a P channel M having a gate connected to the second power supply and a source connected to the first power supply.
It may be composed of an OS transistor and an N-channel MOS transistor whose gate is connected to the first power supply and whose source is connected to the second power supply.

Further, the capacitor cell of the cell-based designed semiconductor integrated circuit of the present invention may be arranged so as to overlap a plurality of the wiring patterns arranged in the wiring region.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A cell-based designed semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing the structure of a cell-based designed semiconductor integrated circuit device according to an embodiment of the present invention.

Referring to FIG. 1, the cell-based design semiconductor integrated circuit device of this embodiment includes a power supply wiring 21, a GND wiring 22, and function blocks (23 to 37) internally configured to realize a logic circuit function. The function blocks (23 to 37) are arranged and the respective terminals of the function blocks (23 to 37) are automatically connected by a CAD tool based on the circuit connection information to realize the function as the cell-based design LSI. . It should be noted that, for simplification of description, connection terminals for connecting terminals of the function blocks (23 to 37) are not shown.

When a mask pattern is created using a CAD automatic placement and routing tool such as cell-based design, an area for wiring is required between each function block, and all function blocks (23 to 3) are required.
7) cannot be placed in close contact.

Furthermore, the cell-based designed semiconductor integrated circuit device of one embodiment of the present invention has capacitor cells (40 to 43) arranged in this wiring region.

This capacitor cell (40-4 shown in FIG.
Referring also to FIG. 2 which is an enlarged view of a part where 3) is arranged, the cell-based design semiconductor integrated circuit device of this embodiment has function blocks 1 and 2, a capacitor cell 3, a power supply wiring 4, It is composed of the GND wiring 5.

The capacitor cell 3 has a gate 6 of a P-channel MOS transistor and a diffusion layer 8,
The gate 6 is connected to the GND potential by the contact 10, and the diffusion layer 8 is connected to the power supply potential by the contact 10. Also, this capacitor cell 3 is an N channel M
It has a gate 7 and a diffusion layer 9 of an OS transistor, the gate 7 is connected to a power supply potential by a contact 10, and the diffusion layer 9 is connected to a GND potential by a contact 10.

Referring to FIG. 3 showing the internal circuit of the capacitor cell 3, a MOS is provided between the power supply wiring and the GND wiring.
Capacitor cell 3 using the gate capacitance of the transistor
Has been realized. Further, only the gate and the diffusion layer are used inside the capacitor cell 3, and the first layer aluminum wiring and the second layer aluminum wiring which are usually designed by the CAD automatic wiring tool are not used at all. Even if the cell 3 is arranged in the wiring area, no adverse effect occurs on the automatic wiring tool.

By forming such a dedicated cell, the channel length L and the channel width W of the MOS transistor can be increased as much as possible, and a capacitor cell having the same cell size and a large capacity can be formed, and the wiring region can be formed. By using, the bypass capacitor can be inserted without increasing the chip size.

[0018]

As described above, according to the present invention, by arranging the capacitor cells in the wiring region by using the cell-based design method, the chip size of the bypass capacitor between the power supply wiring and the GND wiring is increased. Without LS
This can be realized within I, and the effect of improving the noise resistance of the LSI can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing the configuration of a cell-based designed semiconductor integrated circuit device according to an embodiment of the present invention.

2 is an enlarged view of a part of the cell-based design semiconductor integrated circuit device of the embodiment of the present invention shown in FIG.

FIG. 3 is a circuit diagram showing an internal circuit of a capacitor cell.

FIG. 4 is a diagram showing a circuit configuration of a bypass capacitor of a conventional master rice type LSI.

[Explanation of symbols]

 1,2,23-37 Function block 4,21 Power supply wiring 5,22 GND wiring 6,7 MOS transistor gate 8,9 Diffusion layer 10 Contact 40-43 Capacitor cell

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 8832-4M H01L 27/04 A

Claims (3)

[Claims] 1. A first power supply and a second power supply are connected to perform a logic function operation and connect between the first and second power supplies so as to substantially eliminate power supply noise generated during the logic function operation. A plurality of function block cells having the predetermined logic function including the basic cell capacitance element are arranged on a semiconductor substrate to form a block cell, and the semiconductor substrate is sandwiched or surrounded by the block cell. A desired circuit function is realized by arranging the wiring regions formed above and connecting between the function block cells and between the block cells as necessary to form a plurality of wiring patterns to be arranged in the wiring region. In the cell-based design semiconductor integrated circuit device configured by the cell-based design method, A cell-based designed semiconductor integrated circuit device having a capacitor cell which is arranged between cells and is composed of the first and second capacitive elements connected to each other. 2. The P-channel MOS transistor, the gate of which is connected to the second power supply and the source of which is connected to the first power supply, and the gate of which is connected to the first power supply and whose source is the first power supply. N channel MO connected to 2 power supplies
The cell-based designed semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is composed of an S-transistor. 3. The cell-based designed semiconductor integrated circuit according to claim 1, wherein the capacitor cell is arranged so as to overlap a plurality of the wiring patterns arranged in the wiring region.