JP2001168209A - Cmos integrated circuit and its automatic design method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed CMOS transistor integrated circuit of low power consumption and an automatic design method. SOLUTION: This CMOS integrated circuit is provided with four kinds of boards which are isolated electrically, using two systems of power sources where VDD' and VSS' are added as statistic board bias power sources to VDD and VSS of usual power sources, and the absolute values of the threshold voltages of all pull down/pull up transistors including drive inverters whether they are static circuits or dynamic circuits are set rather high. As a result, this achieves low power consumption even at operation excluding the time of standby, and contrives speed up even a little, setting the residual all transistors to the threshold voltages whose absolute values are rather low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor CMOS transistor integrated circuit, and more particularly to a circuit design and layout design of a basic cell in a chip design, that is, a physical design technique.

[0002]

2. Description of the Related Art At present, system LSIs of 0.18 μm bulk CMOS transistors are about to be mass-produced ahead of schedule. System LSIs, which are responsible for the achievements of IP in the limelight, use a state-of-the-art process technology aiming for ever-increasing high integration, and appear as a system-on-a-chip, incorporating a large number of functional modules including embedded memories. Is showing. In order to realize such a system LSI, it has become important to lower the power consumption and achieve a clock operation with the highest possible frequency. Therefore, in the example 0.18μm process technology, reduce the power supply voltage to 1.8V, a gate oxide film thickness and 4 nm, setting the threshold voltage V _T to 0.45 V (D.
Sylvester, K. Keutzer, "Getting to the Bottom of D
eep Submicron, "Proc. IEEE / ACM Int. Conf. on Compu
ter-Aided Design, pp. 203 211, Nov. 1998). On the extension, the 0.10μm process, lowering the supply voltage to 1.2V, a gate oxide film thickness and 2.5 nm, but must be set to the threshold voltage V _T to 0.3V (ibid), in general the threshold voltage V _T can not be as it is scaling (B. Davari, RH
Dennard, "The proponent himself revised the scaling rule, CMOS can evolve over the next 10 years," Nikkei Microdevices,
(September 1994, pp. 142153). If the voltage is further reduced below 0.3 V, it becomes difficult to control the leakage current.

[0003]

A CMOS having a characteristic of originally consuming less power than other semiconductor devices.
In order to further reduce the power consumption of the transistor technology, the following several technologies have been proposed. The first is MTCMOS by NTT (S. Mutoh,
et. al., "1-V Power Supply High-Speed Digital Circ
uit Technology with Multithreshold-Voltage CMOS, "
IEEE J. Solid-State Circuits, Vol. 30, No. 8, pp. 847
-854, Aug. 1995). By using the ion implantation technology, a threshold voltage having a low absolute value (V _TN , V _TP ) and a threshold voltage having a high absolute value (V _{TN ′} , V _{TP ′} ) are provided, and a pull-down / pull-up having the latter threshold value is provided during standby. Use to achieve low power consumption. In operation, it provided a high threshold voltage V _{TP 'of} the entire chip through the PMOS transistor of the virtual V _DD' absolute value (<V _DD) to the power supply of V _DD, also higher than the power supply V _SS Although a virtual V _{SS ′} (> V _SS ) via an NMOS transistor with a threshold voltage V _{TN ′} is used, it is difficult to determine W of those transistors in the whole chip. Actually, since a logic circuit having a threshold voltage with a low absolute value is operated at the voltage level of [V _{DD '} , V _{SS '} ] determined by W, the drop of V _{DD '} and the floating of V _{SS '} are caused by the logic circuit. Greatly affects the operating speed of the

The second is VTCMOS by Toshiba (T.
Sakurai and T. Kuroda, "Low-Power Circuit Design
Using CMOS VLSI's, "Proc. Of SASIMI'96, pp.3-10,
Nov. 1996). In this circuit method, a circuit that dynamically switches the substrate bias is used, the substrate bias is increased for all the transistors at the time of standby, a threshold voltage having a high absolute value is maintained, and low power consumption is maintained. In contrast, a high-speed operation is performed by setting a threshold voltage having a low absolute value with a normal substrate bias of [V _DD , V _SS ].
However, the finer the structure, the more difficult it is to balance maintaining high speed operation and reducing leakage current.

Third, the absolute value is increased by applying a substrate bias.
Is a circuit method that realizes a low threshold voltage and a low threshold voltage.
(S. Thompson, et. Al., "Dual Threshold Voltages a
nd Substrate Bias: Keys to High Performance, Low P
ower, 0.1μm Logic Designs, "1997 Symposium on VLSI
 Technology Digest of Technical Papers, pp. 69 70,
 1997). Its high threshold voltage applies to dynamic circuits
However, low threshold voltages are used for static circuits. S
The drive inverter, which is a static circuit, has its threshold voltage
, It is difficult to prevent leakage current. Fourth is Toshiba's other
Low power supply voltage V by group_DDAnd high power supply voltage V
_{DD '}(> V _DD) Is a dual power supply system (K. Usami and
M. Horowitz, "Clustered Voltage Scaling Technique
for Low-Power Design, "Proc. of Int. Symp. on Low
Power Design, pp. 38, 1995). The two types of PMO
Separating the S transistor substrate, V_SSDo not change. Only
However, the power consumption of the high-speed operation circuit is
It becomes. On the other hand, the low-speed operation circuit uses low power and consumes low power.
Power, but a voltage conversion circuit is required between
Increase the area.

[0006] In the history of the development of MOS transistor type large scale integrated circuits up to now, a remarkable improvement in the degree of integration has been achieved twice in 18 months based on the full scaling (constant electric field scaling) rule. This scaling reduces the power consumption to 1 / (S × S) by reducing all dimensions to 1 / S, increasing the impurity concentration to S times, and reducing the voltage to 1 / S. The power is kept constant.
Considering the full scaling of the design rule up to 0.07 μm on this extension, the following threshold voltages and the gate oxide film thickness of SiO 2 are particularly problematic. If the threshold voltage value is 0.3 V or less, it becomes difficult to cut off the drain current. In the vicinity immediately below the threshold voltage value, the drain current changes exponentially. The swing of the weak inversion voltage at which the single-digit drain current changes is N
At room temperature, about 80 mV / digit for MOS transistors, but about 100 mV / digit at 85 ° C., and 0.1 V
Each time it goes down, the standby current increases by one digit. Although this swing can be greatly reduced by applying a substrate bias, MTCMOS which controls the threshold voltage by ion implantation is used.
Difficult with transistors. Recently, Toshiba has established a new metal gate CMOS transistor manufacturing method, which is said to be used for the next generation 0.13 μm CMOS mass production line (Kyoichi Suguro, "MOS transistor manufacturing method is
Transformers: Renewal: Maintaining the Trend of High Speed ", Nikkei Microdevices, pp. 4651, May 1999. After source / drain diffusion using polysilicon for self-alignment, the polysilicon and gate oxide SiO2 are removed using damascene technology, then a new material gate oxide Ta2O5 is grown, and an aluminum gate is deposited. . Since Ta2O5 has a higher dielectric constant than SiO2, the reduction by scaling is smaller and the withstand voltage is increased, and the problem of the gate oxide film will be basically solved.

Further, in the conventional design of a high-speed data path module, a dynamic CMOS transistor circuit has been used, and an interactive manual design method for asking the designer everywhere has been frequently used. In order to improve the design efficiency of the system LSI, in order to improve the design efficiency of the system LSI, first of all, while maximizing the advantage of the dynamic CMOS transistor circuit of high speed and low power consumption, first apply to the circuit and layout design of the control circuit module, and It is important to establish those automatic design schemes. Next is the design automation of the data path module. In the conventional standard cell system, a drive inverter is included in a basic cell, and several basic cells having the same logic circuit but different drive capabilities are prepared in a library. If the logic circuit portion and the drive inverter portion of the basic cell are separated, only one type of different logic circuit is required in the library, and the drive inverters required at that time may be dispersedly inserted. In general, only the drive inverter has a large W transistor, and it is difficult to automatically arrange transistors in a basic cell including the transistor. Conversely, if the driving inverters are separated, the rest is regarded as having substantially the same size, and the automatic arrangement of the transistors can be easily automated.

In a pull-down transistor and a pull-up transistor in a conventional CMOS inverter, the diffusion of each source and drain is often laid out almost symmetrically, and each has approximately half the junction capacitance value with respect to the substrate. Further, there is a channel stopper having an impurity concentration approximately one digit higher than that of the substrate, and generally a higher junction capacitance is added in contact with the diffusion on three sides. However, since the voltage values of both source terminals connected to the ground V _SS or the power supply V _DD are constant, the junction capacitance of the source terminals including the three sides does not become a load. Conversely, the drain terminals of both become output nodes, and the junction capacitance load there is one of the factors that determine the operation speed. Therefore, there is a demand for a physical structure of a transistor that reduces the junction area of the drain and eliminates the channel stopper junction. If this source-drain asymmetry is further advanced, the short channel structure (Y. Tar
ui, Y. Hayashi, and T. Sekigawa, "Diffusion Self-A
ligned Enhance-Depletion MOS-IC (DSA-ED-MOS-IC), "
^{Proc. Of the 2 nd Conference on} Solid State Device
s, Tokyo, 1970, Supplement to the Journal of the J
apan Society of Applied Physics, Vol.40, pp.193-1
98).

It is an object of the present invention to provide a high-speed and low-power C
An object of the present invention is to provide a MOS transistor integrated circuit and an automatic design method thereof.

[0010]

SUMMARY OF THE INVENTION A CMOS transistor integrated circuit according to the present invention is a CMOS transistor integrated circuit that uses a pull-up / pull-up of a threshold voltage having a high absolute value by applying a substrate bias. Normal power supply [V _DD ,
To _{V SS], [V D D} ' as a static substrate bias power supply, V _SS
4 ] electrically isolated using two power supplies
All types of pull-down / including inverters are provided regardless of static circuit or dynamic circuit.
The absolute value of the threshold voltage of the pull-up transistor is set higher. As a result, low power consumption is achieved even during operations other than the stand-by operation, and the remaining transistors have lower absolute values of the threshold voltage, thereby increasing the speed even slightly.

Specifically, in a circuit and layout design for a CMOS transistor basic cell, the following four types of substrate separation circuit systems using a two-system power supply are used. That is, in addition to a pair of [V _DD , V _SS ] which is a normal power supply, a pair of [V _{DD ′} (> V _DD ), V
_{SS '} (< _VSS )], and these four types of [V _{DD '} , V _{SS '} ] are added to the substrate of the CMOS transistor in the basic cell.
By _applying a substrate bias of [V _DD , V _SS ], two types of electrically separated p-wells and n-wells as follows,
Create a total of four types. (1) The first-type p-well includes an NMOS transistor which is a pull-down transistor having a source terminal connected to the ground, and has a higher absolute value of a negative substrate bias V _{SS ′} (<
V _SS ), and has a higher positive threshold voltage. (2) The first-type n-well includes a PMOS transistor whose source terminal is a pull-up connected to a power supply, and a higher substrate bias voltage V _{DD ′} (> V _DD ) is applied to the n-well to increase the absolute value of the negative voltage. It has a threshold voltage. (3) The second type p-well is an NM constituting a logic circuit other than the pull-down.
It has an OS transistor and has a lower positive threshold voltage due to the substrate bias of V _SS . (4) The second type n-well is a PMOS constituting a logic circuit other than pull-up
It has a transistor and has a negative threshold voltage whose absolute value is lower due to the substrate bias of _VDD . These four types of wells are formed electrically separated on the substrate. For example, shallow trench isolation (ST
These are separated by I).

The physical structure of the pull-down / pull-up transistor in the above-described CMOS transistor integrated circuit has shallow source / drain diffusion. Assuming, as an example, an inverter composed of a pull-down and a pull-up having a higher absolute value of the threshold voltage, the drain terminals of both transistors serve as output terminals as they are. The shallow source / drain diffusion minimizes the area of each drain junction capacitance, and even if there is a channel / stopper diffusion, the drain diffusion has a structure not in contact with it, thereby increasing the speed. Further, the structure is such that a narrow channel effect does not occur. More specifically, in this physical structure, first, in the pull-down, the basic unit NMOS transistor having a high threshold voltage on the first type p well and having the source terminal connected to the ground, has a pitch of the second metal wiring in the horizontal direction. In order to make the drain junction capacitance as small as possible, a constant width w, which is an integral multiple, is used as a basic unit.
A drain terminal using a second metal is formed through a metal, a salicide (or polycide) gate terminal having the shortest channel length is formed on the outer periphery thereof, and a source formed by diffusion on the outer periphery of the gate terminal is formed. Terminal
It is formed so as to cover with the first metal connected to the ground V _SS , and is formed so as to have a constant height h in the vertical direction which is an integral multiple of the minimum wiring pitch of the third metal. Next, in the pull-up, the basic unit PMOS transistor having a high absolute value of the threshold voltage on the first type n-well has a source terminal formed by diffusion around the gate terminal with the first metal connected to the power supply _VDD. So as to cover the width w in the horizontal direction and the height h in the vertical direction.
(The same size as the basic unit NMOS transistor).

In the above-described CMOS transistor integrated circuit, D [Doubl] in which short channel diffusion and shallow source diffusion are performed by performing double diffusion on the source side.
e-Diffused] (or DSA [Diffusion Self-Aligned])-
MOST structure (Y. Tarui, Y. Hayashi, and T. Sekigaw
a, "Diffusion Self-Aligned Enhance-Depletion MOS-I
C (DSA-ED-MOS- IC), "Proc. Of the 2 nd Conference on
Solid State Devices, Tokyo, 1970, Supplement to the
Journal of the Japan Society of AppliedPhysics, V
ol.40, pp.193-198), and only shallow drain diffusion is performed on the drain side. This physical structure, except that it uses double spreading on the source side to form a short channel,
This is similar to the above-described CMOS integrated circuit.

In the above-described layout structure of the CMOS transistor integrated circuit, the absolute value between the columns electrically separated from the pull-down / pull-up by using the normal CMOS transistor configuration of [V _DD , V _SS ]. A lower threshold voltage is set to realize a logic circuit cell as fast as possible. Specifically, in the layout structure of the logic circuit cell, first, the second type p having a low positive threshold voltage
M series n composed of NMOS transistors on the well
In a parallel combinational logic circuit cell, a structured layout is performed so as to be an integer multiple i of the width w in the horizontal direction, and a certain constant is set in the vertical direction so as to be an integer multiple of the wiring pitch of the third metal including the isolation region. Height p. Next, a PMOS on a second type n well having a negative threshold voltage having a small absolute value
In an n-series / m-parallel combination logic circuit cell composed of transistors, a layout structured so as to be an integral multiple j of the width w in the horizontal direction is performed, and the mobility is approximately one half that of the NMOS transistor. About 2
The transistor width is twice as large, and the vertical direction is a constant height q including the isolation region, which is an integral multiple of the wiring pitch of the third metal. Further, the flip-flop composed of both transistors on both wells of the second kind also has a structured layout in which the width does not exceed an integral multiple k of the width w, and the vertical direction has a fixed height ( (p + q).

The layout structure of the CMOS integrated circuit according to the present invention is for a basic cell composed of a pull-down / pull-up drive circuit and a logic circuit which are electrically separated from the substrate. In all or a part of the module layout structure of the CMOS integrated circuit, four kinds of substrates to be electrically separated (a first type p well, a second type p well,
The first-type n-well and the second-type n-well) are vertically stacked with a separation width, have a constant height which is an integral multiple of the pitch of the third metal wiring, and are long in the horizontal direction according to the standard cell. On a rectangular cell row, basic cells are arranged horizontally without any gap. This is a normal power supply
Two power supplies consisting of [V _DD , V _SS ] and a substrate bias power supply [V _{DD '} , V _{SS '} ] can be automatically connected on the cell row.

In the layout structure for realizing the pull-down / pull-up circuit in the above-described logic circuit cell area, the pull-up is equivalent to r pull-downs in the vertical direction with a width w in a partial continuous column area of the logic circuit. In order to create s equivalents, first use the initial width w for the power line folding and separation area, then arrange the required number of vertically stacked r pull-downs and s pull-ups in the horizontal direction. These substrates are referred to as a first type p well and a first type n well,
A separation region is provided with the last width w, and the power supply line is bent again to return to the original position.

Next, the arrangement of the driving inverter in the CMOS integrated circuit will be described. The driving inverter is configured by a pull-up / pull-down having a threshold voltage having a large absolute value. According to the layout method of the present invention, instead of preparing several basic cells having the same logic for each driving capability, one type of basic cells having the same logic is stored in a library, and an inverter driven by an RC wiring load is used as needed at that time. Is distributedly inserted. In the above-described layout method, the driving inverter can be created anywhere on the quasi-standard cell row on the module. As a result, an inverter having a necessary driving capacity combining a pull-up of a basic unit and several pull-downs can be inserted into an optimum position with respect to a signal delay of a large load having a long RC wiring between modules and a large number of fan-outs. .

Therefore, in accordance with the automatic floor plan, a long RC which does not satisfy the delay condition by being connected to another module.
The wiring corrects the placement by inserting driving inverters at the output points and some intermediate points included in the soft module. In addition, when a connection must be made with a hard module, a driving inverter cannot be inserted therein, so that a driving inverter is inserted in a soft module so as to satisfy a delay condition. Specifically, an inverter driven by a large load such as a long RC wiring is inserted as follows in each of the following cases. When driving a load of a long RC wiring between modules, one basic unit NMOS transistor and two or three PMOS transistors are used.
(In this case, two units are described and expressed as [1: 2], but in the case of three units, the same as [1: 3]), a basic unit inverter is formed, and the basic unit inverter is driven to delay the RC wiring. The basic inverters are distributed and inserted evenly within the maximum length proportional to the wiring length so as to satisfy the delay condition. Also, when driving a large capacitive load, it is driven by a multi-stage inverter. In the circuit configuration, the current capacity is increased by about three times in order, that is, starting with [1: 2], [3:
6], [9:18],...

The automatic layout method for a CMOS transistor integrated circuit chip according to the present invention is based on a quasi-standard cell system in which a basic cell having the above-described four types of substrates is a constituent element. Here, when integrating a hard module or a soft module for each function on a semiconductor chip, the soft module is created by the quasi-standard cell method having the above-described four types of substrates. First, in the first step of the automatic floor plan, the approximate position of the hard module and the soft module and the approximate shape of the soft module are set so that the total wiring length between the modules is set as an evaluation function and is minimized. And the approximate position of the interconnection terminal. Below, one software
Thinking in the module, in a second step, a netlist representing connection information between basic cells consisting of m series and n parallel (or n series and m parallel) combinational logic circuits driven by pull-down / pull-up and flip-flops;
Then, various basic cell information such as a basic cell width which is an integral multiple of w used is input.

Next, in a third step, taking into account the difference in mobility between the NMOS transistor and the PMOS transistor, for example, considering the number of pull-downs x and the number of pull-ups y in the width w, the total {(x + y) × h + p + q}, the sum of the basic cell widths in each cell row is the average basic cell for a predetermined cell row length, ie, the soft module width W. Automatic placement is performed using a placement evaluation function that allows "variation" from 1/2 to 2 in width. Next, in a fourth step, automatic schematic wiring is performed in the software module. Next, in a fifth step, a drive inverter is inserted into a wiring that does not satisfy the delay condition in the soft module to correct the arrangement. Next, in the sixth step,
According to the automatic floor plan, long RC wiring connected to other modules and not meeting the delay
The drive inverters must be inserted evenly at the output points and intermediate points included in the module to correct the arrangement. If the drive inverter must be connected to the hardware module, the drive inverter cannot be inserted into it, so the delay condition must be satisfied. Unequally inserted drive inverter in the software module. Then, in a seventh step, automatic detailed wiring in the module is performed.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference symbols indicate the same or equivalent ones. A CMOS transistor integrated circuit according to the present invention is a CMOS transistor integrated circuit that uses a pull-down / pull-up of a threshold voltage having a high absolute value by applying a substrate bias. A pair of static power sources [V _DD , V _SS ] and a pair of static substrate bias power sources [V
_{DD '} , V _{SS '} ] and two types of power supply, and electrically separated four types of substrates are provided. All pull-down / pull-up circuits including drive inverters, regardless of whether they are static circuits or dynamic circuits, The absolute value of the threshold voltage of the transistor is set higher. As a result, low power consumption is achieved even during operations other than the stand-by operation, and the remaining transistors have lower absolute values of the threshold voltage, thereby increasing the speed even slightly.

FIG. 1 shows the basic concept of the above-described CMOS transistor basic cell circuit system using a pull-down / pull-up having a threshold voltage with a high absolute value, including a driving inverter. The CMOS transistor integrated circuit includes a plurality of NMOS transistors 10 (corresponding to a first-type p-well), PMOS transistors 12 (corresponding to a first-type n-well), and other circuits (logic circuits) 14 (logic circuits) disposed therebetween. (Corresponding to the second type p-well and n-well). [V _{DD ′} (> V _DD ), V _{SS ′} (<V _SS )] is used as a substrate bias power supply in addition to [V _DD , V _SS ] which is a normal power supply. The source terminals of all NMOS transistors 10 are connected to ground and pulled down. Furthermore, for all NMOS transistors 10, V _{SS ′} (<V _SS )
The absolute value of the threshold voltage V _T is increased by applying a higher negative substrate bias. The source terminals of all the PMOS transistors 12 are connected to a power supply and pulled up. Also, all the PMOS transistors 1
2, a higher positive substrate bias of V _{DD ′} (> V _DD ) is applied to provide a negative threshold voltage | V _T | with a higher absolute value. Furthermore, in other circuit 14 for NMOS transistor (not shown) constituting a logic circuit other than the pull-down, the substrate bias of V _SS to have a lower positive threshold voltage. In addition, a PMOS transistor (not shown) constituting a logic circuit other than the pull-up has a negative threshold voltage having a lower absolute value due to the substrate bias of _VDD .

Therefore, the CMOS transistor in the basic cell
Four types of [V_{DD '}, V_{SS '}] And [V_DD,
V_SS] With a substrate bias of electrically isolated p
Two types of wells and two types of n-wells were created, for a total of four types
You. FIG. 2 shows four types of bases in this CMOS integrated circuit.
Regarding plate separation, for example, V_{SS '}Substrate bias
Added first type p well 20, V_{DD '}Substrate bias
The first type n well 22 and V_SSSubstrate bias
2nd type p well 24 and V_DDSubstrate bias
The added second type n-well 26 is shown. This CMOS integrated circuit
On the road, shallow train
Electrical isolation using switch isolation (STI) technology
are doing. The first type p well 20 has a source terminal connected to ground.
Connect the connected NMOS transistor 10 as a pull-down
Negative substrate bias V with higher absolute value_{SS '}(<V_SS)
And has a higher positive threshold voltage. First
The seed n-well 22 is a pull-up device having a source terminal connected to a power supply.
A PMOS transistor 12 which is a
Plate bias voltage V_{DD '}(> V_DD) To increase the absolute value
With a negative threshold voltage. Type 2 p-well
24 is an NMOS which constitutes a logic circuit other than the pull-down
Having a transistor, V_SSLower substrate bias
It has a positive threshold voltage. Type 2 n-well 26
Is a PMOS transistor constituting a logic circuit other than the pull-up.
Transistor, and V_DDAbsolute value is low due to substrate bias
It has a negative threshold voltage.

Next, this integrated circuit will be described by a domino CMOS transistor circuit system. Here, it is assumed that only the dynamic logic circuit and the driving inverter are used, and no static CMOS transistor circuit other than the inverter is used. Therefore, a logic circuit is constituted only by the NMOS transistors on the p-well of the second kind, and the n-well of the second kind is not used (that is, a parameter q = 0 to be used later). The domino CMOS transistor circuit system is described in the following document. (JA Luisi, CW Padgett, DC
Street, "High Speed-Low Cost, Clock Controlled
CMOS Logic Implementation, "Sept. 21 1976, U.S. Pat.No. 3,982,138; RH Krambeck, CM Lee, H.-FS La
w, "High-Speed Compact Circuits with CMOS," IEEE
J. Solid-State Circuits, vol.SC-17, no.3, pp.614-6
19, June 1982; RK Brayton, CL Chen, C. McMulle
n, R. Otten, YJ Yamour, "Automated Implementatio
n ofSwitching Functions as Dynamic CMOS Circuits, "
Proc. IEEE Custom Integrated Circuits Conference,
pp.346-350, May 1984; M. Hofmann, AR Newton, "A
Domino CMOS Logic Synthesis System, "Proc. IEEE In
t. Symposium on Circuits and Systems, pp.411-414,
1985; G. De Micheli, "Performance-Oriented Synthes
is of Large-Scale Domino Circuits, "IEEE Trans. Co
mputer-AidedDesign, vol.CAD-6, no.6, pp.751-765, S
ep. 1987; R. Puri, A. Bjorksten, TE Rosser, "Logi
c Optimization by Output Phase Assignment in Dynam
ic Logic Synthesis, "Proc. IEEE / ACM Int. Conf. on
Computer-Aided Design, pp. 2-8, 1996; MR Prasad,
D. Kirkpatrick, RK Brayton, AL Sangiovanni-Vin
centelli, "Domino Logic Synthesis and Technology M
apping, "Proc. Int. Workshop on Logic Synthesis, vo
l.1, May 1997; and G. Yee, C. Sechen, "Dynamic Lo
gic Synthesis, "Proc. IEEE Custom Integrated Circu
its Conference, pp.345-348, May 1997)

A technique for automatically designing these standard cell libraries for a one-phase clock dynamic CMOS transistor circuit, starting with a basic cell for a control circuit module and then a basic cell for a data path module. Is shown. As a specific example, a domino CMOS
First, the outline of optimizing the circuit and layout will be described focusing on the transistor circuit system.

(A) Domino CMOS transistor circuit
To the logic circuit cell portion of the NMOS transistor configuration.
And the remaining clocked pull-up / pull-down and pull-up
Static CM consisting only of pull-up / pull-down
It is separated into the drive circuit cell portion of the OS inverter. (B) The NMOS substrate in the logic circuit cell portion is_SSConnect to
And the threshold voltage V_TTo V _DDSet to about 1/10 lower
The switching of the NMOS transistor
Increase speed. On the other hand, regarding the drive circuit cell portion,
First-type n-well substrate of pull-up PMOS transistor
V to 22_{DD '}(> V_DD) Bias and pull-down
V is applied to the first type p well substrate 20 of the NMOS transistor._SS
'(<V_SS) Bias with 0.25μm technology
Is the threshold voltage V of both_TThe absolute value of V _DDAbout 1/4 of
Set to V_DDAnd V_SSPrevent leakage current between and consume
Reduce power. (C) a low threshold voltage NMOS logic circuit cell portion,
Dormitory separated into the drive circuit cell part with high threshold voltage
Each cell of CMOS transistors is separated by a substrate
Quasi-standard cell automatic ray placed in another column
Do out.

In one example of the domino CMOS circuit cell shown in FIG. 3, the integrated circuit has a high absolute value threshold voltage NMOS.
It is composed of a driving circuit cell of a transistor and a PMOS transistor and an NMOS logic circuit cell with a low threshold voltage. In this way, the low threshold voltage NMOS logic circuit cell portion and the high absolute value threshold voltage drive circuit cell portion are separated into separate columns. Here, the NMOS logic circuit cell has a 12-input 3-series / 4-parallel configuration.

Conventionally, there has been proposed a circuit system for stabilizing a threshold voltage by dynamically switching a substrate bias (VTC).
MOS). On the other hand, in the above-mentioned CMOS integrated circuit,
The threshold voltage is controlled by applying a different substrate bias statically. The following equation shows the dependence of the threshold voltage V _{T on} the substrate bias voltage V _SB , and FIG. 4 shows how the threshold voltage V _T changes.

(Equation 1) If the substrate impurity concentration forming the PN junction with the source / drain is 3 × 10 ¹⁷ / cm ³ , the built-in potential is as high as 1.03V. Under a reverse substrate bias of 1.8 V, the junction capacitance value is reduced to about 60% as compared with the case of 0 V, and the speed is increased accordingly.

Next, the physical structure of the pull-down / pull-up transistor in the circuit layout of the CMOS integrated circuit will be described. In the case of an inverter composed of a pull-down transistor and a pull-up transistor having a higher absolute value of the threshold voltage, the drain terminal of both transistors is used as an output terminal. Here, the area of each drain junction capacitance is minimized by using shallow drain diffusion, and even if there is a channel stopper diffusion, the drain diffusion has a structure not in contact with it, thereby increasing the speed. Specifically, in the pull-down, the basic unit NMOS transistor having a high threshold voltage on the first type p well and having the source terminal connected to the ground has a constant width which is an integral multiple of the pitch of the second metal wiring in the horizontal direction. w is the basic unit,
The vertical direction is set to a constant height h which is an integral multiple of the minimum wiring pitch of the third metal wiring (polysilicon). In order to make the drain junction capacitance as small as possible in the basic unit NMOS transistors,
A drain terminal using the second metal wiring is formed via the metal wiring, and a salicide (or polycide) gate terminal having the shortest channel length is formed on the outer periphery thereof.
Furthermore the source terminal formed by a shallow diffusion on the outer periphery of the gate terminal, to create so as to cover the first metal interconnection connected to ground V _SS. Next, in the pull-up, the basic unit PMOS transistor having a high absolute value threshold voltage on the first type n-well has a first metal wiring in which a source terminal formed by diffusion around the gate terminal is connected to the power supply _VDD. To form a shape having the width w in the horizontal direction and the height h in the vertical direction (the same size as the basic unit NMOS transistor).

Preferably, in the above-described physical structure of the pull-down / pull-up transistor, a D [Double-Diffused] -MOST structure (double-diffusion on the source side to perform short channel diffusion and shallow source diffusion) Or DSA [Diffusion Self-Aligned])-Create a MOST structure (Y. Tarui, Y. Hayashi, and T. Sekigawa, "Di
ffusion Self-Aligned Enhance-Depletion MOS-IC (DSA-
ED-MOS-IC), " Proc. Ofthe 2 nd Conference on Solid S
tate Devices, Tokyo, 1970, Supplement to the Journ
al of the Japan Society of Applied Physics, Vol.4
0, pp.193-198). On the drain side, only shallow drain diffusion is performed. This makes it easy to create short channels,
On the other hand, the drain breakdown voltage can be increased.

As a specific example, a 0.18 μm process is taken and typical numerical values are shown. First, power supply conditions are shown below. V _DD = 1.8 V, V _SS = 0 V V _{DD '} = 3.6 V, V _{SS '} = -1.8 V The numerical values of the main parameters in the process are also shown. (a) Threshold voltage without substrate bias (normal temperature): V _T0 (N) = 0.18 V, V _T0 (P) = − 0.18 V (b) Carrier mobility on silicon surface (normal temperature): μ When (N) = 250 cm ² / vs and μ (P) = 100 cm ² / vs or less, the parameters of both MOS transistors were set to be the same. (c) Impurity concentration of channel region including depletion layer in twin-tub configuration: N _A = 3 × 10 ¹⁷ / cm ³ , N _D = 3 × 10 ¹⁷ / cm ³ (d) Oxide film thickness: T _OX = 4 nm (e) Gate oxide film capacitance: C _OX = 8.78 × 10 ⁻⁷ F / cm ² (f) Diffusion depth: X _j = 0.05 μm (g) _Effective channel length: L _eff = L _mask 2 × 0.8 × X _j = 0.10 μm (h) Substrate bias coefficient:

(Equation 2) (i) Fermi potential: | 2φ _F | = 0.876 V

FIG. 5 shows a layout structure of a pull-up PMOS transistor as an example to improve the performance. (Not shown is the same NMOS transistors.) In this case, a high pull-up PMOS transistor in the driver circuit cell having a threshold voltage V _T of the absolute value λ Design
I drew a figure based on the rules. The width of the central PMOS transistor is the smaller of 4 × 6λ. FIG. 6 is a horizontal cross-sectional view passing through the center of the PMOS transistor in the layout diagram of FIG. As shown in the center of FIG. 6, the drain terminal is output via two layers of metal wiring and two contacts.

In this PMOS transistor, the pitch in the horizontal direction (width in the horizontal direction) in the layout of the NMOS (PMOS) transistor having a high absolute value of the threshold voltage
Is a constant width w which is an integral multiple of the pitch of the second metal wiring.
Is determined as a basic unit. Here, it is assumed to be 16λ. The vertical direction is set to a constant height h which is an integral multiple of the minimum wiring pitch of the third metal wiring (polysilicon wiring) (here, 36λ). P connected to power supply V _{DD '}
A select part is provided, an n + diffusion part is formed therein, and further connected by a first metal wiring via a plurality of contacts in one row. On the other hand, an N select section is provided below it. A drain diffusion connected to an output or the like via the via hole and the second metal wiring is formed at the center. In order to make the drain junction capacitance as small as possible, the drain terminal is formed using a second metal through a first metal from a shallow diffusion with a minimum dimension. A gate terminal is formed on the outer periphery as a salicide (or polycide) having the shortest channel length, and is connected to a clock or the like. Further, a source diffusion portion is provided therearound by p + diffusion, and connected by a first metal wiring via a plurality of contacts.

The layouts shown in FIGS. 5 and 6 have the following features. (1) The silicide gate surrounds the periphery of the drain region and is laid out so that its PN capacitance is minimized. Compared to a symmetric layout, the source / drain having the same width does not first come into contact with the channel stopper, and the junction area with the well is the smallest. If the impurity concentration of the channel stopper is 3 × 10 ¹⁸ / cm ^3, which is about ten times the well concentration, the built-in potential rises to 1.09 V. As a result, when compared with the junction capacitance value in the case where the source and the drain are symmetrical, the value is greatly reduced to about 50%. (2) The source diffusion portion of the PMOS transistor connected to the power supply V _DD is connected to the PMOS transistor through many first contacts.
The connection is made by the first metal wiring so as to surround the transistor, and the voltage drop due to the diffusion resistance can be ignored. As a result, the operation of the PMOS transistor is stabilized. In addition, a leakage current generally occurs easily at two points in the source diffusion portion where the channel stopper is formed, but now both ends are the source portions and have the same potential, and no leakage current occurs. (3) References (D. Sylvester, K. Keutzer, "Getting t
o the Bottom of DeepSubmicron, "Proc. IEEE / ACM In
t. Conf.on Computer-Aided Design, pp. 203211, Nov.
1998)), when driving a 230 μm wiring length and an RC load of fanout 2 with a static 2-input NAND of a 0.25 μm process, Wn = Wp is optimal and each transistor size W / L is 20 μm. It is said that it should be about degree. In this structure, the transistor dimension W / L is 12, and if two transistors are used, the value approaches the optimum value.

In the layout structure of the logic circuit cell, [V _DD ,
A threshold voltage having a lower absolute value is set using a normal CMOS transistor configuration based on V _SS ], thereby realizing a logic circuit cell as fast as possible. Specifically, in an m-series / n-parallel combinational logic circuit cell having a low positive threshold voltage and constituted by NMOS transistors on a second-type p-well, the width is set to an integral multiple i of the width w in the horizontal direction. And a constant height p in the vertical direction that is an integral multiple of the wiring pitch of the third metal including the isolation region. In addition, a second threshold voltage having a small absolute threshold voltage is used.
In an n-series / m-parallel combination logic circuit cell composed of PMOS transistors on a seed n-well, a structured layout is performed so that the width becomes an integral multiple j of the width w in the horizontal direction. Considering that the mobility is about one half of that of the NMOS transistor, the transistor width is made about twice as large as the NMOS transistor, and the vertical direction is an integer multiple of the wiring pitch of the third metal including the isolation region. Height q. Furthermore, n of the second kind
The flip-flop composed of both the well and the p-well transistors also has a structured layout such that it does not exceed an integral multiple k of the width w in the horizontal direction, and exceeds a certain height (p + q) in the vertical direction. Layout so that there is no.

In the case of a domino CMOS transistor circuit, the NMOS logic circuit cell has several stages of NMs connected in series.
A circuit configuration for connecting OS transistors is adopted. In order to continuously improve the degree of integration and achieve low power consumption, the power supply voltage must be continuously reduced in accordance with the scaling rule. On the other hand, even if the substrate bias is 0V,
If the source voltage has a positive value, a body bias effect occurs,
This voltage drop limits the number of series stages. Further, as the number of stages in series increases, the equivalent resistance increases accordingly, and the circuit speed decreases unless the width of each transistor is increased. Increasing the width increases power consumption and area, and trades off in all aspects. Therefore, the power consumption is emphasized as the first priority, and the speed is increased as the second priority, and the number of series stages is set to three as shown in FIG. FIG. 7 shows a layout of the NMOS logic circuit cell portion. It is a circuit portion of three stages in series and one parallel. Here, based on a lateral pitch of 16λ (see FIG. 5) in the layout of the NMOS (PMOS) transistor having a high absolute value of the threshold voltage, the area is first minimized within a range of 32λ which is twice as large. The NMOS transistor width became 21λ. The Deep Submicron MOSFET current equation is not the classic (V _GS -V _T ) square law, but because of carrier velocity saturation effects (C. Hu, "Device
and Technology Impact on Low Power Electronics, "
Low Power Design Methodologies, ed. Jan Rabaey, Kl
uwer, pp. 21-35, 1996).

[Formula 3] _{I DSAT = W · v sat ·} C OX · (V GS -V T) (2) where, v _sat is the saturation speed of the carrier. This equation does not depend on the channel length. However, D (or DSA) -M
The case of OST has not been confirmed yet.

Next, each substrate is separated into a domino C cell as a lump into an NMOS logic circuit cell portion having a low threshold voltage V _T and a driving circuit cell portion having a high absolute value V _T.
Described below is how to automatically layout and synthesize MOS cells. In a normal standard cell, the cells are arranged in a row with the same height, so that a power supply or the like is automatically connected. If four or more layers of metal wiring are used, the chip will be "sea of cells" and can be wired almost on cells, eliminating the need for dedicated channel wiring areas.

Next, the layout structure of the semiconductor CMOS module using the quasi-standard cell system will be described. This layout structure is for a basic cell composed of a pull-down / pull-up drive circuit and a logic circuit that electrically separate the substrate. In all or a part of this layout, four types of substrates to be electrically separated, a first-type p-well, a second-type p-well, a second-type n-well, and a first-type n-well, are vertically separated by a separation width. The basic cells are arranged in a horizontal direction on a horizontally long rectangular cell row according to a standard cell at a constant height which is an integral multiple of the pitch of the third metal wiring, and are arranged without gaps. As a result, two power supplies composed of the normal power supplies [V _DD , V _SS ] and the substrate bias power supplies [V _{DD '} , V _{SS '} ] are automatically connected on the cell row.

Further, in this layout method, a pull-down / pull-up circuit having a threshold voltage having a higher absolute value is realized in the logic circuit cell region as described below. That is,
In order to create r pull-downs and s pull-ups in the vertical direction with a width w in the partial continuous column area of the logic circuit, first use the initial width w for the power supply line bending and separation areas, Then, in the horizontal direction, the required number of vertically stacked r pull-downs and s pull-ups are arranged at the same time. At the same time, the substrates are formed into a first type p well and a first type n well, and the separation region is formed with a final width w. Is provided and the power supply line is bent again to return to the original state.

Also, in this layout method, when inserting an inverter driven by an RC wiring load, instead of preparing several basic cells of the same logic for each driving capability, one type of basic cells having the same logic is stored in the library. Are distributed and inserted as needed at that time. The driving inverter is configured by pull-up / pull-down with a large absolute value threshold voltage, but using the layout method described above, it can be created anywhere on the quasi-standard cell row on the module . Therefore, specifically, a long RC
An inverter driven by a large load, such as wiring, is inserted as follows in each of the following cases to guarantee the operation.
(1) To drive a long RC wiring load between modules, one basic unit NMOS transistor and the same PMOS
A basic unit inverter is composed of two or three transistors (in this case, two transistors will be described and expressed as [1: 2], but in the case of three transistors, the same as [1: 3]), and driving of the basic unit inverter Accordingly, the delay time of the RC wiring is within the maximum length proportional to the wiring length, and the basic inverters are evenly distributed and inserted to satisfy the delay condition. (2) When driving a large capacitive load, drive with a multi-stage inverter. Here, a circuit configuration for sequentially increasing the current capability by about three times, that is, [1: 2] is started, and [3: 6], [9:
18],... And a multi-stage configuration in which the number of basic inverters is increased until the delay condition is satisfied.

Referring to FIG. 8, as a quasi-standard cell, a high threshold NMOS transistor, a low threshold NMOS transistor, and a high threshold PMOS transistor are separated into three rows (at appropriate separation intervals). An example of the arrangement is shown. As shown in FIG. 7, the logic circuit cell portion of the lower V _T (LN) has a width 32λ 1 parallel configuration of three-stage series. The NMOS transistor width is slightly smaller than that of the NMOS transistor width of high V _T. In this example, two high V _T NMOS transistors (HN) are used, one for the pull-down and one for the drive inverter. The high PMOS transistor absolute value of the threshold V _T (HP), as say for example, three for one drive inverter for pull-up, it is possible to use a total of four.

In accordance with the quasi-standard cell method as shown in FIG. 8, automatic layout of semiconductor chips is performed as shown in the following procedure. Here, when integrating a hardware module or a software module for each function on a semiconductor chip, the soft module is created by a quasi-standard cell method including the above-described basic cell having the four types of substrates as constituent elements. I do. In this automatic layout method, (1) When a hard module or a soft module for each function is integrated on a semiconductor chip, the soft module is generally created by a quasi-standard cell method having four types of substrates. . (2) Determine the approximate position of the hard module and the soft module, the approximate shape of the soft module, and the approximate position of the interconnection terminal so that the total interconnection length between modules is set as an evaluation function and is minimized. Implement an automatic floor plan. (3) The following steps are considered in one software module. First, a netlist representing connection information between basic cells consisting of an m-series / n-parallel (or n-series / m-parallel) combinational logic circuit driven by pull-down / pull-up and a flip-flop, and 16
Various basic cell information such as a basic cell width which is an integral multiple of λ (generally w) is input. (4) In consideration of the difference in mobility between the NMOS transistor and the PMOS transistor, for example, considering the number of pull-downs x (for example, 0.5) and the number of pull-ups y (here, one) within the width w, the total is calculated. {(x + y) × h + p + q} (=
For a cell row having a height of (1.5 × h + p + q), the sum of the basic cell widths in each cell row is an average with respect to the length of a predetermined cell row, that is, the soft module width W. Automatic placement is performed using a placement evaluation function that allows "variation" from 1/2 to 2 of the basic cell width. (5) Perform automatic general wiring in the software module. (6) A drive inverter is inserted into the wiring that does not satisfy the delay condition in the soft module to correct the arrangement. (7) In accordance with the automatic floor plan, long RC wiring that does not satisfy the delay condition by being connected to other modules can be achieved by inserting driving inverters evenly at the output points and some intermediate points included in the soft module. When the arrangement must be corrected and a hard module must be connected, a drive inverter cannot be inserted into the hard module. Therefore, drive inverters are unequally inserted in the soft module to satisfy the delay condition. (8) Then, automatic detailed wiring in the module is performed.

[0043]

According to the present invention, low power consumption is achieved as the first priority, and high speed is achieved as the second priority.
A CMOS basic cell was realized as a quasi-standard cell. Also, automatic layout can be performed like a standard cell in a software module. All pull-downs / pull-ups whose source terminals are connected to V _SS and V _DD have a threshold voltage with a high absolute value, and all have the same size for structuring. A logic circuit cell having a threshold voltage with a low absolute value approaches a state close to the final logical state early in the preparatory stage, and quickly enters the final logical state in the evaluation stage. Further, automatic layout processing can be performed in the same manner as the standard cell by using quasi-standard cells which are electrically separated and vertically stacked on four types of substrates. In the current deep submicron era, wiring RC delay becomes larger than gate delay, and this is an important issue. In the present invention, the drive inverter can be inserted anywhere in the soft macro on the chip except for the hard module, and the possibility of containing the wiring RC delay within the delay constraint condition is significantly increased. By adopting the double diffusion D (or DSA) -MOST, a short channel can be easily formed, and the drain breakdown voltage can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram of an example of a pull-down / pull-up CMOS integrated circuit showing a basic concept of a CMOS transistor circuit of the present invention.

FIG. 2 is a cross-sectional view of each MOSFET including four types of substrates.

[Figure 3] domino CMOS circuit cell diagram separated and the logic circuit portion, the drive circuit the absolute value has a high V _T (clock input gate and an inverter) portion having a lower V _T

FIG. 4 is a graph showing a substrate bias V _SB at a threshold voltage V _T.

FIG. 5 is a layout diagram of a pull-up PMOS transistor.

FIG. 6 is a sectional view of a pull-up PMOS transistor.

FIG. 7 is a layout diagram for a logic circuit cell having a low _VT and a three-series one-parallel configuration.

FIG. 8 Layout diagram of quasi-standard cell

[Explanation of symbols]

10 pull-down NMOS transistor, 12
Pull-up PMOS transistor, 14 Other circuits, 20 First-type p-well, 22 First-type n
Wells, 24 second type p wells, 26 second type n wells.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) DD07 DD34 EE02 EE19 EE22 EE35 EE36

Claims (8)

[Claims] 1. In addition to a pair of power supply V _DD and ground V _SS , a pair of power supply V _{DD ′} (> V _DD ) and ground V _{SS ′} (<V _SS ) can be connected as a substrate bias power supply. The source terminal of the NMOS transistor is connected to the ground V _SS , the first type p well to which the substrate bias V _{SS '} is added, the source terminal of the PMOS transistor is connected to the power supply V _DD , and the substrate bias V _{DD '} is further connected. The added first type n well and the source terminal of the NMOS transistor are connected to the ground V _SS
And a second type p-well having a lower positive threshold voltage than the first type p-well due to the substrate bias of the ground V _{SS, and} the substrate of the power source having the source terminal of the PMOS transistor not connected to the power source _VDD. A second type n-well having a negative threshold voltage whose absolute value is lower than that of the first type p-well due to bias; and these four types of wells are electrically separated from each other on the substrate. A CMOS integrated circuit characterized by the above-mentioned. 2. The CMOS integrated circuit according to claim 1, wherein said NMOS transistor on said first-type p-well basically has a constant width w which is an integral multiple of a pitch of a second metal wiring in a horizontal direction. In units, the vertical direction has a constant height h which is an integral multiple of the minimum wiring pitch of the third metal wiring, and the drain terminal is located between the drain region formed by diffusion and the first.
A salicide (or polycide) gate terminal is formed on the outer periphery of the drain terminal, and a source terminal is connected to ground from a source region formed by diffusion on the outer periphery of the gate terminal. The PMOS transistor on the first type n well formed of the first metal wiring has the width w in the horizontal direction and the height h in the vertical direction, and the source terminal is a gate terminal. And a source region formed by diffusion on the outer periphery of the CMOS integrated circuit and covered with a first metal wiring connected to a power supply. 3. The CMOS integrated circuit according to claim 2, further comprising performing a double diffusion on a source side to form a D (or DSA) -MOST structure in which a short channel diffusion and a shallow source diffusion are performed. A CMOS integrated circuit, wherein only the shallow drain diffusion is performed on the drain side. 4. The CMOS integrated circuit according to claim 2, wherein an m-series-n-parallel combination logic circuit cell composed of NMOS transistors on a second-type p-well has an integer of the width w in the horizontal direction. A PMOS transistor on a second-type n-well having a layout structured so as to be a multiple i and having a constant height p in the vertical direction that is an integral multiple of the pitch of the third metal wiring including the isolation region. Has a layout structured so as to be an integral multiple j of the width w in the horizontal direction, and has the wiring pitch of the third metal including the isolation region in the vertical direction. A flip-flop having a constant height q that is an integral multiple and a transistor on the second type p-well and the second type n-well has an integer multiple k of the width w in the horizontal direction. Ray that does not cross A CMOS integrated circuit having a layout having an out and not exceeding a certain height (p + q) in a vertical direction. 5. The CMOS integrated circuit according to claim 2, wherein at least a part of the layout includes four types of substrates to be electrically separated, that is, a first type p well and an n well and a second type p well. Wells and n-wells are vertically stacked with a separation width, and at a constant height that is an integral multiple of the pitch of the third metal wiring, on a horizontally long rectangular cell row similar to a standard cell, A CMOS integrated circuit, wherein basic cells are arranged horizontally without any gap. 6. The CMOS integrated circuit according to claim 4, wherein in the partial continuous column region of the logic circuit cell, r pull-downs and s pull-ups are vertically equivalent in width W units. Minutes, using the initial width W for the power line folding and separation area, and then arranging the required number of vertically stacked r pull-down and s pull-up transistors in the horizontal direction while simultaneously arranging them. A CMOS integrated circuit, wherein a substrate is a first-type p-well and a first-type n-well, an isolation region is provided with a final width W, and a power supply line is bent again to return to an original state. 7. The CMOS according to claim 5 or 6.
In the integrated circuit, the driving inverter is a pull-up / pull-down transistor having a threshold voltage with a large absolute value, and is formed at an arbitrary position on a module. 8. In a layout in which a hard module and a soft module for each function are integrated on a semiconductor chip, the soft module is divided into four types of substrates,
That is, the source terminal of the NMOS transistor is connected to the ground V
_{The first} which is connected to _SS and adds the substrate bias V _{SS ′} (<V _SS )
A p-type seed, a first-type n-well in which the source terminal of the PMOS transistor is connected to the power supply V _DD and a substrate bias V _{DD ′} (> V _DD ) is added, and a source terminal of the NMOS transistor is connected to the ground V _SS. The second having a positive threshold voltage lower than the first type p well due to the substrate bias of the ground V _SS
The seed p-well and the source terminal of the PMOS transistor are not connected to the power supply _VDD, and the first terminal is supplied by the substrate bias of the power supply.
A second type n-well having a threshold voltage higher in absolute value than the type n-well is created by the quasi-standard cell method, and the total wiring length between the modules is minimized, so that the outline of the hard module and the soft module is obtained. The first step of the automatic floor plan for determining the position, the general shape of the soft module and the general position of the interconnection terminal, and thereafter, m series n parallel (or n) driven by pull-down / pull-up in one soft module A series of netlists representing connection information between basic cells composed of combinational logic circuits and flip-flops, and various basic cell information such as a basic cell width that is an integer fraction of the soft module width W used therein. A second step of inputting, where h is a basic pitch in the vertical direction, and p is an NMOS transistor on a second type p well. Assuming that the vertical height of the group, q, is the vertical height of the PMOS transistor group on the second type n-well, a total of {(x + y ) × h + p + q}, the sum of the basic cell widths in each cell row is calculated by calculating the average basic cell width of the predetermined cell row length, that is, the soft module width W. The third step of automatic placement using a placement evaluation function that allows "variation" from 1/2 to 2; the fourth step of automatic schematic routing in the soft module; and the delay condition in the soft module. A fifth step of correcting the arrangement by inserting a drive inverter for the wiring that does not satisfy the condition, and a long R that does not satisfy the delay condition by connecting to another module according to the automatic floor plan. C wiring is soft
The drive inverter is inserted at the output point and some intermediate points included in the module to correct the arrangement, and when the wiring must be connected to the hard module, the drive inverter cannot be inserted into the module, so that the delay condition is satisfied. A method for automatically laying out semiconductor chips based on a quasi-standard cell method, comprising: a sixth step of inserting a drive inverter in a software module as described above; and a seventh step of performing automatic detailed wiring in the module.