JP2001291775A - Method for designing layout of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for designing the layout of an integrated circuit capable of effectively reducing a power source noise, and reducing the increase of a semiconductor chip area. SOLUTION: A power source noise generated in a circuit block is calculated by referring to a load capacity connected to the output terminal of the circuit block and a rising and falling time, and outputted as power source noise information in a step S5. A by-pass capacity for setting a prescribed power source noise level or less is selected from a noise by-pass capacity table 13 by referring to the power source noise information and the noise by-pass capacity table 13 in a step S6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for an integrated circuit, and more particularly to an integrated circuit that reduces power supply noise generated in an integrated circuit and prevents other circuits in the same integrated circuit from malfunctioning due to the power supply noise. Layout design method.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor integrated circuits, the voltage of semiconductor integrated circuits has been reduced, and the speed of semiconductor integrated circuits has rapidly increased, as represented by LSIs for processing multimedia. ing. Due to such circumstances,
Switching noise generated in a digital circuit constituting a semiconductor integrated circuit has become an extremely serious problem. That is, the noise margin decreases as the voltage decreases, and the power product of the noise increases as the speed of the semiconductor integrated circuit increases, and the internal circuit of the semiconductor integrated circuit easily malfunctions due to the noise.

As an example in which a circuit malfunctions due to noise, noise generated in a digital circuit forming a semiconductor integrated circuit propagates as power supply noise on a power supply wiring or a GND wiring (ground wiring), and the other circuit of the semiconductor integrated circuit. A typical case is that the bias voltage or signal voltage of a digital circuit or an analog circuit is instantaneously changed, thereby changing the threshold value of the circuit.

In order to prevent such power supply noise, an integrated circuit described in Japanese Patent Application Publication No.
By forming a bypass capacitor in the S transistor, power supply noise is reduced.

Next, the integrated circuit described in the above publication will be described with reference to FIG.

An N well 91 is formed on a P-type substrate except for a hollow region 96 shown in FIG. That is, the inside of the hollow region 96 is a P-type substrate. In N well 91,
A P-channel transistor 93 and an N-channel transistor 94 are formed, and these two transistors constitute an inverter.

A P-channel transistor 93 is composed of a gate polysilicon 92 and a P-type diffusion layer 95 forming a source and a drain.
4 comprises a gate polysilicon 92 and an N-type diffusion layer 97 forming a source and a drain.

The N well 91 and the P-type substrate are connected to a power supply VDD and a ground VSS, respectively.
Since the mold substrate is in a reverse bias state, the N well 91 and the P
A junction capacitance is formed by the mold substrate, and this junction capacitance acts as a power supply noise absorbing capacitor.

In the above structure, the N channel transistor 93 and the N channel transistor 94 are formed.
Since the well region can be widened, the N well 91
And a P-type substrate, that is, the capacitance value of the power supply noise absorbing capacitor can be increased, and the power supply noise can be effectively absorbed.

The power supply noise absorbing capacitor formed by the N-well 91 can reduce the mutual interference between the function block A, the function block B, and the function block C.

[0011]

SUMMARY OF THE INVENTION The above-described conventional integrated circuit has a power supply noise absorbing capacitor, that is, a bypass capacitor, regardless of whether or not it is required for each circuit constituting the semiconductor integrated circuit. Since a bypass capacitor is formed for each MOS transistor, there is a problem that the area of a semiconductor chip increases and the degree of integration of a semiconductor integrated circuit decreases.

In the conventional integrated circuit, the same bypass capacitance is formed corresponding to each MOS transistor.
When power supply noise is reduced at a large-scale macroblock or an upper circuit level, there is a disadvantage that it is not possible to cope with the characteristics of the macroblock or the upper circuit level or the layout situation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems of the conventional integrated circuit, and to reduce the increase in the area of the semiconductor chip and effectively reduce the power supply noise. It is an object of the present invention to provide a layout design method of an integrated circuit which can perform the above.

[0014]

Therefore, an integrated circuit layout design method according to the present invention is a layout design method for an integrated circuit including a plurality of circuit blocks and a power supply wiring and a ground wiring connected to these circuit blocks. A first arrangement / wiring step of arranging the plurality of circuit blocks and arranging wiring between the plurality of circuit blocks and wiring of the power supply wiring and the ground wiring, and reducing a wiring capacitance between the plurality of circuit blocks. A load capacity extracting step of extracting a load capacity of the circuit block, a rise time and a fall time calculating step of calculating a rise time and a fall time of an input voltage of the circuit block, and a load capacity extracting step. The load capacity, and the rise time and fall time of the input voltage calculated in the rise time and fall time calculation steps. A power supply noise calculating step of calculating a power supply noise generated in the circuit block and transmitted through the power supply wiring or the ground wiring, a rise time and a fall time of the input voltage; And a power supply noise storing data of a basic power supply noise which is the power supply noise determined from conditions including a bypass capacitance connected between the power supply wiring and the ground wiring.
A power supply noise / bypass capacitance table generating step of generating a bypass capacitance table; and the power supply noise calculated in the power supply noise calculating step; and referring to the power supply noise / bypass capacitance table to reduce the power supply noise to a predetermined value or less. And a bypass capacitance selecting step of selecting the necessary bypass capacitance from the power supply noise / bypass capacitance table, and disposing the bypass capacitance selected in the bypass capacitance selecting step between the power supply wiring and the ground wiring. And a second arrangement / wiring step.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing an embodiment of a layout design method for an integrated circuit according to the present invention. The circuit connection information 11 includes cells which are basic circuits such as NAND, NOR, and flip-flop circuits; CPU, RA
It is constituted by a circuit block including a mega macro having a large circuit scale such as M and ROM.

First, in step S1, circuit connection information 11
Refer to and perform automatic placement and wiring. The automatic placement / routing process may be a schematic placement / routing process including a schematic layout of circuit blocks included in the circuit connection information 11 and a schematic wiring process between these circuit blocks. Alternatively, a detailed arrangement / detailed wiring processing step including detailed arrangement of circuit blocks and detailed wiring processing between these circuit blocks may be used.

Next, in step S2, the load capacitance added to the output terminal of the circuit block is extracted. This load capacitance is composed of the wiring capacitance connected to the output terminal of the circuit block and the input capacitance of the circuit block to which the output terminal is connected. As the wiring length of the wiring connected to the output terminal of the circuit block increases, the wiring capacitance increases substantially in proportion to the length. In recent LSIs, wiring having a long wiring length exceeding 10 mm has been increasing with the increase in circuit scale.
This is a factor that increases power supply noise.

Next, in step S3, step S2
A circuit simulation is performed by using the load capacitance extracted in the above and the simulation pattern 12 for the circuit simulation prepared in advance, and referring to the circuit simulation information obtained in the step S3, the rise of the input voltage of the circuit block in the step S4 And the fall time is calculated.

Next, in step S5, step S2
The power supply noise generated in the circuit block is calculated with reference to the load capacitance obtained in the step (a) and the rise and fall times of the input voltage obtained in the step S4, and output as power supply noise information.

Subsequently, in step S6, step S
5, the power supply noise information obtained in step 5 and a noise / bypass capacitance table 13 indicating the relationship between the power supply noise described later and the bypass capacitance connected between the power supply terminal and the ground terminal of the circuit block. A bypass capacitance for making the level or less is selected from the noise bypass capacitance table. At this time, if the power supply noise level is equal to or lower than the predetermined power supply noise level without adding the bypass capacitance, the bypass capacitance is not added.

Subsequently, in step S7, step S
6, the circuit connection information with the bypass capacitance is generated by adding the bypass capacitance selected in step 6 to the circuit connection information 11, and step S
At 8, it is determined whether the bypass capacitance is to be manually arranged or automatically arranged.

If automatic placement of bypass capacitance is selected in step S8, the bypass capacitance is automatically placed in step S9 with reference to the circuit connection information with bypass capacitance generated in step S7, and the bypass capacitance is manually placed in step S8. If the placement is selected, the bypass capacitance is manually placed in step S10.

Next, in step S11, it is determined whether or not the bypass capacitance arranged in step S9 or S10 satisfies an evaluation criterion such as a layout constraint, and if it satisfies the evaluation criterion, a step S12 is performed.
Then, wiring and rewiring between circuit blocks including bypass capacitors are performed, and layout data 14 for mask fabrication is generated based on the layout data of the circuit blocks and the wiring data between the circuit blocks.

At this time, if the connection between the circuit blocks can be performed without changing the wiring generated in step S1, the wiring generated in step S1 is left as it is, and the wiring requiring correction is re-routed. For the wiring between the bypass capacitor and the power supply terminal and the ground terminal, a new wiring is generated.

If it is determined in step S11 that the placement evaluation does not satisfy the evaluation criteria, the bypass capacitors are rearranged in step S13, and then automatic wiring is performed in step S12.

Next, referring to FIG. 2 to FIG.
The bypass capacity table 13 will be described.

FIG. 2 is a flowchart showing a method of generating the power supply noise bypass capacitance table 13. In step S21, a circuit block such as a cell or a mega macro is selected.

Next, in step S22, the load capacitance connected to the output terminal of the circuit block, the rise time and fall time of the input voltage applied to the input terminal of the circuit block,
Initial conditions including initial values such as the capacitance value of the bypass capacitance are set.

Here, the rise time and the fall time of the input voltage will be described with reference to FIG. 4. The rise time and the fall time are from the low level (high level) to the high level (low level) of the input signal. 10%
The transition time is between 90% and 90%.

Next, with respect to the circuit block selected in step S21, referring to the initial conditions set in step S22, the current driving capability of the circuit block, and the like, step S21 is executed.
At 23, a basic power supply noise simulation for calculating the basic power supply noise which is the power supply noise constituting the power supply noise / bypass capacitance table 13 is executed. The power supply noise increases as the input waveform becomes steeper, that is, the rise time and fall time of the input voltage are shorter, the load capacity is larger, and the current drive capability of the circuit block is larger. Therefore, when the wiring length of the wiring connected to the output terminal of the circuit block incorporating the high-drive output buffer is very long and the slew rate of the input signal is large, the power supply noise is particularly large.

Subsequently, in step S24, with regard to variables for performing the noise simulation, such as the load capacitance, the rise time and the fall time of the input voltage, and the capacitance value of the bias capacitance, whether the noise simulation has been performed for all variable designated ranges. It is determined whether or not the answer is YES in step S24.
If it is determined that there is a condition for which the noise simulation has not been completed for the variable range specified in step 5, the variable condition is set and the noise simulation in step S23 is executed.

As described above, steps S23 to S
Step 25 is repeated, and a noise simulation for calculating power supply noise is performed for all specified variable ranges.

As for the condition setting in step S25, it is generally used that the additional capacity is set to Co and Co = Co + α to increase the additional capacity by α in order from the initial value for each process. Have been. This is the same for other variables.

Next, in step S26, step S
Based on the power supply noise calculated in 23, a power supply noise bypass capacitance table 13 shown as an example in FIG. 3 is generated.

In FIG. 3, the load capacitance connected to the output terminal of the circuit block is 1 pF, 2 pF, and 3 pF, respectively, and the rise time and fall time of the input voltage applied to the input terminal of the circuit block are 0.5 nsec, respectively.
At 1 nsec and 2 nsec, the capacitance value of the bypass capacitance is not connected between the power supply terminal and the ground terminal of the circuit block, that is, the case where no bypass capacitance is arranged, and the capacitance value of the bypass capacitance connected between the power supply terminal and the ground terminal of the circuit block Are set to C1, C2 to C8, respectively.

Therefore, in step S6, the bypass capacitance required to prevent the malfunction of the circuit is calculated, and the capacitance closest to the calculated capacitance value is selected from the power supply noise bypass capacitance table 13 shown in FIG.

Here, C1 <C2 <C3 <C4 <C5 <
C6 <C7 <C8, and V1 ≧ V2> V3, V1 ′>
V2 ′> V3 ′, V1 ″ ≧ V2 ″> V3 ″.

For example, in step S5 of FIG. 1, it is assumed that 0.5 Vrms is obtained as a result of calculating power supply noise for a circuit block having a rise time and a fall time of an input voltage of 1 nsec and a load capacitance of 1 pF. In step S6, it is determined that the circuit malfunctions at 0.5 Vrms.
It is assumed that rms is determined to be necessary.

On the other hand, in FIG. 3, when the capacitance C1 is 10 pF and the basic power supply noise V2 'is 0.31 Vrms, and the capacitance C2 is 15 pF and the basic power supply noise V2 "is 0.2 Vrms, the power supply noise is reduced to 0.3 Vrms or less. Next, C2 (= 15 pF) is selected as the bypass capacitance from the power supply noise / bypass capacitance table 13 shown in FIG.

Further, as described in step S5, in the case of a circuit block having a large current driving capability, the power supply noise also increases, so that the bypass capacitance is also increased.

Next, with reference to FIG. 5, the bypass capacitance used in the integrated circuit layout designing method of the present invention will be described.

FIG. 5A is a plan view of the bypass capacitor, and FIG. 5B is a schematic sectional view of the bypass capacitor. In FIG. 5, reference numeral 51 denotes a polysilicon diffusion region doped with impurities; 54, a P-type substrate; 55A, 55B locos oxide films; 56A, 56B field oxide films;
Is an N well, 58 is an N type diffusion region, 53A is a contact for extracting an electrode from the N type diffusion region 58 to the semiconductor surface, 53B is a contact for extracting an electrode from the polysilicon diffusion region 51 to the semiconductor surface, and 52A is an N The lead electrode of the mold diffusion region 58 and 52B are the lead electrodes of the polysilicon diffusion region 51.

The bypass capacitor of this structure uses an insulating film between the N-type diffusion region 58 and the polysilicon diffusion region 51 as an insulating film between the capacitor electrodes, and is also used as a gate oxide film of a normal MOS transistor.

By connecting the extraction electrode 52A to the power supply terminal and connecting the extraction electrode 52B to the ground terminal, the N-well 57 and the P-type substrate 54 are reverse-biased. The junction capacitance is formed in parallel between the extraction electrode 52A and the extraction electrode 52B.

Therefore, the capacitance value of the bypass capacitance can be increased as compared with the case where the capacitance is formed by using the insulating film between the N-type diffusion region 58 and the polysilicon diffusion region 51 alone as the insulating film between the capacitor electrodes. .

The power supply noise absorbing capacitor described in Japanese Patent Application Laid-Open No. 6-151741 is constituted only by the junction capacitance between the P-type substrate and the N well. Large fluctuation in capacity.

On the other hand, the bypass capacitance used in the layout design method of the integrated circuit according to the present invention is characterized in that the fluctuation due to the power supply voltage is small and the fluctuation due to the manufacturing process is mainly the fluctuation due to the gate oxide film pressure.

The area occupied by the bypass capacitor shown in FIG. 5 is substantially proportional to the bypass capacitor. The bypass capacitances C1 to C8 in the power supply noise bypass capacitance table 13 shown in FIG.
It is stored in a storage device as a bypass capacitance cell having a fixed layout and a different area.

Therefore, assuming that the occupied areas of the bypass capacitors C1 to C8 are S1 to S8, respectively, S1 <S2 <.
... <S8. In the layout design method for an integrated circuit according to the present invention, by selecting a plurality of bypass capacitors having different areas and arranging them on the semiconductor chip, it is possible to prevent the area of the semiconductor chip from becoming unnecessarily large.

Further, as described above, since the bypass capacitance is constituted by bypass capacitance cells having different areas, an arbitrary capacitance can be created by combining the bypass capacitance cells in series, parallel or series-parallel. It is possible to

It is also possible to register macro bypass capacitors fixed in layout as cells by combining bypass capacitor cells in series, in parallel, or in series / parallel. By doing so, the range of selection of the bypass capacitance is increased, so that more optimal power supply noise countermeasures can be taken.

Next, a specific example of a circuit to which the layout design method for an integrated circuit according to the present invention is applied will be described with reference to FIG.

The circuit shown in FIG. 6 has an input terminal IN1 (601)
And the signals applied to the input terminal IN2 (602) are shaped by inverters 603 and 609, respectively, and the output signals of the inverters 603 and 609 are output from the NOR gate 6 respectively.
11, the output signal of the inverter 603 is input to the high drive buffer 605, and the output signal of the high drive buffer 605 and the output signal of the NOR gate 611 are both NAN.
An input signal is input to the D gate 613, and an output signal is extracted from an output terminal 615 to which the output terminal of the NAND gate 613 is connected.

Reference numerals 602 and 608 denote load capacitors connected to the input terminals 601 and 609, respectively.
Is a load capacitance connected to the output terminals of the inverters 603 and 609, respectively, and 606 is a load capacitance of the high drive buffer 605. In this circuit example, wiring from the output terminal of the high drive buffer 605 to the input terminal of the NAND gate 613 is used. And the load capacity is large.

Therefore, the power supply noise generated in the high drive buffer 605 is large and the circuit malfunctions. Therefore, the bypass capacitor 606 is connected to the power supply terminal of the high drive buffer 605 and the ground terminal.

The bypass capacitor 606 is used to control the current driving capability and load capacitance of the high drive buffer 605, the slew rate of the input signal applied to the input terminal, and the inverters 603 and 606.
09, a NOR gate 611, a NAND gate 613, and the like, which are arranged around the high drive buffer 605 and are connected to a power supply line and a ground line common to the power supply terminal and the ground terminal of the high drive buffer 605, taking into account the noise margin of a circuit block. In step S6 of FIG. 1, a bypass capacitance having a minimum capacitance value at which the circuit does not malfunction is selected from the power supply noise bypass capacitance table 13 shown in FIG.

Next, a semiconductor chip 71 designed by applying the layout design method for an integrated circuit according to the present invention will be described with reference to FIGS.

In FIG. 7, an input / output buffer 72, cells 73A to 73I, and mega macros A to E are arranged on a semiconductor chip 71.

Next, the processing of steps S1 to S6 in FIG. 1 is performed (the wiring is not shown), and as shown in FIG. 8, the current driving capabilities of the cells 73A to 73I and the mega macros A to E and the circuit block To prevent the circuit from malfunctioning due to the power supply noise calculated from the load capacitance of the power supply and the rise time and fall time of the signal wiring.
A to 81F are arranged adjacent to the circuit block.

[0061]

As described above, the layout design method for an integrated circuit according to the present invention is irrespective of whether a bypass capacitor is required for each circuit constituting a semiconductor integrated circuit as in the conventional example. Unlike the method in which a bypass capacitance is formed for each MOS transistor, a bypass capacitance of such a size that a circuit malfunction does not occur due to power supply noise is arranged adjacent to the circuit block. When the circuit does not malfunction due to power supply noise, no bypass capacitor is provided, so that an increase in the area of the semiconductor chip can be reduced.

In the case of the integrated circuit described in Japanese Patent Application Laid-Open No. 6-151741, a bypass capacitance is provided for each MOS transistor. 50%
Assuming that the bypass capacitance is formed in all the transistors, the area increases by 15% with respect to the original semiconductor chip area.

However, in the case of the present invention, the bypass capacitance to be arranged can be selected according to the degree of noise reduction. Therefore, only when the circuit malfunctions due to power supply noise, the bypass capacitance cell having the area corresponding to the capacitance value of the bypass capacitance is provided. , The increase in the area of the semiconductor chip due to the placement of the bypass capacitor is small.

Since the design is automatically performed with reference to the power supply noise / bypass capacitance table, it is possible to prevent the designer from making mistakes.

Further, in Japanese Patent Application Laid-Open No. 6-151741, since the bypass capacitance is formed uniformly, the power supply noise at the circuit level in the mega macro or the upper hierarchy when the chips are hierarchized is reduced. Although it is difficult to optimally arrange bypass capacitors in consideration of layout conditions, in the case of the present invention, it is possible to configure a bypass capacitor having a required capacitance value by combining basic bypass capacitors.

For this reason, it is possible to freely lay out the bypass capacitance, not only to eliminate the unplaced and unwired wiring in the automatic placement / wiring processing, but also to reduce the unnecessary area, thereby providing the bypass capacitance. It is possible to reduce the increase in the area of the semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a layout design method for an integrated circuit according to the present invention.

FIG. 2 is a flowchart illustrating a method for creating a power supply noise bypass capacitance table 13 according to the present invention.

FIG. 3 is a diagram showing an example of a power supply noise bypass capacitance table according to the present invention.

FIG. 4 is an explanatory diagram for explaining a rise time and a fall time.

FIG. 5 is a plan view and a schematic cross-sectional view of a bypass capacitor used in the layout design method for an integrated circuit according to the present invention.

FIG. 6 is a specific example of a circuit to which the layout design method for an integrated circuit of the present invention is applied.

FIG. 7 is a plan view of a semiconductor chip designed by applying the integrated circuit layout design method of the present invention.

FIG. 8 is a plan view of a semiconductor chip designed by applying the layout design method for an integrated circuit according to the present invention.

FIG. 9 is a plan view showing a bypass capacitor described in Japanese Patent Publication No. Hei 6-151741.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Circuit connection information 12 Simulation pattern 13 Power supply noise / bypass capacitance table 14 Layout data 51 Impurity-doped polysilicon diffusion region 52A Extraction electrode of N-type diffusion region 58 52B Extraction electrode of polysilicon diffusion region 51 53A N-type diffusion region 53B Contact for extracting an electrode from the polysilicon to the semiconductor surface 53B Contact for extracting an electrode from the polysilicon diffusion region 51 to the semiconductor surface 54 P-type substrate 55A, 55B Locos oxide film 56A, 56B Field oxide film 57 N well 58 N-type diffusion region 601 and 607 input terminals 603 and 609 inverters 602, 604, 608, 610, 612, 614, 6
16 Load capacitance 605 High drive buffer 606 Bypass capacitance 611 NOR gate 613 NAND gate 615 Output terminal 71 Semiconductor chip 72 Input / output buffer 73A-73I Cell 81A-81F Bypass capacitance A-E Mega macro

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) EE02 EE08 EE43 EE45 HH06 HH09

Claims (6)

[Claims] 1. A layout design method for an integrated circuit including a plurality of circuit blocks, and a power supply line and a ground line connected to the circuit blocks, wherein the plurality of circuit blocks are arranged, and A first arrangement / wiring step of wiring the power supply wiring and the ground wiring, and a load capacitance extracting step of extracting a load capacitance of the circuit block including a wiring capacitance between the plurality of circuit blocks; A rise time and a fall time calculation step for calculating a rise time and a fall time of the input voltage of the circuit block; the load capacity extracted in the load capacity extraction step; and a rise time and a fall time calculation step. With reference to the rise time and fall time of the input voltage, the power supply wiring or the connection generated in the circuit block is referred to. A power supply noise calculating step of calculating power supply noise transmitted through a wiring; a rise time and a fall time of the input voltage; the load capacitance; and a bypass capacitance connected between the power supply wiring and the ground wiring. A power supply noise that generates a power supply noise bypass capacitance table storing data of the basic power supply noise that is the power supply noise determined from the conditions.
A bypass capacitance table generation step, and the power supply noise calculated in the power supply noise calculation step, and referring to the power supply noise / bypass capacitance table, the bypass capacitance required to reduce the power supply noise to a predetermined value or less. A bypass capacitance selecting step of selecting from the power supply noise bypass capacitance table; a second arrangement / wiring step of arranging the bypass capacitance selected in the bypass capacitance selecting step between the power supply wiring and the ground wiring; A layout design method for an integrated circuit, comprising: 2. The layout design method for an integrated circuit according to claim 1, wherein said bypass capacitor is arranged adjacent to said circuit block. 3. The power supply noise bypass capacitance table generating step includes: a circuit block selecting step of selecting one of the plurality of circuit blocks; a rise time and a fall time of the input voltage; A condition setting step of setting conditions for a bypass capacitance connected between the power supply wiring and the ground wiring; and a condition selected in the circuit block selecting step according to the conditions set in the condition setting step. A basic power supply noise calculation step of calculating a basic power supply noise transmitted from the circuit block to the power supply wiring or the ground wiring; a basic power supply noise calculated in the basic power supply noise calculation step; a rise time and a rise time of the input voltage; 2. A step of generating a fall time, the load capacity, and the bypass capacity as a table. Integrated circuit layout design method. 4. The power supply noise calculated in the power supply noise calculation step in the bypass capacitance selection step,
If the integrated circuit does not malfunction, the selection of the bypass capacitance from the power supply noise / bypass capacitance table is not performed, and the bypass capacitance is not arranged in the second arrangement / wiring step. A layout design method for an integrated circuit according to claim 1. 5. A bypass capacitance cell fixed in layout corresponding to the bypass capacitance constituting the power supply noise bypass capacitance table, and a layout fixed by combining the bypass capacitance cells in series, parallel or series-parallel. The registered macro bypass capacitance is registered as a cell, and the bypass capacitance is arranged using the bypass capacitance cell or the macro bypass capacitance in the second arrangement / wiring step. The layout design method of the integrated circuit described above. 6. A semiconductor substrate of a first conductivity type, a well region of a second conductivity type formed from a main surface of the semiconductor substrate to a region inside the substrate, and an insulation formed on a main surface of the well region. A semiconductor film and an electrode formed on the insulating film, the semiconductor substrate and the electrode are connected to the power supply wiring or the ground wiring, and the semiconductor substrate and the well are connected to the well and the reverse bias. 2. The layout design method for an integrated circuit according to claim 1, wherein the layout is connected to the ground wiring or the power supply wiring.