JPH0566737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a large-scale integrated circuit device that simplifies the system configuration of a data processing device or the like.

[Technical background of the invention and its problems]

To configure a system such as a personal computer, multiple LSIs (Large-Scale Integrated Circuits) are usually used in combination. These are CPU (Central Processing Unit), ROM (Read Only Memory), RAM
(random access memory), key input control section, serial input/output section, parallel input/output section, counter timing control section, display drive section, etc., and interconnections between each chip are done by printed circuit boards. . However, this method requires complicated interconnections on the printed circuit board and is time-consuming to manufacture.
This causes an increase in costs. Also, because the electrostatic capacity of the printed wiring is large, even if the speed of each chip increases, it does not lead to an increase in the power of the entire system. In addition, due to the high failure rate, there is a strong demand from users that it is possible to integrate multiple LSIs used in a system into a single chip.

As a way to meet the above demand for single-chip integration,
(b) Re-design the entire system and create a new 1-chip LSI
(b) encapsulating multiple chips in one package to create a so-called hybrid IC (integrated circuit). In the case of the method of redesigning the entire system as described in item (a) above, the existing design methods include a completely manual design method, an automatic design method using a building block method using a computer, an automatic design method using a gate array, etc. etc. All of these have advantages/disadvantages, but the biggest disadvantage of redesigning is that even though each chip has already been developed and has been sufficiently evaluated in terms of function and characteristics, In order to design, the design and evaluation steps must be repeated. Therefore, there are various problems such as the risk of design errors and the need for development time.
I have to say that this is an incompetent method.

The hybrid IC method described in item (b) above is that when viewed from the outside, it only appears as a single component;
This is simply a method of mounting a plurality of chips on the printed circuit board and wiring them to a smaller size. Of course, there are some merits to just making it smaller, but as an actual implementation technology, it is questionable how many chips can be hybridized, and even if it were possible, the cost would increase considerably.

Therefore, the present applicant has proposed a large-scale integrated circuit that makes it possible to integrate a new system into a single chip, which is different from either redesign or hybridization (for example, Japanese Patent Application Laid-Open No. 58-91003). FIG. 8 shows this proposal. In the figure, 1 is a semiconductor chip, and A and B are chip-equivalent regions formed simultaneously in the same process in the chip 1. These regions were previously formed in the chip A, respectively. This has been evaluated as Chip B. 2 and 3 are the bonding pads when the chip equivalent areas A and B were previously chips A and B (this is temporarily called the inner bonding pad), and 4 is the bonding pad of chip 1 (this is temporarily called the outer bonding pad). ). In this way, the chip-corresponding regions A and B, which have already been evaluated and confirmed, are arranged and formed within the chip 1 with an appropriate space 5 between them. This space 5 is a wiring area for mutual wiring 6 between the chip equivalent areas A and B, and near the periphery of the chip there are bonding pads for connection to the outside as lead terminals from the LSI after the chip is integrated into a single chip. A wiring area used for wiring (temporarily referred to as external wiring) 7 is also provided. That is, chip equivalent areas A and B
Interconnection lines 6 between the bonding pads of areas A and B are made of a wiring layer (polysilicon, aluminum, etc.) by the process of areas A and B, using the wiring area 5 described above between the bonding pads that each area has. Furthermore, the required number of bonding pads 4 corresponding to the external wiring 7 are laid out around the chip, and the external wiring 7 is also placed between the bonding pads 2 and 3 in the corresponding areas A and B and the outer bonding pad 4. Made from silicon, aluminum, etc.

FIG. 9 shows a partial cross section of FIG.
12 is an N type substrate, 13 and 14 are P ⁺ type sources,
15 is an insulating film, 16 is a polysilicon gate electrode, 17 is an aluminum wiring, 18 is a wiring difference region 17 ₁ and 17 ₂ in the wiring region 5, and 8th
Aluminum wiring layer 19 corresponding to wiring 6 in the figure
is a polysilicon wiring layer.

This integrated circuit device shown in FIGS. 8 and 9 is
Although it is manufactured on a single semiconductor substrate 12, designing a glass mask pattern for manufacturing such a device is very easy and there is almost no chance of making a mistake. Furthermore, since the chip-equivalent regions A and B require almost no modification to the conventional chip configuration, the functions and characteristics that have been evaluated and confirmed can be used as is.
chipped. Furthermore, conventional manufacturing processes can be applied as they are to obtain this device.

By the way, as mentioned above, the area A corresponding to multiple chips,
If B is formed within one chip, there will be a latch-up phenomenon between chip-equivalent regions A and B, or between chip-equivalent regions A or B and the chip periphery, that is, excessive surges or excessive noise at the input/output terminals. When voltage or current is applied, or due to noise from internal circuits, a phenomenon occurs in which abnormal current continues to flow between the power supplies. Figures 10 and 11 are for explaining the latch-up phenomenon between chip-equivalent regions A and B. Figure 10 is a circuit diagram of the adjacent area between chips A and B, and Figure 11 is the same. FIG. In the figure, 21 and 22 are low impedance buffer P-channel and N-channel transistors configured in chip A, 23 is its output pad, 24 is an N-channel transistor configured in chip B, and 25, 26 28 and 29 are the source and drain layers of the transistor 21, 30 is the P well layer, and 31 and 32 are the substrate bias N ⁺ type diffusion layers for biasing the N type substrate 27 to the potential of the power supply _VDD . Source and drain layers, 33 are P ⁺
layer 29 or 28, N ⁺ layer 25 or N type substrate 2
7. Parasitic lateral PNP transistor with P-well layer 30 as emitter, base, and collector, 3
4 is an N type substrate 27, a P well layer 30, and an N ⁺ layer 31
It is a parasitic lateral NPN transistor with collector, base, and emitter.

In Figures 10 and 11, external noise (above the V _DD level) is applied to the P ⁺ layer 29 through the pad 23.
When current i ₁ flows, it becomes the base current of the lateral PNP transistor 33, and a collector current i ₂ flows to the P well layer 30 in accordance with its h _FE (current amplification factor). Then, the potential of the P well layer 30 becomes the power supply.
The voltage rises to the V _DD side, current i ₃ flows and the lateral NPN transistor 34 is turned on, and current i ₄ flows from the N ⁺ layer (ground potential). As a result, the potential of the substrate 27 is pulled to the ground side, the potential near the N ⁺ layer 25 is lowered, and the P ⁺
Lateral transistor 3 with layer 28 as emitter
3 base current is applied. At this time, the lateral NPN
Transistor 34 is also on and enters latch-up development.

That is, in chips that have already been designed and evaluated, countermeasures have been taken in the area around the pads in order to guarantee the latch-up voltage and current for each terminal. However, in each chip, countermeasures are generally taken only in the area from the pad to the inside of the chip, but not in the area outside the chip. This is because in the region extending from the pad to the outside of the chip, only one conductivity type transistor exists at most, so no latch-up occurs in this region.

As described above, conventionally, pattern-like measures are taken to absorb surges in the area extending from the pad to the inside of the chip. However, Figures 8 to 11
In a large-scale integrated circuit device as shown in the figure, transistor elements exist even in the outward direction of each chip (chip-equivalent region) that has already been designed and evaluated. In FIG. 8, if pad 23 is an output terminal in chip A, an instantaneous current flows when pad 23 is switched, which becomes a surge current, and the surge propagates to chip B through the semiconductor substrate of semiconductor chip 1, causing the latch to open. cause a phenomenon.
In particular, when P and N channel transistors are located facing each other between chips A and B, latch-up is likely to occur.

Furthermore, the higher the chip can withstand high-speed operation, the lower the impedance of the output buffer is set to improve its switching characteristics, thus inducing more switching current. Further, when pad 23 is connected to an external terminal, a latch-up is induced between chips A and B due to a surge from the outside.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to prevent the latch-up phenomenon in large-scale integrated circuits having a plurality of chip-equivalent regions formed independently within the same semiconductor.

[Summary of the invention]

In order to prevent the latch-up phenomenon, the trigger current propagating between the region where the P-channel transistor is formed and the region where the N-channel transistor is formed may be reduced therebetween. Therefore, in the present invention, a high concentration impurity layer with low resistance is provided in the opposing regions of a plurality of chip-equivalent regions or between the chip-phase region and the outer edge of the chip, that is, in the region outside the chip-equivalent region, and this is appropriately applied. This biases the power supply level to a certain level.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a plan view of the same embodiment, Fig. 2 is a planar configuration diagram of the vicinity of adjacent areas corresponding to the chip,
The figures are the same cross-sectional views, but since these are examples in which they correspond to those in Figures 8, 10, and 11, corresponding parts are given the same reference numerals and explanations will be omitted. , explain the features. The feature of this embodiment is that a highly doped N-type diffusion layer 41 is provided between the chip equivalent regions A and B, and this is biased to the power supply V _DD (>0).

In the case of the devices shown in FIGS. 1 to 3, a surge is applied to the P + layer 29 due to a surge from the bonding pad 42 or a surge during switching of the low impedance buffer, and from there, the power supply V _DD is applied to the P ⁺ layer 29 through the substrate 27. A current _i1 flows into the side. That is, this current flows into the N ⁺ layer 25, which is all in close proximity to the P ⁺ layer 29 and biased to _VDD . This becomes the base current of the parasitic lateral PNP transistor 33 and produces a collector current i ₂ .

Here, if the N ⁺ layer 41 does not exist, the power supply V _DD of the N ⁺ layer 25 on the current flow side is more positive.
V _DD and a potential gradient is generated between it and the N ⁺ layer 26 .
This means that a potential gradient occurs in the base region of the transistor based on the N ⁺ layer 25 or N ⁺ layer 27, which improves the current gain of the lateral transistor 33 and makes it easier to induce the latch-up phenomenon described above. Become. On the other hand, by inserting the low-resistance N ⁺ layer 41, the potential gradient in the base of the lateral transistor 33 can be reduced, the current gain of the transistor 33 can be reduced, and the latch-up phenomenon can be prevented.

In the above embodiment, the case of an N-type substrate was explained, but
It is clear that in the case of a P type substrate, a P ⁺ layer may be used in place of the N ⁺ layer 41 and biased to the power supply V _SS level.

FIG. 4 shows another embodiment of the invention. That is, the high concentration diffusion layer 41 may be provided widely within the wiring region 5. Moreover, if the high concentration diffusion layer 41 is provided all over the wiring region 5 as shown in FIG. 5, the effect will be even greater.

FIG. 6 shows a different embodiment of the present invention, in which the region where the high concentration diffusion layer 41 is arranged is a chip equivalent region A,
Each box in B. In this way, a latch-up between the chip-corresponding regions A and B and the external terminal 4 can be prevented.

FIG. 7 shows still another embodiment of the present invention, in which a bias power source 51 for the heavily doped diffusion layer 41 is provided separately from power sources 52 for the chip equivalent regions A and B. In this way, since the bias power supply for the chip equivalent regions A and B, which are unstable to the bias of the high concentration layer 41, is not used, the high concentration diffusion layer 41 can be made more stable.
1 can be supplied with a bias.

Note that the present invention is not limited to those in which the structure of the chip equivalent region is a silicon gate structure, but can also be applied to structures such as an aluminum gate structure.

〔Effect of the invention〕

As explained above, according to the present invention, the latch-up phenomenon can be easily prevented by arranging a highly concentrated layer biased to the power supply level in the region facing the chip-equivalent region or in the region surrounding the chip-equivalent region. , it is possible to reduce the chip equivalent area to one chip without modification. By burying the above-mentioned high concentration layer under the wiring region, latch-up can be prevented without increasing the chip size.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of the essential parts, FIG. 3 is a sectional view of the essential parts, and FIGS. A schematic plan view of a different embodiment; FIG. 8 is a schematic plan view of a conventional improved large-scale integrated circuit; FIG. 9 is a partial cross-sectional view of the same circuit; and FIG. 10 is a plan view of essential parts of the circuit. FIG. 11 is a sectional view of the main parts. 1... Semiconductor chip, 5... Wiring area, 41...
...High concentration layer, A, B...chip equivalent area.

Claims (1)

[Scope of Claims] 1. A plurality of chip-equivalent regions, each of which is formed independently in the same semiconductor substrate and corresponds to a single chip whose functions and characteristics have already been evaluated, and an electrode for leading out of the region of the chip-equivalent region. a wiring layer for selectively connecting the chips; a wiring region between the chip-equivalent regions and serving as an installation region for the wiring layer;
at least a high-concentration layer inserted between the opposing chip-equivalent regions and biased to one power supply level, and the chip-equivalent regions are of complementary type.
1. A large-scale integrated circuit device having a MOS configuration, wherein a region in which the high concentration layer is arranged is a region outside the chip-equivalent region. 2. The large-scale integrated circuit device according to claim 1, wherein a power source for biasing the high concentration layer is provided separately from a power source for the chip-equivalent region.