JPS61144846A - Large scale integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent latchup by a method wherein high-concentration impurity- diffused layers are provided in opposing locations of chip regions or in locations out-side a chip region and the layers are biased on a proper power source level. CONSTITUTION:An N<+> layer 41 is provided between regions A, B equivalent to chips and a bias voltage VDD>0 is applied thereto. Application of a surge to a P<+> layer 29 from a pad 42 results in the flow through a substrate 27 of a base current i1 of a parasitic PNP element 33 through an N<+> layer 25 biased with the voltageeVDD, which results in a collector current i2 allowing latchup to easily take place. Insertion of an N<+> layer 41 moderates the potential gradient within the N-base of a parasitic lateral PNP element, reducing the current gain in the element 33 and thereby preventing latchup. In case of a P type substrate, the substrate is biased on a power source VSS level by using the P<+> layer 41.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a large-scale integrated circuit device that has a simplified system configuration such as a data processing device.

[Technical background of the invention and its problems]

K, which constitutes a system such as a personal computer, is usually used in combination with a plurality of r and sI (large scale integrated circuits). These are CPU (Central Processing Unit), ROM (
Read-only memory), RAM (random access memory), key manual control section, serial input/output section, parallel input/output section, counter timing control section, display drive section, etc., and there are many chips between each chip. Inter-wiring is done on a printed circuit board. However, with this method, the interconnections on the printed circuit board are complicated and the manufacturing process is labor-intensive, resulting in increased costs.

Also, even if the printed wiring has a large capacitance and the speed of each chip becomes faster, the overall system speed will not be as high as fK. In addition, due to the high failure rate, the user's request is to reduce the number of L
There is a strong demand for SI to be made into a single unit.

As a method to meet the above-mentioned demand for one chip, (support) redesign the entire system to create a new 1-chip L8I chip, or (←) encapsulate multiple chips in one 74-chip cage to create a so-called hybrid chip. It is conceivable to use an IC (integrated circuit). Above f.

In the case of the method of redesigning the entire system described in section 3.2, the current design methods include: ■ Complete manual design method, ■ Automatic design method using a building block method using a computer, ■ Automatic design using a dirt array, etc. There is. All of these ■～■ have advantages and disadvantages, but the biggest disadvantage of redesigning is that ``each chip has already been developed and has been sufficiently evaluated in terms of function and characteristics; In order to design the project again, the design and evaluation qPJI must be carried out again.

Therefore, there are various problems such as the risk of design errors and the time required for development, so it cannot help but be said that this method is ineffective.

The hybrid IC method described in item ←) above appears as a single component when viewed from the outside, and is merely a miniaturization of the method of mounting and wiring a plurality of chips on the printed circuit board. Of course, there are advantages to just making it smaller, but as an actual implementation technology, there are still doubts as to how many chips can be hybridized, and even if it were possible, the cost would increase considerably. Dew.

Therefore, the present applicant would like to propose a large-scale integrated circuit that enables a new system to be integrated into a single chip, which is different from either redesign or hybridization (for example, Japanese Patent Application No. 58-91003). Figure 8 shows this proposal, where 1 represents a semiconductor chip and a person.

B is a chip-equivalent region formed together in the same process in the chip f1, and these regions were previously formed in the chip fh.
, which has been evaluated as ChifB. 2 and 3 are the landing pads when the chip equivalent areas A and B used to be chips A and B (temporarily assume that the inner
．． The number 4 is the leading edge of the chip 1 (this is temporarily referred to as the outer winding point). In this way, the chip equivalent areas A and B whose evaluation has already been confirmed
are arranged and formed within the chip 1 with an appropriate space 5. This space 5 is a wiring area for mutual wiring 6 between the chip corresponding area M and B, and there is also space near the chip periphery for connection to the outside as a lead terminal from the KLSI after it is integrated into one chip. A wiring area used for wiring 11 (temporarily referred to as external wiring) 7 with the landing pad is also provided. That is, the mutual wiring 6 between the chip-equivalent regions A and 1 is
, which B each has? The wiring region 5 is used between the bonding nodes to form a wiring layer (of silicon, aluminum, etc.) by the process of regions A and B. Furthermore, a necessary number of connecting pads 4 are laid out around the chip, and the external wiring 7 is connected to the ending pads 2 and 3 of the corresponding areas A and B, and the actuator landing pads.

Between 4 and 4, it is made of silicon, aluminum, etc.

9 shows a partial cross section of FIG. 8, 11 is a transistor region of chip equivalent area A or B, 12 is an N-type substrate, 13.14 is a pm source and drain region, 15 is an insulating film, 16 is a 1 is a silicon ff-) electrode, 17 is an aluminum wiring, 18 is a wiring crossing area in the wiring area 5,
71.17° is an aluminum-ram wiring layer corresponding to the wiring 6 in FIG. 8, and 19 is a 4-Si wiring layer.

The present integrated circuit device shown in FIGS. 8 and 9 is fabricated on a single semiconductor substrate 12, but it is very easy to design a glass i-sk Δ turn to fabricate such a device. I almost never make a mistake. Furthermore, chip equivalent area A.

B requires almost no modification to the conventional chip configuration, so the functions and characteristics that have already been evaluated and confirmed can be integrated into a single chip. Furthermore, conventional manufacturing processes can be applied as they are to obtain this device.

By the way, as mentioned above, the area A corresponds to multiple chips.

When formed in a B'QI chip, there may be latch-up phenomenon between the chip-equivalent areas A and B, or between the chip-equivalent area or iB and the chip periphery, excessive surges, noise, etc. at the input/output terminals. If an excessive voltage or current is applied to the product, or noise from the internal circuit occurs, an abnormal current may continue to flow between the stains. Figures 10 and 11 are for explaining the latch-up phenomenon between chip equivalent areas A and B. Figure 10 is a circuit diagram of the adjacent area between chips A and B, and Figure 11 is a diagram of the circuit configuration near the adjacent chips. It is the same sectional view. 21 in the figure.
22 is a P-channel type and N-channel type transistor of a low impedance buffer configured in the chip body, 23 is its output capacitor, 24 is a nine N-channel type transistor configured in the chip B, and 25.26 is an N-type substrate. N for board bias to bias 27 to the potential of power supply VDD
type diffusion layer, 28.29 is the source and drain layer of the transistor 21, 30 is the P well layer, 31.32 is the source and drain layer of the transistor 24, 33 is the double layer 29 or 2
8°+N layer 25 or N type substrate 27. Parasitic lateral PNP with P-well layer 30 as emitter, base, and collector)
transistor, 34 is N-type substrate 27°P well layer so, N
Layer sxt collector, base.

It is a parasitic lateral NPN transistor with an emitter.

In FIGS. 1O and 11, when external noise (above the vDD level) enters the second layer 29 through the /4 wire 23,
A current 11 flows and becomes a base current of the lateral PNP transistor 33, and a collector current i is caused to flow to the P well layer 30 in accordance with its h□ (current amplification factor). Then, the potential of the P well layer 30 rises to the power supply VDD side, and the current increases for 1 s.
flows and lateral NPN ) transistor 34 turns on,
A current I4 flows through the N layer (ground potential). As a result, the potential of the substrate 27 is pulled to the ground side, the potential near the N layer 25 is lowered, and a base current of the lateral transistor 33 whose emitter is the second layer 28 flows. At this time, lateral NPN)
The transistor 34 is also in an on state and enters a latch-up phenomenon.

In other words, in a chip that has already been designed and evaluated, in order to guarantee the latch-up voltage and current for each terminal,
A/Tsudo peripheral area K> and countermeasures have been taken. However, when it comes to individual chips, countermeasures are generally taken only in areas from the neck to the inside of the chip, but not in areas outside the chip. This is because in the region extending from the pad to the outside of the transistor, only one conductivity type transistor exists at most, so latch-up does not occur in this region.

As described above, conventionally, 14-tank measures are taken to absorb surges in the region from the pad to the inside of the trigger. However, in large-scale integrated circuit devices such as those shown in FIGS. 8 to 11, each chip (
An instantaneous switching current from the transistor element also flows in the outside of the chip (chip equivalent area), and this does not become a surge current.The surge propagates to the chip fH through the semiconductor substrate of the semiconductor chip f1, causing the latch. In particular, when P and N channel transistors are located facing each other between chips 7'A and 1, latch-up is likely to occur.

Furthermore, in a chip capable of withstanding high speed operation, the output buffer's enabler/s is set low to improve its switching characteristics, thus inducing more switching current. Further, when the dead 23 is connected to an external terminal, a latch-up is induced between the chips A and B due to a surge from the outside.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to prevent the latch-up phenomenon in a large-scale integrated circuit having a plurality of chip-equivalent regions formed independently within the same semiconductor.

[Summary of the invention]

In order to prevent the latch-up phenomenon, the trigger current that propagates between the region where the P-channel transistor is formed and the region where the N-channel transistor is formed may be reduced therebetween. Therefore, in the present invention, a highly concentrated impurity layer with low resistance is provided in the opposing regions of a plurality of chip-equivalent regions or between the chig phase region and the outer edge of the chip, that is, in the region outside the chip-equivalent region. It biases the power supply level appropriately.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the following. 1st
The figure is a plan view of the same embodiment, FIG. 2 is a planar configuration diagram of the adjacent area between chip-equivalent regions, and FIG. 3 is a cross-sectional view of the same. Since this is an example of a case where this corresponds to that shown in FIG. 11, the corresponding parts are given the same reference numerals, and the explanation will be omitted, and the characteristic points will be explained.

The feature of this embodiment is that a high concentration N-type diffusion layer 41 is provided between the chip equivalent regions A and 1, and this is biased relative to the power supply VD (>0).

For those shown in Figures 1 to 3, the gendering Δ
Due to a surge from the pin 42 or a surge during switching of the low impedance buffer, a surge is applied to the second layer 29, and the current 11 flows from there through the substrate 27 to the power supply VDtl side. That is, this current flows into the AN layer 25 closest to the second layer 29 and is biased by vDDK/4.

This causes a base current of the parasitic lateral PNP transistor 33 and a collector current 13.

If the N layer 41 does not exist at ζζ, the power supply MDI) of the N layer 25 on the current flow side becomes a more positive Vl)D)
A potential gradient is generated between the N layer 26 and the N layer 26.

This means that a potential gradient occurs in the base region of the transistor based on the N layer 25 to the 8 layer 27,
This improves the current gain of the lateral transistor 33, making it easier to induce the aforementioned latch-up phenomenon. On the other hand, if a low resistance N layer 41 is inserted, the lateral transistor 3
This makes it possible to reduce the potential gradient within the transistor 30, reduce the current gain of the transistor 33, and prevent the latch-up phenomenon.

In the above embodiment, the case of an N-type substrate was explained, but in the case of a PH1 substrate, a P+ layer is used instead of the B s N'' layer 41.

This is used as the power source v1. It is clear that all you have to do is bias the level.

FIG. 4 shows another embodiment of the invention. That is, the high concentration diffusion layer 41 may be provided widely within the wiring region 5. Moreover, if the high concentration diffusion layer 41 is provided in the entire wiring region 6 as shown in FIG. 5, the effect will be even greater.

FIG. 6 shows a different embodiment of the present invention, in which the high concentration diffusion layer 4
The area where 1 is placed is surrounded by chip equivalent areas A and B, respectively. In this way, latch-up between the chip-equivalent regions A and B and the external terminals 4 can be prevented.

FIG. 7 shows a further different embodiment of the present invention, in which a high concentration diffusion layer 4
This is an example in which one noise power source 51 is provided separately from the power sources 52 of the chip equivalent areas A and B. In this way, since the bias power supply for the chip-equivalent regions A and B, which are unstable in the bias of the high concentration layer 41, is not used, a more stable bias supply to the high concentration diffusion layer 41 can be performed. .

Note that the present invention is not limited to those in which the structure of the chip equivalent region is a silicon gate structure, but can also be applied to structures such as an aluminum dart structure.

〔Effect of the invention〕

As explained above, according to the present invention, the latch-up phenomenon can be easily prevented by disposing a high concentration layer biased to the power supply level in the region facing the chip equivalent region or in the region surrounding the chip phase foil region. It is possible to reduce the chip equivalent area to one chip without modification. By burying the above-mentioned high concentration layer under the wiring region, latch-up can be prevented without increasing the chip size.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of the essential parts, FIG. 3 is a sectional view of the essential parts, and FIGS. A schematic plan view of a different embodiment; FIG. 8 is a schematic plan view of a conventional improved large-scale integrated circuit; FIG. 9 is a partial cross-sectional view of the same circuit; and FIG. 10 is a plan view of essential parts of the circuit. FIG. 11 is a sectional view of the main parts. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 5... Wiring area, 41... High concentration layer, A, B... Chip equivalent area. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 4 Figure 5 Wi

Claims (4)

[Claims] (1) A plurality of chip-equivalent regions each independently formed in the same semiconductor substrate, a wiring layer that selectively connects an electrode for leading out of the chip-equivalent region, and a wiring layer that selectively connects a plurality of chip-equivalent regions that are formed independently in the same semiconductor substrate; A large-scale integrated circuit device comprising a wiring area serving as an installation area for a wiring layer, and a highly concentrated layer inserted between at least the opposing chip-equivalent areas and biased to one power supply level. . (2) The large-scale integrated circuit device according to claim 1, wherein the chip-equivalent region has a complementary MOS configuration. (3) Claim 1, characterized in that the region where the high concentration layer is arranged is a region outside the chip equivalent region.
Large-scale integrated circuit device as described in Section. (4) The large-scale integrated circuit according to claim 1, 2, or 3, characterized in that a power source for biasing the high concentration layer is provided separately from a power source for the chip-equivalent region. Device.