JPH08321551A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit device of which has wirings of high performance and high reliability, and a manufacturing technique capable of easily manufacturing the device. CONSTITUTION: This semiconductor integrated circuit device is provided with a wiring layer 17 as a power supply wiring which is arranged, via an interlayer insulating film, on a signal wiring arranged on the lower layer wiring in a multilayered wiring structure, and a wiring layer 19 as an auxiliary meshy power supply wiring which is arranged on the wiring layer 17 via an interlayer insulating film. The wiring layer 19 as the auxiliary meshy power supply wiring is electrically connected with a region of the wiring layer 17 of the power supply wiring which bears insufficient wiring characteristics in the wiring layer 17 as the power supply wiring, via a through hole wiring in a through hole 20 formed in the interlayer insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit device having high-performance and highly reliable wiring and a technique effectively applied to its manufacturing technique. .

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, high integration and fine processing have been promoted, and accordingly, the wiring structure has become fine, and an excellent wiring structure has been demanded.

In recent years, ASs such as custom ICs, which are semiconductor integrated circuit devices corresponding to the specifications ordered by customers and the individual functions or circuits required by users, have been developed.
In ICs (Application Specific Intergrated Circuits), a large number of products are manufactured in small quantities in response to various customer orders and user requirements, and therefore, there is a demand for easy design and flexible manufacturing processes.

For example, in an ASIC using a gate array system, in order to facilitate the design of the ASIC and to make the manufacturing process flexible, a mesh-shaped power supply wiring is formed by using a lower wiring layer in a multilayer wiring of a semiconductor integrated circuit device, It is possible to arrange a plurality of logic circuit cells between the meshes of the power supply wiring.

Further, since high speed and high performance are required for a custom IC such as a processor IC which frequently uses a macro cell which employs a manual layout, a power supply wiring is arranged in each wiring layer in the multilayer wiring. It is possible to do it.

As a document describing the wiring structure in a semiconductor integrated circuit device having a logic block, there is, for example, the one described in Japanese Patent Application Laid-Open No. 54-20680.

[0007]

However, the present inventor has found that the above-described semiconductor integrated circuit device has various problems as described below.

That is, (1) In an ASIC using, for example, a gate array system, a mesh-like power supply wiring is formed by using a lower wiring layer in a multilayer wiring of a semiconductor integrated circuit device, and a logic circuit cell is provided between meshes of the power supply wiring. By arranging a plurality of wirings, the mesh-shaped power supply wiring becomes over-spec, and more wiring area than is used is used as power supply wiring, which is a cause of lowering the integration degree of the semiconductor integrated circuit device. ing.

Further, since the mesh-shaped power supply wiring is formed by using the lower wiring layer in the multi-layer wiring of the semiconductor integrated circuit device, there are many restrictions and design choices such as wiring layout in the multi-layer wiring. Since the characteristics are limited and the wiring structure is insufficient, it is a cause of deteriorating the characteristics of the semiconductor integrated circuit device.

(2) For example, in a custom IC such as a processor IC in which macro cells that employ a manual layout are frequently used, since power supply wirings are arranged in the wirings of each layer in the multilayer wiring, signals other than the power supply wirings are provided. Since complicated wiring such as wiring is arranged in each layer of the multi-layer wiring, it is difficult to provide sufficient high-performance power supply wiring. There is a problem that wiring cannot be obtained.

An object of the present invention is to provide a semiconductor integrated circuit device having high performance and highly reliable wiring.

An object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having high-performance and highly reliable wiring.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

The typical ones of the inventions disclosed in the present invention will be outlined below.

(1) In the semiconductor integrated circuit device of the present invention, the signal wiring arranged in the lower wiring in the multilayer wiring structure, and the first wiring arranged on the signal wiring via the first interlayer insulating film. Second on power supply wiring and first power supply wiring
Second mesh-like layer disposed via the inter-layer insulating film of
And the second power supply wiring is electrically connected to the selective area of the first power supply wiring through the through-hole wiring provided in the second interlayer insulating film.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of forming signal wirings of a first layer and a second layer on a substrate having a semiconductor element formed in a semiconductor region of the substrate, and a signal wiring. A step of forming a first interlayer insulating film and a first power wiring on the first power wiring, and a second step on the first power wiring.
The step of forming the interlayer insulating film and the mesh-shaped second power wiring, and the through holes are formed in the second interlayer insulating film and the second power wiring on the selective region of the first power wiring. After that, a step of electrically connecting the selective region of the first power supply wiring and the second power supply wiring by burying a conductive material in the through hole is included.

[0017]

[Action]

(1) According to the semiconductor integrated circuit device of the present invention described above,
A first power supply wiring arranged on a signal wiring in a multilayer wiring structure via a first interlayer insulating film, and a mesh arranged on a first power supply wiring via a second interlayer insulating film. A second power supply line having a rectangular shape, and the second power supply line is electrically connected to a selective region of the first power supply line through a through-hole line provided in the second interlayer insulating film. This allows the power supply wiring to be laid out according to its own design standard without being restricted by the layout of the signal wiring, and the second power supply wiring can be electrically connected to the area of the wiring characteristics of the first power supply wiring through the through-hole wiring. Therefore, the first power supply wiring having sufficient wiring characteristics can be obtained.

Therefore, since the power supply wiring having sufficient wiring characteristics is provided, the power supply rate is in a perfect state, and the abnormal power supply state can be prevented, so that the occurrence of electromigration and the noise margin are prevented. Since it is possible to prevent deterioration and the like, it is possible to improve the performance and reliability of the wiring layer such as high-speed operation.

Further, the first power supply wiring and the second power supply wiring are arranged on the upper layer of the signal wiring, and the first power supply wiring and the second power supply wiring are electrically connected only by the through-hole wiring. Therefore, the power supply wiring can be laid out according to its own design standard without being limited to the layout of the signal wiring, and the wiring area can be minimized. Therefore, a highly integrated semiconductor integrated circuit device should be provided. You can

(2) According to the method of manufacturing a semiconductor integrated circuit device of the present invention described above, the step of forming the first interlayer insulating film and the first power supply wiring on the signal wiring, and the first power supply wiring. A step of forming a second interlayer insulating film and a mesh-shaped second power wiring on the first power wiring, and a second interlayer insulating film and a second power wiring on the selective area of the first power wiring. After forming the through hole, by embedding a conductive material in the through hole, there is a step of electrically connecting the selective region of the first power supply wiring and the second power supply wiring. Since the first power supply wiring and the second power supply wiring are arranged in the upper layer and the electrical connection between the first power supply wiring and the second power supply wiring is performed only by the through hole wiring, the power supply wiring is a signal. Limited to the wiring layout It is possible to easily lay out according to its own design criteria and to easily electrically connect the first power supply wiring and the second power supply wiring only with the wiring for through holes, so it is possible to achieve high integration by minimizing the wiring area. In addition, the semiconductor integrated circuit device can be manufactured by a simple manufacturing process.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

1 to 12 are sectional views showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

The semiconductor integrated circuit manufacturing method of this embodiment is
For example, it is a method of manufacturing an ASIC such as a custom IC.

First, as shown in FIG. 1, a field formed of a silicon oxide film is applied to an element isolation region, which is a selective region on the surface of a semiconductor substrate 1 made of, for example, p-type silicon single crystal, by using a thermal oxidation process. The insulating film 2 is formed. Although not shown, a channel stopper layer for preventing inversion is formed under the field insulating film 2.

Next, as shown in FIG. 2, a gate insulating film 3 made of silicon oxide is formed in the active region surrounded by the field insulating film 2, and a gate electrode made of polycrystalline silicon is formed on the gate insulating film 3. 4 is formed. The gate electrode 4 is formed by sequentially depositing an insulating film 5 made of a polycrystalline silicon film and a silicon oxide film on the semiconductor substrate 1 and sequentially etching these. After that, the sidewall insulating film 6 made of silicon oxide is formed on the sidewall of the gate electrode 4.

Next, an n-type impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 to form an n-type semiconductor region 7 serving as a source and a drain.

Next, as shown in FIG. 3, an insulating film 8 is formed on the semiconductor substrate 1. As the insulating film 8, a silicon oxide film or the like formed by the CVD method can be used.

In the manufacturing process of the semiconductor integrated circuit device described above, the ASIC such as a custom IC is mounted on the semiconductor substrate 1.
P-channel MOSF as a semiconductor element which is a component of
Although the ET is formed, the n-channel MOSFET other than the p-channel MOSFET and the CMO are formed on the semiconductor substrate 1.
A mode in which various semiconductor elements such as SFET, bipolar transistor, and capacitive element are formed can be adopted.

Also, for example, an ASIC such as a custom IC
As a substrate for forming a semiconductor element which is a component of
SOI (Silicon on Ins), which is a different substrate from the semiconductor substrate
An SOI substrate in which a single crystal thin film of silicon is formed on an insulating region of an insulator structure can be used.

The above-described manufacturing process of the semiconductor integrated circuit device can be performed by combining various prior arts. The main part of the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention is the wiring layer of the semiconductor integrated circuit device and the manufacturing method thereof. Based on this, in order to simplify the description hereafter, the semiconductor substrate 1 formed by the above-described manufacturing process is used as the starting material for the p-channel M.
A substrate 9 on which an OSFET is formed is comprehensively illustrated, the internal structure of the substrate 9 having an internal structure is omitted, and the dimensions shown in the drawing are reduced.

Next, as shown in FIG. 4, a first wiring layer 10 as a signal wiring is formed on the surface of the base body 9. The first wiring layer 10 is, for example, an aluminum layer formed by CVD (Ch
It is formed by the emical vapor deposition method. As a material of the wiring layer 10, in order to secure the characteristics of stress migration resistance and electromigration resistance, an aluminum layer as the wiring layer 10 is
A wiring layer in which a wiring structure is laminated by using a refractory metal layer such as a titanium nitride (TiN) layer can be used as a lower layer or an upper layer thereof. Further, as the wiring layer 10,
A combination of a polycrystalline silicon layer or a laminated layer of a polycrystalline silicon layer and a refractory silicide layer having electrical conductivity can be used.

The wiring layer 10 includes a wiring layer electrically connected to the n-type semiconductor region 7 through a through hole provided in the insulating film 8 in a region (not shown). It also includes a wiring layer to be used.

Next, a photoresist film 11 is formed on the surface of the wiring layer 10.

Next, as shown in FIG. 5, a pattern for the first wiring layer is formed on the photoresist film 11 by using a photomask for the first wiring layer using the photolithography technique. .

Next, using the photoresist film 11 as an etching mask, the wiring layer 10 is selectively etched by a dry etching method or a wet etching method to pattern the wiring layer 10. Next, an operation of removing the photoresist film 11 that has become unnecessary is performed.

Next, as shown in FIG. 6, a first interlayer insulating film 12 is formed on the entire surface so as to cover the first wiring layer 10. The interlayer insulating film 12 is, for example, a silicon oxide film formed by a CVD method, and then an SOG (Spin On Glass) film is spin-coated to perform surface flattening (spinner).
Are formed by using. Note that the interlayer insulating film 12 is formed of PSG (Ph
ospho Silicate Glass) film or BPSG (Boro Phosp)
It is possible to adopt various modes such as an interlayer insulating film having a laminated structure in which a ho Silicate Glass) film is formed by a CVD method.

Next, a photoresist film 13 is formed on the surface of the interlayer insulating film 12.

Next, as shown in FIG. 7, a pattern for through holes is formed in the photoresist film 13 by using a photo mask for through holes using a photolithography technique.

Next, using the photoresist film 13 as an etching mask, the inter-layer insulating film 12 is selectively etched by a dry etching method or a wet etching method, and a selective region of the inter-layer insulating film 12 is exposed. The hole 14 is formed. Next, an operation of removing the photoresist film 13 that has become unnecessary is performed.

Next, as shown in FIG.
A second wiring layer 15 as a signal wiring is formed on the wiring layer 4 and the interlayer insulating film 12. The wiring layer 15 is, for example, an aluminum layer formed by a CVD method. Second wiring layer 1
5 can have various modes such as a wiring layer having a laminated structure made of the same material as that of the first wiring layer 10 described above.

Next, a pattern as a signal wiring is formed on the second wiring layer 15 by using the photolithography technique and the selective etching technique.

Next, after forming the second interlayer insulating film 16 on the second wiring layer 15, the third wiring layer 17 as the power supply wiring is formed. The second interlayer insulating film 16 is
The same material as that of the first interlayer insulating film 12 can be used. In addition, the third wiring layer 17 as the power wiring
Can be performed using a material similar to that of the first wiring layer 10 or the second wiring layer 15.

The wiring layer 17 includes a wiring layer electrically connected through a through hole provided in the insulating film 16 in a region (not shown), and is electrically connected to the n-type semiconductor region 7. It also includes a wiring layer to be used.

Next, as shown in FIG. 9, a pattern as a power supply wiring is formed on the third wiring layer 17 by using the photolithography technique and the selective etching technique.

That is, after forming a photoresist film on the surface of the wiring layer 17, a photomask for the third wiring layer is used to form the photoresist film for the third wiring layer using the photolithography technique. Pattern is formed.

Next, using the photoresist film as an etching mask, the wiring layer 17 is selectively etched by dry etching or wet etching to pattern the wiring layer 17. Next, the work of removing the photoresist film that has become unnecessary is performed.

FIG. 13 shows a third wiring layer 17 as a power supply wiring in the chip of the semiconductor integrated circuit device of this embodiment.
It is a schematic plan view showing.

Next, as shown in FIG. 10, the third interlayer insulating film 18 is formed on the third wiring layer 17 as the power supply wiring.
After forming, the fourth wiring layer 19 as an auxiliary power supply wiring is formed. The third-layer interlayer insulating film 17 can be formed using the same material as the first-layer interlayer insulating film 12 or the second-layer interlayer insulating film 16. Further, the fourth wiring layer 19 as the power supply wiring can be formed by using the same material as that of the first wiring layer 10, the second wiring layer 15 or the third wiring layer 17.

Next, a pattern as an auxiliary mesh-shaped power supply wiring is formed on the fourth wiring layer 19 by using the photolithography technology and the selective etching technology.

That is, after forming a photoresist film on the surface of the wiring layer 19, a photomask for the fourth wiring layer is used to form the photoresist film for the fourth wiring layer by the photolithography technique. Pattern is formed.

Next, using the photoresist film as an etching mask, the wiring layer 19 is selectively etched by dry etching or wet etching to pattern the wiring layer 19. Next, the work of removing the photoresist film that has become unnecessary is performed.

FIG. 14 is a schematic plan view showing the fourth wiring layer 19 as the mesh-shaped power supply wiring in the chip of the semiconductor integrated circuit device of this embodiment.

In this case, in the fourth wiring layer 19 as the auxiliary mesh-shaped power wiring, for example, the wiring pitch of the mesh-shaped power wiring is the minimum wiring pitch of the third wiring layer 17 as the power wiring. By adopting the mode in which the value is adopted, the wiring layer 19 as the auxiliary power supply wiring
The size of the mesh is set such that the wiring layer 19 as the fourth-layer mesh-shaped power supply wiring is arranged on the third wiring layer 17 as all the power supply wirings.

Next, as shown in FIG. 11, after detecting a region having insufficient wiring characteristics in the third wiring layer 17 as a power supply wiring, the interlayer insulating film 18 and the fourth layer above the region are detected. Through holes 20 are formed in the wiring layer 19 by using the photolithography technique and the selective etching technique.

The detection of a region having insufficient wiring characteristics in the third wiring layer 17 as the power supply wiring can be performed by inspection such as analysis by simulation.

FIG. 15 is a schematic perspective view showing the position of the through hole 20 in the chip of the semiconductor integrated circuit device of this embodiment. Note that, in FIG. 15, the dimensions of each region are shown in a modeled state in which they are in a state different from an actual state and are in a see-through state for the sake of clarity and simplification in the drawing.

Next, as shown in FIG. 12, a through hole 20 is filled with a conductive material to form a through hole wiring 21.

Next, after the through-hole wiring 21 is formed, an inspection such as an analysis by simulation is performed to check whether the region of the third wiring layer 17 as the power supply wiring having insufficient wiring characteristics is reinforced. Inspect whether or not.

As a result of the inspection, when the region having insufficient wiring characteristics in the third wiring layer 17 as the power supply wiring is not reinforced, the formation of the through hole 20 and the formation of the through hole wiring 21 described above. Is performed again, and the power supply wiring having complete wiring characteristics is obtained by using the fourth wiring layer 19 as the auxiliary mesh-shaped power supply wiring.

By this manufacturing process, 3
Since it is possible to electrically connect the region of insufficient wiring characteristics in the wiring layer 17 of the fourth layer and the wiring layer 19 of the fourth layer as the mesh-shaped power wiring,
The area where the wiring characteristics are insufficient in the wiring layer 17 of the second layer is
Since the fourth wiring layer 19 as the mesh-shaped power supply wiring can be electrically connected and reinforced,
The wiring characteristics of the power wiring including the third-layer power wiring and the fourth-layer mesh-shaped power wiring can be made sufficient.

In FIG. 15, the through hole 20
Although only one is illustrated for the sake of simplification in the drawing, a plurality of through holes 20 are correspondingly provided on the plurality of regions of the wiring layer 17 as the power supply wiring having incomplete wiring characteristics. Has been formed.

The fourth wiring layer 19 as an auxiliary mesh-shaped power supply wiring in the semiconductor integrated circuit device of this embodiment.
In the above, all mesh sizes of the wiring layer 19 as the auxiliary power wiring, such as a mode in which the wiring pitch of the mesh-shaped power wiring is set to the minimum value of the wiring pitch of the third wiring layer 17 as the power wiring, The size is such that the wiring layer 19 as the fourth-layer mesh-shaped power supply wiring is arranged on the third wiring layer 17 as the power supply wiring.

Therefore, after the wiring pattern of the lower wiring layer, that is, the wiring pattern of the third wiring layer 17 as the power supply wiring is determined, the mesh of the wiring layer 19 as the auxiliary mesh-like power supply wiring is selected according to the situation. Since the size can be determined, even in an ASIC such as an IC that uses many irregular macrocells such as a processor IC, there is no constraint in designing the wiring pattern of the third wiring layer 17 as a power supply wiring, which is large. Since there is a degree of freedom, it is possible to easily design the power supply wiring, and it is possible to adopt an automatic wiring system using a CAD system that supports wiring design of the semiconductor integrated circuit device.

The third wiring layer 1 as the power supply wiring
After the wiring pattern 7 is determined, the size of the mesh of the wiring layer 19 as the auxiliary mesh power supply wiring can be determined according to the situation, and thus the data corresponding to the pattern of the wiring layer 17 as the power supply wiring can be determined. Since the pattern of the wiring layer 19 as the auxiliary mesh-like power supply wiring can be formed by the automatic wiring system using the CAD system that supports the wiring design of the semiconductor integrated circuit device using It can be formed using a manufacturing process.

Further, in the manufacturing process of the through hole 20 and the through hole wiring 21, the data corresponding to the pattern of the wiring layer 19 as the auxiliary mesh-like power supply wiring is used to support the wiring design of the semiconductor integrated circuit device. Since an automatic wiring system using a CAD system can be adopted, a wiring pattern can be formed by a simple manufacturing process.

Next, a surface protective film (not shown) such as a nitric oxide film is formed on the fourth wiring layer 19, thereby completing the manufacturing process of the semiconductor integrated circuit device.

In the semiconductor integrated circuit device of this embodiment described above, the third wiring layer 17 and the fourth wiring layer 19 are provided.
Is used exclusively as the power supply wiring, but as another mode, if there is a margin other than the area of the third wiring layer 17 or the fourth wiring layer 19 as the power supply wiring, the By using the spare area as signal wiring,
The third layer or 4 to release the severe situation of signal wiring
A spare area of the wiring layer of the layer can be used as a signal wiring. Further, in designing the wiring, the signal wiring or the power supply wiring can be arranged by using the wiring layers of the fifth layer or more, if necessary.

In the semiconductor integrated circuit device of this embodiment,
A wiring layer 17 as a power supply wiring arranged on the signal wiring in the multilayer wiring structure via the interlayer insulating film 16 and an auxiliary mesh-shaped wiring arranged on the wiring layer 17 via the interlayer insulating film 18. A wiring layer 19 as a power supply wiring is provided, and a through hole wiring 21 provided in the interlayer insulating film 18 in a selective region of the wiring layer 17 as a power supply wiring.
Wiring layer 1 as auxiliary mesh-like power supply wiring through
9 is electrically connected.

Therefore, the wiring layer 17 and the wiring layer 19 as the power supply wiring can be laid out according to its own design standard without being limited to the layout of the signal wiring, and the wiring layer 17 as the power supply wiring has an insufficient wiring characteristic region. Since the wiring layer 19 as the auxiliary mesh-shaped power supply wiring can be electrically connected through the through-hole wiring 21, the power supply wiring having sufficient wiring characteristics can be obtained.

Therefore, since the power supply wiring having sufficient wiring characteristics is provided, the power supply rate has a perfect state, and the abnormal power supply state can be prevented, so that the occurrence of electromigration and the noise margin are prevented. Since it is possible to prevent deterioration and the like, it is possible to improve the performance and reliability of the wiring layer such as high-speed operation.

Further, the power supply wiring is arranged on the upper layer of the signal wiring, and the wiring layer 17 as the power supply wiring and the wiring layer 19 as the mesh-shaped power supply wiring are electrically connected only by the through-hole wiring 21. As a result, the power supply wiring can be laid out according to its own design standard without being restricted by the layout of the signal wiring, and the wiring area can be minimized, so that a highly integrated semiconductor integrated circuit device can be obtained. .

In the method of manufacturing the semiconductor integrated circuit device of this embodiment, the step of forming the interlayer insulating film 16 and the wiring layer 17 as the power supply wiring on the signal wiring, and the step of forming the interlayer insulating film 18 and the wiring layer 17 on the wiring layer 17 are performed. The step of forming the wiring layer 19 as the mesh-shaped power wiring, the through hole 20 in the interlayer insulating film 18 and the wiring layer 19 as the mesh-shaped power wiring on the selective region of the wiring layer 17 as the power wiring. After the formation of the wiring, a conductive material is embedded in the through holes 20, so that a selective region of the wiring layer 18 as the power wiring and the wiring layer 1 as the mesh-shaped power wiring are formed.
9 has a step of electrically connecting.

Therefore, the power supply wiring is arranged on the upper layer of the signal wiring, and the wiring layer 17 as the power supply wiring and the wiring layer 19 as the auxiliary mesh-like power supply wiring are electrically connected only by the through-hole wiring 21. Therefore, the power supply wiring is not limited to the layout of the signal wiring and can be easily laid out according to the original design criteria, and the wiring layer 1 as the power supply wiring can be easily provided only by the through-hole wiring 21.
7 and the wiring layer 19 as the auxiliary mesh-shaped power supply wiring can be electrically connected to each other, the wiring area can be minimized to achieve high integration and a semiconductor integrated circuit device can be manufactured by a simple manufacturing process. .

The fourth wiring layer 19 as an auxiliary mesh-shaped power supply wiring in the semiconductor integrated circuit device of this embodiment.
In the above, all mesh sizes of the wiring layer 19 as the auxiliary power wiring, such as a mode in which the wiring pitch of the mesh-shaped power wiring is set to the minimum value of the wiring pitch of the third wiring layer 17 as the power wiring, The size is such that the wiring layer 19 as the fourth-layer mesh-shaped power supply wiring is arranged on the third wiring layer 17 as the power supply wiring.

Therefore, after the wiring pattern of the lower wiring layer, that is, the wiring pattern of the third wiring layer 17 as the power supply wiring is determined, the mesh of the wiring layer 19 as the auxiliary power supply wiring is formed according to the situation. Since the size can be determined, even in an ASIC such as an IC that uses many irregular macrocells such as a processor IC, there is no constraint in designing the wiring pattern of the third wiring layer 17 as a power supply wiring, which is large. Since there is a degree of freedom, it is possible to easily design the power supply wiring, and it is possible to adopt an automatic wiring system using a CAD system that supports wiring design of the semiconductor integrated circuit device.

Also, the third wiring layer 1 as the power wiring
After the wiring pattern 7 is determined, the size of the mesh of the wiring layer 19 as the auxiliary mesh power supply wiring can be determined according to the situation, and thus the data corresponding to the pattern of the wiring layer 17 as the power supply wiring can be determined. Since the pattern of the wiring layer 19 as the auxiliary mesh-like power supply wiring can be formed by the automatic wiring system using the CAD system that supports the wiring design of the semiconductor integrated circuit device using It can be formed using a manufacturing process.

Further, in the manufacturing process of the through hole 20 and the through hole wiring 21, the data corresponding to the pattern of the wiring layer 19 as the auxiliary mesh-like power supply wiring is used to support the wiring design of the semiconductor integrated circuit device. Since an automatic wiring system using a CAD system can be adopted, a wiring pattern can be formed by a simple manufacturing process.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the MOSF
The semiconductor integrated circuit device having the ET provided on the substrate and the method for manufacturing the semiconductor integrated circuit device have a CMOSFET, a bipolar transistor, or a BiMOS or BiCMOS in which a MOSFET and a bipolar transistor are combined on the substrate.
The present invention can be applied to a semiconductor integrated circuit device having various semiconductor elements such as structures and manufacturing technology thereof.

[0080]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) In the semiconductor integrated circuit device of the present invention, an interlayer insulating film is formed on a wiring layer as a power supply wiring arranged on the signal wiring in the multilayer wiring structure via an interlayer insulating film and on the wiring layer. It has a wiring layer as an auxiliary mesh-like power supply wiring arranged via the auxiliary mesh-like wiring through the through-hole wiring provided in the interlayer insulating film in a selective region of the wiring layer as a power supply wiring. The wiring layer as the power supply wiring is electrically connected.

Therefore, the wiring layer as the power supply wiring and the wiring layer as the auxiliary mesh-shaped power supply wiring can be laid out according to the original design standard without being restricted by the layout of the signal wiring, and the wiring layer as the power supply wiring can be formed without any limitation. Since the wiring layer as the auxiliary mesh-shaped power supply wiring can be electrically connected to the region having the sufficient wiring characteristics through the through-hole wiring, the power supply wiring having the sufficient wiring characteristics can be obtained.

Therefore, since the power supply wiring having sufficient wiring characteristics is provided, the power supply rate has a perfect state, and the abnormal power supply state can be prevented, so that the occurrence of electromigration and the noise margin are prevented. Since it is possible to prevent deterioration and the like, it is possible to improve the performance and reliability of the wiring layer such as high-speed operation.

By disposing the power supply wiring on the upper layer of the signal wiring and electrically connecting the wiring layer as the power supply wiring and the wiring layer as the mesh-shaped power supply wiring only by the through-hole wiring, The power supply wiring can be laid out according to a unique design standard without being limited to the layout of the signal wiring, and the wiring area can be minimized, so that the semiconductor integrated circuit device having a high degree of integration can be obtained.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming an interlayer insulating film and a wiring layer as a power supply wiring on the signal wiring, and an interlayer insulating film and a mesh shape on the wiring layer. The step of forming a wiring layer as the power supply wiring, and after forming the through hole in the interlayer insulating film and the wiring layer as the mesh-shaped power supply wiring on the selective region of the wiring layer as the power supply wiring, the through hole is formed. By embedding a conductive material in the wiring layer, a step of electrically connecting the selective region of the wiring layer as the power source wiring and the wiring layer as the mesh-shaped power source wiring is provided.

Therefore, the power supply wiring is arranged on the upper layer of the signal wiring, and the wiring layer as the power supply wiring and the wiring layer as the auxiliary mesh-shaped power supply wiring are electrically connected only by the through-hole wiring. The power supply wiring is not limited to the layout of the signal wiring and can be easily laid out according to the original design criteria, and the wiring layer for the power supply wiring and the wiring layer for the auxiliary mesh-shaped power supply wiring can be easily formed only by the wiring for the through holes. Since they can be electrically connected to each other, the semiconductor integrated circuit device can be manufactured by a simple manufacturing process while achieving high integration by minimizing the wiring area.

(3) In the fourth wiring layer as the auxiliary mesh-shaped power wiring in the semiconductor integrated circuit device of the present invention, for example, the wiring pitch of the mesh-shaped power wiring is the third wiring as the power wiring. The size of the mesh of the wiring layer as the auxiliary power wiring, such as the mode in which the wiring pitch of the layer is set to the minimum value, is set on the third wiring layer as all the power wiring, and the mesh-shaped power wiring of the fourth layer. The wiring layer has a size such that it is arranged.

Therefore, after the wiring pattern of the lower wiring layer, that is, the wiring pattern of the third wiring layer as the power supply wiring is determined, the size of the mesh of the wiring layer as the auxiliary power supply wiring is determined according to the situation. Therefore, even in an ASIC such as an IC that uses a lot of irregular macro cells such as a processor IC, there is no constraint in designing the wiring pattern of the third wiring layer as a power supply wiring, and a large degree of freedom can be obtained. Therefore, the power supply wiring can be easily designed, and an automatic wiring system using a CAD system that supports the wiring design of the semiconductor integrated circuit device can be adopted.

Further, since the wiring pattern of the third wiring layer as the power supply wiring is determined, the size of the mesh of the wiring layer as the auxiliary mesh-shaped power supply wiring can be determined according to the situation. An auxiliary mesh-like power supply wiring pattern is formed by an automatic wiring system using a CAD system that supports wiring design of a semiconductor integrated circuit device using data corresponding to a wiring layer pattern as power supply wiring. Therefore, the wiring pattern can be formed using a simple manufacturing process.

Further, in the manufacturing process of the through hole and the wiring for the through hole, the CAD system for supporting the wiring design of the semiconductor integrated circuit device by using the data corresponding to the pattern of the wiring layer as the auxiliary mesh-shaped power supply wiring. Since an automatic wiring system using can be adopted, the wiring pattern can be formed using a simple manufacturing process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 13 is a schematic plan view showing a third wiring layer as a power supply wiring in a chip of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 14 is a schematic plan view showing a fourth wiring layer as a mesh-shaped power supply wiring in a chip of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 15 is a schematic perspective view showing positions of through holes in a chip of a semiconductor integrated circuit device which is an embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 insulating film 6 sidewall insulating film 7 n-type semiconductor region 8 insulating film 9 substrate 10 wiring layer 11 photoresist film 12 interlayer insulating film 13 photoresist film 14 through hole 15 wiring layer 16 interlayer insulating film 17 wiring layer 18 interlayer insulating film 19 wiring layer 20 through hole 21 through hole wiring

Claims (9)

[Claims] 1. A signal wiring arranged in a lower layer wiring in a multilayer wiring structure, a first power wiring arranged on the signal wiring via a first interlayer insulating film, and the first power wiring. Has a mesh-shaped second power supply line disposed above the second interlayer insulation film, and is provided on the second interlayer insulation film in a selective region of the first power supply line. The semiconductor integrated circuit device, wherein the second power supply wiring is electrically connected through the through hole wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein an uppermost wiring layer in a multilayer wiring structure is used as the second power supply wiring. 3. The semiconductor integrated circuit device according to claim 1, wherein a mesh size of the second power supply wiring is such that the second power supply wiring is arranged on all the first power supply wirings. A semiconductor integrated circuit device having a size as described above. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the first power supply wiring is a power supply wiring in an ASIC. 5. A step of forming a semiconductor element in a semiconductor region of a substrate, a step of forming first and second layer signal wirings on the substrate, and a first interlayer insulating layer on the signal wirings. Forming a film, forming a first power supply wiring on the first interlayer insulation film, and forming a second interlayer insulation film on the first power supply wiring, and then forming the second Forming a mesh-shaped second power supply wiring on the inter-layer insulation film, and forming the second inter-layer insulation film and the second power supply wiring on the selective region of the first power supply wiring. After the through hole is formed, a conductive material is embedded in the through hole to electrically connect the selective region of the first power supply line to the second power supply line. Manufacturing method of integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the size of the mesh of the second power supply wiring is such that the second power supply wiring is above all the first power supply wirings. A method of manufacturing a semiconductor integrated circuit device, characterized in that the size of the semiconductor integrated circuit device is set. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the mesh-shaped wiring pitch of the second power supply wirings is a minimum value of the wiring pitch of the first power supply wirings. A method of manufacturing a semiconductor integrated circuit device having a feature. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 5, 6 or 7, wherein the substrate is an SOI substrate or a semiconductor substrate. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 5, 6, 7 or 8, wherein the step of forming the first power supply wiring, the second power supply wiring and the through hole comprises an automatic wiring system. A method of manufacturing a semiconductor integrated circuit device, comprising: