JPH034561A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the production time of a circuit device of this design by a method wherein signal wirings of an X direction are increased in number at a third wiring taking advantage of spaces between basic cells and the surfaces of the basic cells and other signal wirings of a Y direction are increased in number at a second wiring, whereby a circuit is enhanced in mounting rate. CONSTITUTION:A first signal wiring 38 is formed on a logic LSI semiconductor wafer on which basic cells have been arranged using a formed semiconductor manufacturing mask, and then an interlaminar insulating film 39, a connection hole 40, a second signal wire 41, an interlaminar insulating film 42, a connection hole 43, a third signal wiring 44, an interlaminar insulating film 45, a fourth signal wiring 46, and a passivation film 47 are successively formed to constitute a logic LSI. On the other hand, signal wirings of an X direction are increased in number at the third signal wiring 44 by making the wirings small in pitch basing on the X direction wiring information of an X-Y grating wiring channel region, and furthermore the second signal wiring 41 of a Y direction is increased in arrangement number.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device that employs a gate array method in which multiple layers of wiring are formed in an automatic wiring placement system. It is related to effective technology.

[Conventional technology]

The logic LSI (semiconductor integrated circuit device with built-in logic circuit) currently being developed by the present inventor employs a gate array method.

A logic LSI employing the gate array method is formed by the following semiconductor manufacturing process.

First, a semiconductor substrate on which basic cells having a basic design are regularly arranged is prepared in advance. The basic cell is constructed by incorporating, for example, a bipolar transistor, a resistance element, and a capacitance element.

Next, wires are connected within the basic cells arranged on the surface of the semiconductor substrate and between the basic cells (between logic circuits) based on the logic design to obtain a desired logic function. The connection is performed using multiple layers of aluminum signal wiring.

Logic LSIs employing this type of gate array system are characterized by shortening the time required to complete the product. Also.

This type of logic LSI has the feature that other logic functions can be obtained simply by changing the wiring pattern.

In the logic LSI, as the number of gates increases, the area occupied by basic cells tends to increase, and the area occupied by wiring regions (wiring channel regions) in which connections formed between basic cells are arranged tends to decrease. Therefore, the logic LSI that the inventor is currently developing
Although this is not a known technique, it is constructed with a four-layer wiring structure that effectively uses areas between and above the basic cells as wiring areas. The first layer wiring, the second layer wiring, and the third layer wiring are mainly composed of signal wiring. The fourth layer wiring is mainly composed of signal wiring and power wiring.

The first layer wiring is arranged as a signal wiring that connects logic circuits between basic cells, and is also arranged as an intra-basic cell wiring that connects each semiconductor element within a basic cell. Each of the second layer wiring and the third layer wiring is arranged as a signal wiring that connects the logic circuits.

Japanese Unexamined Patent Publication No. 60-22337 describes a semiconductor integrated circuit device employing a gate array method using a three-layer wiring structure. However, since the wiring in each layer is placed only in the wiring area between basic cells, we cannot expect a significant increase in the number of signal wirings, and semiconductor integrated circuit devices that use this gate array method are limited in the number of gates. As the number of signal lines increases, the area occupied by the interconnection area between basic cells decreases, so in this respect as well, a significant increase in the number of signal interconnections cannot be expected.

The connection pattern of the logic LSI currently being developed by the present inventor is formed by an automatic wiring placement system (DA) that uses a computer for two-dimensional processing. In other words, the automatic wiring placement system automatically places the information of the logically designed logic circuit, and also automatically places the information about the logical circuit in the x-y grid wiring channel area that is virtually set in the memory space. Connection information (wiring information) that connects circuits can be placed. In the automatic wiring placement system, wiring information for the first layer wiring and wiring information for the third layer wiring are placed in the X direction of the xy grid wiring channel region. The wiring information for the second layer wiring is x
-y Arranged in the X direction of the lattice wiring channel region. Connection between first layer wiring and second layer wiring.

Connections between the 2Mth wiring and the third layer wiring are each made at a predetermined lattice point in the XY lattice wiring channel region.

When wiring information is automatically placed by this automatic wiring placement system, a mask for semiconductor manufacturing is created based on this wiring information. This semiconductor manufacturing mask is used for the logic LSI.
It has a pattern of connections to be formed. Then, by using this semiconductor manufacturing mask and performing a semiconductor wafer manufacturing process, the logic L of the multilayer wiring structure described above is
SI can be formed.

Regarding logic LSIs that adopt the gate array method, see 1, for example, Science Forum Co., Ltd., VLSI
It is described in Device Handbook, published on November 28, 1981, pages 354 to 416.

[Problem to be solved by the invention]

The present inventor discovered that the multilayer wiring structure of a logic LSI employing the gate array method described above causes the following problems.

In the multilayer wiring structure, the step shape of the lower layer wiring, for example, the first layer wiring, is transmitted to the surface of the interlayer insulating film formed above, and the step shape is formed on the surface of the interlayer insulating film. The step shape on the surface of this interlayer insulating film grows larger as the interlayer insulating film becomes an upper layer. To deal with this phenomenon, in the semiconductor wafer manufacturing process, it is necessary to increase the wiring width dimension, the space between wirings, etc. toward the upper layer to ensure a large processing margin. That is, the wiring pitch of the second layer wiring is larger than that of the first layer wiring, and the wiring pitch of the third layer wiring is larger than that of the second layer wiring. For this reason, the number of third-layer wiring, which is the top layer signal wiring, is particularly small, and the number of signal wiring extending in the The ratio of the number of circuits implemented to the number of circuits that can be implemented decreases.

Further, since the signal wiring extending in the X direction is composed of the first layer wiring and the third layer wiring, the number of second layer wiring, that is, the signal wiring extending in the X direction is insufficient. For this reason, the implementation rate of logic circuits decreases as described above.

An object of the present invention is to provide a technique that can improve the circuit mounting rate in a semiconductor integrated circuit device that employs a gate array method.

Another object of the present invention is to provide a technique capable of achieving the above object by increasing the number of signal wirings extending in the X direction in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of achieving the above object by increasing the number of signal wirings extending in the X direction in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique for achieving the above object and shortening the product completion time in the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a semiconductor integrated circuit device that employs a gate array method, based on the wiring information placed in the X direction of the X-Y lattice wiring channel region of the automatic wiring placement system, the first layer is In addition to placing the eye wiring, third layer wiring is placed between the basic cells and on the basic cells, and based on the wiring information placed in the Y direction of the X-Y lattice wiring channel region, the wiring between the basic cells and the basic A second layer wiring is arranged on the cell, and the wiring pitch of the third layer wiring is configured to be substantially the same as or smaller than the wiring pitch of the first layer wiring.

(2) In a semiconductor integrated circuit device that adopts a gate array method, based on the wiring information placed in the X direction of the X-Y lattice wiring channel region of the automatic wiring placement system, the first layer is In addition to placing the eye wiring, third layer wiring is placed between basic cells and on the basic cells, and based on the wiring information placed in the Y direction of the x-y lattice wiring channel region, the A second layer wiring is arranged on the cell, and the wiring pitch of the second layer wiring is configured to be substantially the same as or smaller than the wiring pitch of the first layer wiring.

(3) In a semiconductor integrated circuit device that employs a gate array method, the first layer wiring is placed between basic cells based on the wiring information placed in the X direction of the X-Y lattice wiring channel region of the automatic wiring placement system. At the same time, the third layer wiring is placed between the basic cells and on the basic cells, and the third layer wiring is placed between the basic cells and on the basic cells based on the wiring information placed in the Y direction of the x-y lattice wiring channel region. A second layer wiring is arranged, and the wiring pitch of each of the second layer wiring and the third layer wiring is configured to be substantially the same as the wiring pitch of the first layer wiring.

[For production]

According to the above-mentioned means (1), the number of signal wirings extending in the X direction is increased by the third layer wiring by utilizing the space between the basic cells and on the basic cells, and the number of signal wirings extending in the Y direction is increased. The number of wires placed can be increased with the second layer of wires, so
It is possible to improve the degree of freedom in wiring placement in the automatic wiring placement system and improve the implementation rate of logic circuits. Since the number of layer wiring and second layer wiring can be equalized, the degree of freedom in wiring placement in the automatic wiring placement system can be further improved, and the implementation rate of logic circuits can be further improved. can.

According to the above-mentioned means (2), the number of signal wirings extending in the X direction is increased by the third layer wiring by utilizing the space between the basic cells and on the basic cells, and the number of signal wirings extending in the Y direction is increased. The number of wires placed can be increased with the second layer of wires, so
It is possible to improve the degree of freedom in wiring placement in the automatic wiring placement system and improve the implementation rate of logic circuits. Since the number of wires between the layer wiring and the second layer wiring can be equalized, the degree of freedom in wiring placement in the automatic wiring placement system can be further improved, and the implementation rate of logic circuits can be further improved. can. Furthermore, when the wiring pitches of the first layer wiring and the second layer wiring are substantially the same, the first layer wiring and the second layer wiring can be connected to each other at any lattice point in the Since connections with wiring can be made, the degree of freedom in wiring placement in an automatic wiring placement system can be improved, and the implementation rate of logic circuits can be improved.

According to the above-described means (3), the effects of (1) and (2) can be achieved, and the first layer input into the X-Y lattice wiring channel area of the automatic wiring placement system Since the wiring information for wiring, second layer wiring, and third layer wiring is not subjected to resosen processing or blowmono processing, the calculation processing time in the automatic wiring placement system is reduced by the amount corresponding to these processing steps. , product completion time can be shortened.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a logic LSI employing a gate array method.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 2 (chip layout diagram) shows a schematic configuration of a logic LSI (semiconductor integrated circuit device) employing a gate array system, which is an embodiment of the present invention.

As shown in FIG. 2, a logic LSI (LSI) is composed of a semiconductor chip (semiconductor pellet) having a rectangular plane.

External terminals (
A plurality of bonding pads) 10 are arranged. External terminal 10 is configured to establish an electrical connection with an external device. Inside the external terminal 10, a plurality of human output buffer circuits 11 are arranged around the logics L S and I. The input/output buffer circuit 11 is arranged at a position corresponding to the arrangement of the external terminals 10.

In the area surrounded by the covered sofa circuit 11, a logic circuit section is provided in the logic LSI. In the logic circuit section, a plurality of basic cells 12 having a basic design are regularly arranged in a matrix. A plurality of basic cells 12 are arranged in the row direction (X direction) in FIG.
Configure. Each basic cell column 13 is arranged in a plurality of columns with wiring regions (wiring channel regions) 14 interposed in the column direction (X direction).

The basic cell 12 is a logic LSI employing a gate array system which is currently being developed by the present inventor, and includes, for example, 100 to 200 basic elements. The basic elements are transistors, resistive elements and capacitive elements. That is, the basic cell 12 is configured to be able to configure a predetermined logic circuit. Among the basic elements arranged in the basic cell 12, the transistors are 5EPT (Selective Etching).
of Poly-silicon technology
) structure. As will be described later, a bipolar transistor adopting this 5EPT structure has a base region, a base extraction electrode, an emitter region, an emitter extraction electrode, and a base extraction electrode.
Each of the interlayer insulating films between the emitter extraction electrodes is formed in a self-aligned manner.

A bipolar transistor employing a 5EPT structure has the feature that the area of each operating region can be reduced and the parasitic capacitance formed between each operating region can be reduced, so that the operating speed can be increased.

This logic LSI employs a four-layer wiring structure (multilayer wiring structure). A wiring pattern layout for at least the signal wiring in this four-layer wiring structure is formed by an automatic wiring placement system using a computer. The connections between each semiconductor element in the basic cell 12 of the logic LSI are mainly the first signal wiring (38
A) is connected (basic cell internal wiring). In the wiring area 14 between the basic cell rows 13, a first calendar signal wiring 38 is arranged as shown in FIG. As the number of gates increases, the size of the basic cell 12 increases and its occupied area becomes larger, so the size of the wiring region 14 (particularly the width dimension in the X direction) becomes smaller. Specifically, the size of the wiring region 14 is about one quarter or less of the size of the basic cell 12.

The first calendar signal distribution vA38 has a predetermined wiring pitch of
A plurality of them are arranged in the X direction and are configured to extend in the X direction. The first calendar signal wiring 38 mainly connects logic circuits formed by performing intra-basic cell wiring in the basic cell 12.

The first calendar signal wiring 38 is.

For example, the wiring width dimension is 3.0 [μm], and the wiring interval (space between wiring) is 2.0 μm. The film is composed of O [uml] and a film thickness of 1.0 [μm]. Therefore, the wiring pitch P1 of the first calendar signal wiring 38 is configured to be 5.0 [μm]. The wiring pitch P1 here is the dimension between the center position of the first calendar signal wiring 38 in the wiring width direction and the center position of the adjacent first calendar signal wiring 83B in the wiring width direction. Hereinafter, the definition of wiring pitch is the same.

A plurality of second layer signal wirings 41 are arranged in the X direction at a predetermined wiring pitch on the two basic cells 12 and the wiring area 14 (between the basic cells 12), and are configured to extend in the X direction. . In other words, the second calendar signal wiring 41 is a logic LSI.
Substantially the entire area of the logic circuit section extends as a wiring region (wiring channel region). The second calendar signal wiring l1A41 mainly connects the logic circuits.

For example, the second layer signal wiring 41 has a wiring width dimension of 3.5[
μm], wiring spacing 1.5 [μm], film thickness 1.0
It consists of [μm]. This second calendar signal distribution has a wiring pitch P2 of 1%41 of 5.0 [μm].

A plurality of 3M-th signal wirings 44 are arranged in the Y direction at a predetermined wiring pitch on the basic cells 12 and the wiring area 14 (between the basic cells 12), and are configured to extend in the X direction. The third layer signal wiring 44 is the second layer signal wiring 4.
1, substantially the entire area of the logic circuit portion of the logic LSI is extended as a wiring region. The third layer signal wiring 44 mainly connects the logic circuits. Third layer confidence number, 1!44
For example, the wiring width dimension is 3.5 rμm] and the wiring spacing is 1.
．． The film thickness is 5 rμm and the film thickness is 1°0 [μm]. The wiring pitch P3 of this third layer signal wiring 44 is 5.0 [μm
] Consists of.

Although not shown in FIG. 2, the fourth layer wiring (46) is arranged above the third layer signal wiring 44.

The fourth layer wiring is mainly used as power wiring and signal wiring. The fourth layer wiring has a film thickness of, for example, 2.0 [μm].

As described above, in the logic LSI of this embodiment, the first layer signal wiring 38 and the third layer signal wiring m44 of the four-layer wiring structure are extended in the -X direction, and the second layer signal wiring m44 is extended in the -X direction. Wire 41 to Y
extend in the direction. The first layer signal wiring 38, the second layer signal wiring 41, and the third layer signal wiring 44 are each configured with the same wiring pitch.

Next, the specific structure of the logic LSI will be briefly explained using FIG. 1 (a sectional view of the main part).

As shown in FIG. 1, the logic LSI is composed of an f-type semiconductor substrate 21 made of single crystal silicon. The left side of FIG. 1 shows the basic cell 12 part, and the 5EPs that make up the basic cell
The right side of FIG. 1, which shows the bipolar transistor Tr- employing the T structure, shows the wiring region 14 and each wiring layer of the multilayer wiring structure.

As shown in FIG. 1, the bipolar transistor Tr adopting the 5EPT structure is isolated from other regions by an element isolation region. The element isolation region is formed of a semiconductor substrate 21, an insulating film 26 for element isolation, and a p° type semiconductor region 24. The insulating film 26 for element isolation is the n-type epitaxial layer 2
It is composed of a silicon oxide film formed by selectively oxidizing the main surface of 2. The bottom surface of the inter-element isolation insulating film 26 is connected to the semiconductor substrate 2.
It is configured to reach the main surface of 1. The p° type semiconductor region 24 is provided on the bottom surface of the element isolation insulating film 26 on the main surface of the semiconductor substrate 21 . This p° type semiconductor region 2
4 is configured as a channel stopper region.

Bipolar transistor T that adopts this 5EPT structure
r has a vertical npn structure consisting of an n-type collector region, a p-type base region, and an n-type emitter region.

The n-type collector region is composed of a buried Go-type semiconductor region 23, a Go-type semiconductor region 25 for raising the collector potential, and an epitaxial layer 22. In the n-type collector region, the first-layer signal wiring (basic cell internal wiring) 38A is connected to the n°-type semiconductor region 25 for raising the collector potential. The connection between the Go-type semiconductor region 25 for raising the collector potential and the first layer signal wiring 38A is made through connection holes 37 formed in the interlayer insulating films 27, 32 and 36. The first layer signal wiring 38A is formed of, for example, an aluminum film or an aluminum alloy film deposited by a sputtering method or a vapor deposition method. Cu or Cu and Si are added to the aluminum alloy film.

Cu mainly acts to reduce migration. Si acts to reduce alloy spikes.

The p-type base region includes a p-type semiconductor region 30 which is a graft base region and a p-type semiconductor region 3 which is an intrinsic base region.
Consists of 1. p-type semiconductor region 31, p.

Each of the type semiconductor regions 30 is epitaxial! 22 main surfaces.

One end portion of the base extraction electrode 29 is connected to the p° type semiconductor region 30 which is a graft base region of the p type base region through the base opening 28 . Base extraction electrode 2
Reference numeral 9 is formed of a first layer polycrystalline silicon film in a manufacturing process into which, for example, a p-type impurity (CB) is introduced. The base extraction electrode 29 is formed with a thickness of, for example, 500 to 700 [nm]. The position of one end side of the base extraction electrode 29 (the side that defines the emitter opening 34A) is defined by the diffusion distance of the p-type impurity from the p-type semiconductor region 30, and is self-directed with respect to the p-type semiconductor region 30. Formed by alignment. Although the planar shape of the base extraction electrode 29 is not shown, it is configured such that one end defines the periphery of the emitter opening 34A. The other end of the base extraction electrode 29 is provided with an interlayer insulating film 3.
The first layer signal wiring (basic cell internal wiring) 38A is connected through the connection hole 37 formed in 2 and 36.

The n-type emitter region is composed of the Go-type semiconductor region 35A. The n° type semiconductor region 35A is formed on the main surface of the p type semiconductor region 31, which is an intrinsic base region. An emitter extraction electrode 35 is connected to the Go-type semiconductor region 35A through the emitter opening 34A. The emitter extraction electrode 35 is formed of a second layer polycrystalline silicon film in the manufacturing process into which n-type impurities (As) are introduced, for example. The emitter extraction electrode 35 is formed with a film thickness of, for example, 200 to 300 [nml]. The emitter opening 34A is formed within the opening 33 formed in the interlayer insulating film 32 in a region defined by the interlayer insulating film 34 formed on the surface of the base extraction electrode 29 on one end side. The interlayer insulating film 34 is formed of, for example, a silicon oxide film obtained by oxidizing the surface of the base extraction electrode 29, and is formed in self-alignment with the base extraction electrode 29.

In other words, the emitter extraction electrode 35 is formed in a self-aligned manner with respect to the base extraction electrode 29, and furthermore, the emitter extraction electrode 35 is self-aligned and insulated from the base extraction electrode 29 through the interlayer insulating film 34. . The n° type semiconductor region 35A, which is the n type emitter region, is formed by drive-in diffusion of the n type impurity introduced into the emitter extraction electrode 35. A first layer signal wiring (basic cell internal wiring) 38A is connected to the emitter extraction electrode 35 through a connection hole 37 formed in an interlayer insulating film 36.

The bipolar transistor Tr employing the above-mentioned 5EPT structure is formed by substantially the same method as described in detail in, for example, Japanese Patent Application No. 175600/1983, although the method for forming it will not be described.

As shown in FIG. 1, the first layer signal wiring 38 is arranged on the surface of the interlayer insulating film 36 in the wiring region 14. As shown in FIG. The first layer signal wiring 38 is extended in the X direction at a wiring pitch P1, as shown in FIGS. 1 and 3 (plan views of main parts). The first layer signal wiring gaa is formed of the same conductive layer (same manufacturing process) as the first layer signal wiring (basic cell internal wiring) 38A.

As shown in FIGS. 1 and 3, a second layer signal wire 41 is arranged above the first layer signal wire 38 with an interlayer insulating film 39 interposed therebetween. The second layer signal wiring 41 is extended in the Y direction at the wiring pitch P2 as described above. The second layer signal wiring 41 is formed of the same conductive film as the first layer signal wiring 38.

The interlayer insulating film 39 is formed of a silicon oxide film deposited by, for example, a CVD method and then sputter etched with an inert gas so that its surface is planarized. For example, this silicon oxide film is formed by depositing the film to a thickness of about 4 [μm] and then sputter etching the surface to a thickness of about 2.5 [μm]. This interlayer insulating film 39 is formed with a film thickness of about 1.0 to 1.5 [μm] on the flat part on the first layer signal wiring 38, and is formed from the surface on the four parts between the first layer signal wiring 38. The level difference (indentation amount) is formed to be 0°2 to 0.3 [μm] or less. In other words, the step portion of the interlayer insulating film 39 is flattened to about 20% or less.

Further, the interlayer insulating film 39 is flattened so that the angle of the slope between the flat portion and the recessed portion (the slope angle of the stepped portion) is approximately 30 degrees or less.

Further, the interlayer insulating film 39 may be formed of a quartz film deposited by a bias sputtering method (a deposition method in which film deposition and etching of the surface of the deposited film are performed simultaneously). Further, the interlayer insulating film 39 is coated on the surface of the silicon oxide film or silicon nitride film deposited by plasma CVD method (SOG: 5 pin
It is also possible to form a composite film (three-layer structure) in which a silicon oxide film is applied by the on glass method, and a silicon oxide film deposited by the plasma CVD method is laminated on the surface of the silicon oxide film. 0.5[μm1. Approximately 0.2 [μm],
Each film is formed with a thickness of about 1.0 uml.

The second layer signal wiring 41 passes through the connection hole 40 formed in the interlayer insulating film 39 to the first layer signal wiring i! 38. As shown in FIG. 3, the connection hole 40 is formed at the intersection of the first layer signal wiring 38 and the second layer signal wiring 41 (at the lattice points of the x-y lattice wiring channel area of the automatic wiring placement system). corresponding position). The connection hole 40 is
Although not limited to this, it is formed by anisotropic etching such as RIE, and the fine opening size is, for example, 2.0 μm 1×2.
A plane of 0 μml is formed in a rectangular shape. The surface of the first layer signal wiring 38 exposed from inside the connection hole 40 is subjected to sputter etching treatment in an inert gas atmosphere before the second layer signal wiring 41 is formed. This sputter etching process is performed for the purpose of removing an insulating material (for example, alumina oxide) formed on the surface of the first layer signal wiring 1138 during the process. During this sputter etching process, in order to prevent the insulating material from re-adhering to the surface of the first layer signal wiring 38 by hitting the side wall of the interlayer insulating film 39 in the connection hole 40 with charged particles, the connection hole 40 is The side wall of the second layer signal wire 41 is preferably formed steeply, for example, substantially perpendicularly, to the surface of the first layer signal wire 38 based on the steep stepped shape of the side wall of the connection hole 40. If the coverage is reduced, it is preferable to fill the inside of the contact hole 40 with a conductive material. For example, the conductive material used to fill the inside of the contact hole 40 may be deposited by a CVD method and its surface removed by etching. Tungsten (W) left only in the connection hole 40 is used. Furthermore, tungsten selectively deposited by a selective CVD method may be embedded in the connection hole 40.

A third layer signal wiring 44 is arranged above the second layer signal wiring 41 with an interlayer insulating film 42 interposed therebetween. The third layer signal wiring 44 extends in the X direction at the wiring pitch P3, as described above. In this third layer, the wiring pitch P3 of the self-signal wiring 44
are formed at substantially the same wiring pitch as the wiring pitch P1 of the first layer signal wiring 38.

As shown in FIG. 1, the center position of the third layer signal wiring 44 in the wiring width direction is 2 times larger than the wiring pitch P1 or P3 in the Y direction compared to the center position of the first layer signal wiring fi 38 in the wiring width direction.
It is shifted by an amount corresponding to the dimension of 1/1. X virtually set in the two-dimensional memory space of the automatic wiring placement system
- In which layer of the signal line are the first layer signal wiring (AL T ) and the third layer signal wiring (AL m) extending in the same X direction in the Y lattice wiring channel region? It is shifted because it is necessary to identify the The third layer signal wiring 44 is formed of the same conductive film as the first layer signal wiring 38.

The interlayer insulating film 42 is formed of the same insulating film as the interlayer insulating film 39.

The third ffth signal wiring 44 is connected to the second layer signal wiring 41 through a connection hole 43 formed in the interlayer insulating film 42 . As shown in FIG. 1, the connection hole 43 is located at the intersection of the second layer signal wiring 41 and the third layer signal wiring 44 (similarly at the intersection of the X-Y lattice wiring channel area of the automatic wiring placement system). This connecting hole 4 is formed at a position corresponding to the point.
3 is because the third layer signal wiring 44 is shifted from the first layer signal wiring 38.

It is shifted from the connection hole 40 by a dimension corresponding to this amount of shift. In other words, the connection hole 43 has a wiring pitch of P1 or P
It is shifted in the Y direction with respect to the connection hole 40 by an amount corresponding to a half dimension of 3. Like the connection hole 40, the connection hole 43 has a diameter of, for example, 2.0 [μm]×2.0 [μm]. It is formed with an opening size of O [μm].

A fourth layer wiring 46 is arranged above the third ff signal wiring 44 with a living room insulating film 45 interposed therebetween. Although not shown in FIG. 1, the fourth layer target IjlA 46
It is connected to the third layer signal wiring 44 etc. through the connection hole formed in 5. The fourth layer wiring 46 is formed of the same conductive film as the first layer signal wiring 38. Further, the first interlayer insulating film 45 is formed of the same insulating film as the interlayer insulating film 39.

A final passivation film 47 is formed on the fourth layer wiring 46 . The final passivation film 47 is formed of, for example, a silicon nitride film deposited by plasma CVD or sputtering.

The multilayer wiring structure configured in this manner is mainly composed of open insulation, which is the base film of each of the first layer signal wiring 38, second layer signal wiring 41, and third layer signal wiring 44 among the signal wiring. membrane 3
It is assumed that each surface of 6.39.42 is subjected to the planarization process as described above. In other words, the three-layer wiring structure or more multi-layer wiring structure is based on the planarization process of the base film, the first layer signal wiring 838 and the second layer signal wiring 4.
1. It becomes possible to arrange each of the third layer signal wiring lines [44] at a dense wiring pitch. In addition, in the multilayer wiring structure, the wiring pitch P2 of the second layer signal wiring 41 in the upper layer and the wiring pitch P3 of the third layer signal wiring 44 are smaller than the wiring pitch P1 of the first layer signal wiring 38 in the lower layer. It becomes possible to configure each of them to be substantially the same (or smaller).

The aforementioned first layer signal wiring 38 (including the basic cell internal wiring 38A), second layer signal wiring 41, and third layer signal wiring 44
, connection hole 40. Each of the connection holes 43 is formed based on an automatic wiring placement system using a computer. A method for forming a logic LSI employing this gate array method will be briefly explained using FIG. 4 (logic LSI development flow diagram).

First, as shown in FIG. 4, the logic functions to be installed in the logic LSI are determined <51>, that is, the logic circuits to be installed in the logic LSI are designed, and then the logic circuit is subjected to logic simulation and the logic Verify the functionality and finally decide on the logical functions to be installed.

Next, wiring information (connection information) and connection hole information are placed on the X-Y lattice wiring channel area based on the determined logical function using an automatic wiring placement system (DA) that uses a computer for two-dimensional processing. Place automatically <52>
In addition, here, the arrangement of the signal wiring information (corresponding to the first to third layer signal wirings 38, 41, 44) and the connection hole information (corresponding to the connection holes 40 and 43) connecting the signal wirings will be explained. 1. Basic cell internal wiring (logic circuit or first
The arrangement of layer signal wiring 38A) will be omitted. The X-Y lattice wiring channel region includes a plurality of wiring channel regions 1, 2, . . . , 10 and a plurality of wiring channel regions 1, 2.3 extending in the Y direction and arranged at a wiring pitch of a predetermined interval. The wiring channel region extending in the X direction corresponds to a wiring pitch that is half the wiring pitch P1 of the first layer signal wiring 38 or the wiring pitch P3 of the third layer signal wiring 44 described above. The wiring channel region extending in the Y direction corresponds to the wiring pitch P2 of the second mesh signal wiring 41. This X-Y lattice wiring channel region is virtually set in a memory space of an automatic wiring placement system in which memory cells are arranged two-dimensionally.

Next, the wiring information and connection hole information placed in the xy grid wiring channel area of the automatic wiring placement system are three-dimensionally divided <53>. In other words, among the X-Y lattice wiring channel regions, the wiring information placed at the odd number n (n=1.3, 5, etc.) of the wiring channel regions extending in the X direction is the first layer. The eye signal wiring AI is used. The wiring information placed at the even-numbered (n+1)th wiring channel region extending in the X direction is the third layer signal wiring Am. The wiring information arranged in the wiring channel region extending in the Y direction is the second layer signal wiring An. In addition, connection hole information placed at the odd-numbered nth wiring channel region extending in the X direction of the X-Y lattice wiring channel region and at the lattice points of the wiring channel region extending in the Y direction is the first layer signal. A connection hole THI connects the wiring AI and the second signal wiring mA■. Even number n+1 of the wiring channel region extending in the X direction
The connection hole information arranged at the lattice points between the wiring channel region and the wiring channel region extending in the Y direction is the connection hole THII that connects the second layer signal wiring AI and the third layer signal wiring Am. In other words, on the program of the automatic wiring placement system,
First layer signal wiring A1. 2nd layer signal arrangement iAA■1,
3rd door signal, 1AII [, connection hole THI, connection hole T
Each of the HIIs is identified.

Next, a violation of the layout rules of the wiring layout formed in the automatic wiring process <52> is checked <54>
〉. The violation check mainly checks whether the signal wiring can be formed according to the wiring layout without any problem in the semiconductor wafer manufacturing process.

If this violation check indicates a defect, part of the wiring layout will be corrected. If the product passes the violation check <54> as a good product, a mask pattern is generated based on the wiring information and connection hole information of the automatic wiring placement system described above <55>. The processing steps from automatic wiring processing <52> after determining the logic function <51> to mask pattern generation <55> are processing steps using an automatic wiring placement system (D
A process).

Next, a mask for semiconductor manufacturing is manufactured <56>.

This mask is manufactured using, for example, an electron beam drawing device based on the wiring information and connection hole information automatically placed by the automatic wiring placement system.

A mask for semiconductor manufacturing is composed of, for example, a quartz glass substrate on which a pattern is drawn with a shielding film of Cr, Cr0, or the like. The semiconductor manufacturing mask for the first layer signal wiring 38 is the first
It is formed based on the information of the layer signal wiring AI. Similarly,
Based on the respective information of the second layer signal wiring AII, the third Nth signal wiring Anl, the connection hole THI, and the connection hole THU,
Layer signal wiring 41, third layer signal wiring 44, connection hole 40
, a semiconductor manufacturing mask for each of the connection holes 43 is formed.

Next, using the semiconductor manufacturing mask described above, a semiconductor wafer manufacturing process is performed (wafer manufacturing) <57>. That is, first, as shown in FIGS. 1 and 3, the first layer signal wiring 38 is formed on the semiconductor wafer (unconnected) of the logic LSI on which the basic cells 12 are arranged. next,
An interlayer insulating film 39, a connection hole 40, and a second layer signal wiring 41 are formed in sequence. Next, the interlayer insulating film 42, the connection hole 4
3. Form each of the third layer signal wirings 44 one after another. Then, an interlayer insulating film 45. By sequentially forming the fourth layer wiring 46 and the final passivation film 47, a logic LSI having a predetermined logic function is completed. The first layer signal wiring 38, the connection hole 40, the second layer signal wiring 41. The connection hole 43, third layer signal wiring 44, etc. are formed using photolithography technology. The photolithography technique involves forming an etching mask from a photoresist film (photosensitive resin film) using a semiconductor manufacturing mask, and etching each layer using this etching mask.

In this way, in a logic LSI that adopts the gate array method, lines are placed between the basic cells 12 on the semiconductor substrate 21 based on the wiring information placed in the X direction of the X-Y lattice wiring channel region of the automatic wiring placement system. 1st layer signal wiring 38
At the same time, a third layer signal wiring 144 is placed between the basic cells 12 and on the basic cells 12, and based on the wiring information placed in the X direction of the X-Y lattice wiring channel region, the basic cell 12 and on the basic cell 12, and the wiring pitch P3 of the third Nth signal wiring 44 is set to the wiring pitch P1 of the first layer signal wiring 38.
It is configured with substantially the same wiring pitch. With this configuration, by using the space between the basic cells 12 and on the basic cells 12,
The number of signal wirings extending in the X direction can be increased by the third layer signal wiring 44, and the number of second layer signal wirings 41 extending in the X direction can also be increased, so automatic wiring placement is possible. Improves the flexibility of signal wiring placement in the system,
The mounting rate of logic circuits can be improved, and the number of the third layer signal wirings 44 arranged can be increased, so that the first layer signal wiring 38, the third layer signal wiring 44, and the second layer signal wiring Since the number of wires arranged with 41 can be made uniform, the degree of freedom in the arrangement of signal wires in the automatic wire placement system can be further improved, and the implementation rate of logic circuits can be further improved. In particular, in the logic LSI currently being developed by the present inventor, as shown in FIG. 2, the area occupied by the basic cell 12 is large, whereas the area occupied by the wiring area 14 is small. The number of 38 wires is reduced. Therefore, application of the present invention to this logic LSI is particularly effective.

In addition, in a logic LSI that adopts the gate array method, based on the wiring information arranged in the X direction of the X-Y lattice wiring channel region of the automatic wiring placement system, the first layer is In addition to arranging the second signal wiring 38, a third signal wiring 38 is placed between the basic cells 12 and on the basic cell 12.
The layer signal wiring 44 is arranged, and the second Nth signal wiring 41 is placed between the basic cells 12 and on the basic cell 12 based on the wiring information arranged in the X direction of the X-Y lattice wiring channel region.
and the wiring pitch P2 of the second layer signal wiring 41
is configured to have substantially the same wiring pitch as the wiring pitch P1 of the first layer signal wiring 38. With this configuration, the number of signal wirings extending in the X direction is increased by the third layer signal wiring 44 by utilizing the space between the basic cells 12 and on the basic cells 12, and the number of signal wirings extending in the X direction is increased by the third layer signal wiring 44. Since the number of layer signal wirings 41 to be arranged can be increased, the degree of freedom in the arrangement of signal wirings in an automatic wiring placement system can be improved, the implementation rate of logic circuits can be improved, and the number of layer signal wirings 41 can be increased. The number of the first layer signal wiring 38, the third layer signal wiring 44, and the second layer signal wiring [4] was increased.
Since the number of wires arranged can be made uniform, the degree of freedom in the arrangement of signal wires in the automatic wire placement system can be further improved, and the implementation rate of logic circuits can be further improved. Further, when the respective wiring pitches P1 and P2 of the first layer signal wiring 38 and the second layer signal wiring 41 are substantially the same, as shown in FIG. At any grid point in the area, the first layer signal wiring 38 and the 27th layer signal wiring
Since the connection with the first signal wiring 41 can be made, the degree of freedom in arranging the signal wiring in the automatic wiring placement system can be further improved, and the implementation rate of logic circuits can be improved. This effect is.

The same applies when the wiring pitches P2 and P3 of the second layer signal wiring 41 and the third layer signal wiring 44 are substantially the same.

Further, by configuring the wiring pitch P3 of the third layer signal wiring 44 to be smaller than the wiring pitch P1 of the first layer signal wiring 38, the number of wirings of the third layer signal wiring 44 can be further increased. Therefore, the implementation rate of logic circuits can be further improved.

However, as will be described later, the wiring pitch P3 of the third layer signal wiring 44 is practically half the wiring pitch P1 of the first layer signal wiring 38 (0.5 wiring pitch). It is preferable to do so.

The wiring pitch P3 of the third layer signal wiring 44 with respect to the wiring pitch P1 of the first layer signal wiring 38 is practically the fifth layer.
It is set within the range shown in FIGS. 9 to 9 (respective copy layout diagrams of the first and third layer signal wiring). In other words,
The wiring pitch P3 of the third layer signal wiring 44 shown in FIG. 5 is the same as the wiring pitch Pi of the first layer signal wiring 38.

Further, the center position of the third layer signal wiring 44 in the wiring width direction is made to substantially coincide with the center position of the first layer signal wiring 38 in the wiring width direction (exists on the same central axis).

The cross-sectional structure of the logic LSI set with the wiring pitch shown in FIG. 5 is shown in FIG. 10 (a cross-sectional view of the main part).

The wiring pitch P3 of the third layer signal wiring 44 shown in FIG. 6 is as described in the above embodiment, and is the same wiring pitch as the wiring pitch P1 of the first layer signal wiring 38. The center position of the third layer signal wiring 44 in the wiring width direction is 2 times larger than the center position of the first layer signal wiring 38 in the wiring width direction.
It is shifted by a dimension corresponding to 1/1th the wiring pitch. 7th
The ratio of the wiring pitch P3 of the third layer signal wiring 44 shown in FIG. i to the wiring pitch P1 of the first layer signal wiring 38 is 1.
Consists of 5. The center position of the third layer signal wiring 44 in the wiring width direction is made to coincide with the center position of every other first layer signal wiring 38 in the wiring width direction. 3 shown in Figure 8.
The ratio of the wiring pitch P3 of the layer signal wiring 44 to the wiring pitch P1 of the first layer signal wiring 38 is 2.0. And the 37th! The center position of the g-th signal wiring 44 in the wiring width direction is made to coincide with the center position of the first layer signal wiring 38 in the wiring width direction. The wiring pitch P3 of the third layer signal wiring 44 shown in FIG. 9 is the wiring pitch P1 of the first layer signal wiring 38.
The ratio is 2.0. The center position of the third layer signal wiring 44 in the wiring width direction is shifted from the center position of the first layer signal wiring 38 in the wiring width direction by an amount corresponding to one-half the wiring pitch dimension. .

In this way, in the method for forming a logic LSI that adopts the gate array method, the first layer signal wiring 3 of the multilayer wiring structure is
8 and the third layer signal wiring 44 in the X direction, and the second layer signal wiring 41 in the Y direction, and the wiring pitch of the third layer signal wiring 44 with respect to the first layer signal wiring 38. P3
Form a ratio of 0.5.1.0, 1°5 or 2.0. With this configuration, when connecting each of the first layer signal wiring 38 and the third layer signal wiring 44 to the second layer signal wiring 41, the signal wiring can be efficiently connected while securing a manufacturing process margin. , it is possible to reduce unnecessary signal wiring and improve the implementation rate of logic circuits.

Further, by configuring the wiring pitch P2 of the second layer signal wiring 41 to be smaller than the wiring pitch P1 of the first layer signal wiring 38, the number of wirings of the second layer signal wiring 41 can be further increased. Therefore, the implementation rate of logic circuits can be further improved.

For example, the wiring pitch P2 of the second layer signal wiring 41 is 4.
The thickness is approximately 5 to 4.8 [μm]. 2nd layer signal layout J
l! The wiring pitch P2 of 41 is the wiring pitch P1 of the first layer signal wiring 38 and the wiring pitch P of the third layer signal wiring 44.
Since the wiring pitch can be set independently for each of 3 and the wiring pitch P2 can be freely set, the wiring of the first layer signal wiring 38 can be adjusted as shown in the wiring pitch P3 of the third layer signal wiring 144. The wiring pitch P2 of the second layer signal wiring 41, which is not restricted by the pitch P1, is determined by the mask production <56> after the automatic wiring process <52> in the DA process shown in FIG.
> This can be set by adding retsusen processing (processing to make the pattern thinner) before the pattern and performing that processing. Conversely, the wiring pitch P2 of the second layer signal wiring 41 is set in advance to a small wiring pitch, and in the DA processing, the wiring pitch P1 of the first layer signal wiring 38 and the wiring pitch P2 of the third layer The wiring pitch P3 of the signal wiring 44 may be set larger by Broden processing (processing to thicken the pattern).

Furthermore, since the number of signal wirings extending in the X direction can be increased by the third layer signal wiring 44 as described above, the layout rules for the first layer signal wiring 38 are relaxed, and the number of signal wirings extending in the X direction can be increased. Manufacturing process margins are improved,
The manufacturing yield of logic LSIs can be improved.

In addition, in a logic LSI that adopts the gate array method, basic cell 1
A first layer signal wiring 38 is placed between the basic cells 12 and a third layer signal wiring 44 is placed between the basic cells 12 and on the basic cells 12, and is placed in the Y direction of the X-Y lattice wiring channel region. Based on the wiring information obtained, the second layer signal wiring 41 is arranged between the basic cells 12 and on the basic cell 12, and
Wiring pitch P2 of layer signal wiring 41, third layer signal wiring,
Each of the 144 wiring pitches P3 is configured to have substantially the same wiring pitch as the wiring pitch P1 of the first layer signal wiring 38. With this configuration, it is possible to achieve the effect of improving the above-mentioned mounting rate, and at the same time, the first
This is because the wiring information of the layer signal wiring 38, the second layer signal wiring 41, and the third layer signal wiring 44 is not subjected to Ressen processing or Broden processing.

The calculation processing time (DA processing time) in the automatic wiring placement system is shortened by the amount equivalent to these processing steps.

Product completion time can be shortened.

Note that the present invention may apply the logic LSI to four layers of signal wiring and one layer of power supply wiring (5-layer wiring structure), or to a multilayer wiring structure of more than 5 layers. In this case, the first layer signal wiring and the third layer signal wiring are made to extend in the X direction, and the second layer signal wiring and the fourth layer signal wiring are made to extend in the Y direction.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention can be applied to an electronic device having a mother chip structure in which a plurality of semiconductor integrated circuit bags @ (semiconductor chips) are mounted on a mounting surface of a wiring board having a multilayer wiring structure. The multilayer wiring structure of the wiring board of the electronic device has at least three or more layers of signal wiring, and as described above, the signal wiring is automatically arranged using an automatic wiring placement system.

The wiring board is, for example, a single crystal silicon substrate, a silicon carbide substrate,
It is formed from a ceramic substrate, mullite substrate, etc.

Further, the present invention is not limited to logic LSIs, but can be applied to memory LSIs and logic LSIs with memory, such as microcomputers.

In addition, one aspect of the present invention is to convert the basic cell of a logic LSI into a complementary MIS.
Mainly FET or bipolar transistor and complementary type M
It may also be configured in combination with an ISFET.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) In a semiconductor integrated circuit device that employs a gate array method, circuit mounting efficiency can be improved.

(2) In a method for forming a semiconductor integrated circuit device that employs a gate array method, the mounting efficiency of one circuit can be improved and the time required to complete the product can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the main parts of a logic LSI that employs a gate array method as an embodiment of the present invention, FIG. 2 is a chip layout diagram of the logic LSI, and FIG. 3 is a main part of the logic LSI. FIG. 4 is a flowchart for explaining the method for developing the logic LSI, FIGS. 5 to 9 are reproduction layout diagrams of the wiring of the logic LSI, and FIG. FIG. 7 is a sectional view of a main part of a logic LSI employing a gate array method, which is another embodiment. In the figure, 12...basic cell, 14...wiring area, 36
．． 39°42.45...Interlayer insulating film, 38...First
Layer signal wiring, 41...Second layer signal wiring, 44...
・3rd layer signal wiring, 46... 4th Mth wiring, 40.4
3... Connection hole, P... wiring pitch.

Claims (1)

[Claims] 1. X set in the memory space of the automatic wiring placement system
- Automatically arrange multiple layers of wiring information in the Y lattice wiring channel area, and based on this wiring information, connect multiple layers of wiring between circuits consisting of basic cells arranged in rows and columns on the board. In a semiconductor integrated circuit device that employs a gate array method that connects
- Y lattice wiring Based on the wiring information arranged in the x direction of the channel region, arrange the first layer wiring between the basic cells, and arrange the third layer wiring between the basic cells and on the basic cells, Based on the wiring information arranged in the Y direction of the X-Y lattice wiring channel region, the second layer wiring is arranged between basic cells and on the basic cell, and the wiring pitch of the third layer wiring is set according to the wiring pitch of the third layer wiring. A semiconductor integrated circuit device characterized in that the wiring pitch is substantially the same as or smaller than the wiring pitch of the first layer wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein each of the first layer wiring, the second layer wiring, and the third layer wiring is used as a signal wiring. 3. An underlying insulating film for the first layer wiring, an interlayer insulating film between the first layer wiring and the second layer wiring, and an interlayer between the second layer wiring and the third layer wiring. 3. The semiconductor integrated circuit device according to claim 1, wherein each surface of the insulating film is subjected to planarization treatment. 4. Each of the base insulating film and the interlayer insulating film is flattened to have a surface level difference of 20% or less with respect to the film thickness of the flat portion thereof. Each of the semiconductor integrated circuit devices described above. 5. Each of the semiconductor integrated circuit devices according to claim 1, wherein the wiring layer is composed of three or more wiring layers. 6. Claims 1 to 6, characterized in that the ratio of the wiring pitch of the third layer wiring to the first layer wiring is 0.5, 1.0, 1.5, or 2.0. 5. Each semiconductor integrated circuit device according to 5. 7. X set in the memory space of the automatic wiring placement system
- Automatically arrange multiple layers of wiring information in the Y lattice wiring channel area, and based on this wiring information, connect multiple layers of wiring between circuits consisting of basic cells arranged in rows and columns on the board. In a semiconductor integrated circuit device that employs a gate array method that connects
- Y lattice wiring Based on the wiring information arranged in the X direction of the channel region, arrange the first layer wiring between the basic cells, and arrange the third layer wiring between the basic cells and on the basic cells, Based on the wiring information arranged in the Y direction of the X-Y lattice wiring channel region, second layer wiring is arranged between basic cells and on the basic cells, and the wiring pitch of the second layer wiring is set according to the wiring pitch of the second layer wiring. A semiconductor integrated circuit device characterized in that the wiring pitch is substantially the same as or smaller than the wiring pitch of the first layer wiring. 8. X set in the memory space of the automatic wiring placement system
- Automatically arrange multiple layers of wiring information in the Y lattice wiring channel area, and based on this wiring information, connect multiple layers of wiring between circuits consisting of basic cells arranged in rows and columns on the board. In a semiconductor integrated circuit device that employs a gate array method that connects
- Y lattice wiring Based on the wiring information arranged in the X direction of the channel region, arrange the first layer wiring between the basic cells, and arrange the third layer wiring between the basic cells and on the basic cells, Based on the wiring information arranged in the Y direction of the X-Y lattice wiring channel region, the second layer wiring is arranged between the basic cells and on the basic cell, and the second layer wiring and the third layer wiring are arranged. A semiconductor integrated circuit device characterized in that each wiring pitch is configured to be substantially the same as the wiring pitch of the first layer wiring.