JPH08204002A - Manufacturing method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To shorten LSI manufacturing process having multilayer interconnection structure by, after a connecting hole is formed in the first insulating film by the etching with a photo-resist as a mask, forming a connecting hole in the second insulation film lower than a wiring layer by the etching with the photo-resist and the wiring as a mask. CONSTITUTION: By the etching with a photo-resist 14, which is formed on the first insulation film 12 covering a specified wiring layer, as a mask, connecting holes 15A and 15B are formed in the first insulation film 12. Then, by the etching with the photo-resist 14 and wirings 10A and 10B, in a wiring layer which is so assigned that a part of it overlaps the connecting holes 15A and 15B, as a mask, connecting holes 16A and 16B are formed in the second insulation film 9 lower than the wirings 10A and 10B. Thus, since the connecting holes 16A and 16B in the second insulation film 9 are formed in self-alignment to the wirings 10A and 10B, the connecting holes 15A and 15B in the first insulation film 12 and the connecting holes 16A and 16B in the second insulation film 9 are formed in a single process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to the production of a semiconductor integrated circuit device having multi-layer wiring.

[0002]

2. Description of the Related Art In recent years, with the high integration of LSIs, logic L
The SI uses multi-layered wiring of 6 to 7 layers or more, and the memory LSI also employs multi-layered wiring of 3 to 4 layers or more.

To form this kind of multilayer wiring, for example, after forming an element on a semiconductor substrate, deposition of an insulating film → formation of a connection hole by etching the insulation film → a connection hole made of W (tungsten) or the like. Embedding → Metal film deposition →
It is necessary to repeat the process of forming the metal wiring by etching the metal film for the number of wiring layers.

Further, with the miniaturization of the semiconductor element, the alignment margin between the connection hole and the wiring or the semiconductor element becomes smaller. Therefore, in some cases, a pad of polycrystalline silicon is formed at the bottom of the connection hole. By adding steps, short circuits due to mask misalignment are prevented.

A technique for burying a connection hole with W (tungsten) is disclosed in, for example, Japanese Patent Laid-Open No. 58-288.
It is described in Japanese Patent No. 56, etc.

[0006]

As mentioned above, the LS
In the manufacturing process of I, the process of depositing an insulating film → forming a contact hole → filling a contact hole → depositing a metal film → forming a metal interconnect is repeated every time the number of interconnect layers increases, so that the interconnect layer In the case of a large number of LSIs, the number of steps is considerable even if only wiring is formed, which is a major cause of lowering the manufacturing yield of LSIs having multilayer wiring. Further, when a pad of polycrystalline silicon is formed in order to secure a mask alignment margin for the connection hole, the number of steps is further increased. Moreover, when the width of the wiring and the diameter of the connection hole become smaller due to the progress of miniaturization, the contact area between the upper and lower wirings inside the connection hole becomes small, and there is concern that the contact resistance may increase.

As described above, in the process of manufacturing an LSI, the restriction of circuit design due to a decrease in manufacturing yield and an increase in contact resistance becomes a serious problem as the number of wiring layers increases, and a high-performance LSI can be provided at a low cost. It will be difficult.

An object of the present invention is to provide an L having a multilayer wiring structure.
It is to provide a technique capable of improving the manufacturing yield of SI.

Another object of the present invention is to provide a technique capable of reducing the contact resistance of the wiring inside the connection hole and promoting miniaturization of the LSI.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a contact hole is formed in the first insulating film by etching using a photoresist formed on the first insulating film covering a predetermined wiring layer as a mask. After forming, with the photoresist,
The connection hole is formed in the second insulating film below the wiring layer by etching using the wiring of the wiring layer arranged so as to partially overlap the connection hole as a mask.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the horizontal distance between one end of the opening of the photoresist and one end of the wiring is set to a dimension equal to or smaller than the resolution of exposure light. is there.

[0014]

According to the above-mentioned means (1), the contact hole is formed in the first insulating film by etching using the photoresist as a mask, and then the photoresist and the contact hole are arranged so as to partially overlap with the contact hole. By forming a connection hole in the second insulating film below the wiring by etching using the formed wiring as a mask, the connection hole of the second insulating film can be formed in self-alignment with the wiring. Therefore, the connection hole of the first insulating film and the connection hole of the second insulating film can be formed in one step.

According to the above-mentioned means (1), since the conductive film inside the connection hole and the wiring contact not only on the upper surface but also on the side surface of the wiring, even if the diameter of the connection hole is small,
It is possible to secure a sufficient contact area and reduce the contact resistance.

According to the above means (2), the horizontal distance between the one end of the opening portion of the photoresist and the one end of the wiring is set to a dimension equal to or smaller than the resolution of the exposure light, whereby the second insulating film is formed. The diameter of the formed connection hole can be made equal to or smaller than the minimum processing size of the device.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

Example 1 Al which is Example 1 of the present invention
A method of manufacturing a MOS / LSI having two layers of (aluminum) wiring will be described with reference to FIGS.

First, as shown in FIG. 1, p
On the main surface of the semiconductor substrate 1 made of-type single crystal silicon
Type well 2 is formed, then a field insulating film 3 for element isolation is formed on the main surface of the well 2, and then an n-channel type MOSF is formed on the main surface of the well 2 in the active region.
Form ETQn.

The MOSFET Qn has a gate insulating film 4 of silicon oxide formed on the main surface of the well 2, a gate electrode 5 of polycrystalline silicon formed on the gate insulating film 4, and both sides of the gate electrode 5. The n-type semiconductor regions 6A and 6B (source region, drain region) formed on the main surface of the well 2 are formed, and a part of the gate electrode 5 is also disposed on the field insulating film 3. Further, a sidewall spacer 7 of silicon oxide is formed on the sidewall of the gate electrode 5, and a cap insulating film 8 of silicon oxide is formed on the upper portion of the gate electrode 5.

Next, as shown in FIG.
BPSG (Boro Phospho Silicat
After depositing an insulating film 9 made of e-glass), a first metal film 10 is deposited by a sputtering method. This metal film 1
0 is composed of, for example, a three-layer film of a TiN film, an Al film, and a TiN film.

Next, as shown in FIG. 3, the metal film 10 is etched using the photoresist 11 as a mask, so that the wirings 10A, 10B,
10C and 10D are formed.

At this time, the end portion of the wiring 10A near the connection hole forming area (a) shown by the broken line in the drawing is arranged so as to overlap the connection hole forming area (a). Due to the circuit design, if there is no wiring near the prescribed connection hole formation area,
A dummy wiring is formed in the vicinity of the connection hole forming area, and an end portion of the dummy wiring is arranged so as to overlap the connection hole forming area. For example, the wiring 10B is a dummy wiring of this type, and its end portion is arranged so as to overlap the connection hole forming region (b) in the drawing. The dummy wiring may be in a floating state or may be formed by branching a part of the actual wiring.

Next, after removing the photoresist 11,
As shown in FIG. 4, wirings 10A, 10B, 10C, 10
Silicon oxide film and spin-on-glass (Sp
An interlayer insulating film 12 made of an in on glass) film is deposited.

Next, as shown in FIG. 5, a photoresist 14 having openings 13A and 13B above the connection hole forming regions (a) and (b) is deposited on the interlayer insulating film 12, By etching the interlayer insulating film 12 using the photoresist 14 as a mask, a connection hole 15 is formed in the interlayer insulating film 12.
A and 15B are formed. At this time, the end of the wiring 10A is exposed at the bottom of the connection hole 15A, and the end of the wiring 10B is exposed at the bottom of the connection hole 15B.

Subsequently, as shown in FIG. 6, with the photoresist 14 and the wirings 10A and 10B as a mask, the remaining portion of the interlayer insulating film 12, the insulating film 9 below the interlayer insulating film 12,
Further, by continuously etching the underlying gate insulating film 4, the semiconductor region 6A of the MOSFET Qn,
The connection holes 16A and 16B reaching 6B are formed.

That is, the connection hole 16 in the lower layer of the wiring 10A
A is formed in self-alignment with the wiring 10A,
The connection hole 16B in the lower layer of the wiring 10B is formed in self-alignment with the wiring 10B. Therefore, by defining the relative layout of the end portion of the opening 13A of the photoresist 14 and the end portion of the wiring 10A, the connection hole 16A in the lower layer of the wiring 10A can be formed in a desired size and shape. Similarly, by defining the relative layout of the end of the opening 13B of the photoresist 14 and the end of the wiring 10B, the connection hole 16B in the lower layer of the wiring 10B can be formed in a desired size and shape. .

Next, after removing the photoresist 14,
Connection holes 15A, 16A, 15B having a large aspect ratio,
In order to securely embed the wiring material inside the 16B, as shown in FIG. 7, first, as shown in FIG.
The iN / Ti film 17 is provided with connection holes 15A, 16A, 15B, 1
After being deposited on the entire surface of the semiconductor substrate 1 including the inside of 6B, as shown in FIG. 8, connection holes 15A, 16A, 15B, 16 are formed.
A W (tungsten) film 18 is embedded inside B. The W film 18 is embedded by, for example, the connection holes 15A, 16A, 15
A W film 18 is deposited on the entire surface of the semiconductor substrate 1 including the insides of B and 16B by a CVD method, and this is etched back to form a contact hole 1
Leave inside 5A, 16A, 15B, 16B.

Next, as shown in FIG. 9, the interlayer insulating film 12 is formed.
By patterning a two-layer film of, for example, an Al film and a TiN film deposited on the upper surface by sputtering, the second-layer wirings 19A, 1
9B and 19C are formed. The wiring 19A has a connection hole 15
First layer wiring 10A and MOS through A and 16A
The wiring 19B is connected to the semiconductor region 6A of the FET Qn, and the wiring 19B is connected to the MOSFET through the connection holes 15B and 16B.
It is connected to the semiconductor region 6B of Qn. In addition, MOSFE
When it is desired to connect the semiconductor region 6A of TQn only to the wiring 10A of the first layer, the wiring 19A of the second layer may be formed by a dummy wiring.

According to the manufacturing method of the present embodiment described above, the connection holes (15A, 15B) and the connection holes (16A, 16B) can be formed in one step, which was conventionally performed in two steps. The manufacturing yield can be improved by shortening the manufacturing process of the MOS / LSI having the Al2 layer wiring.

Further, according to the manufacturing method of this embodiment, the conductive film (TiN / Ti film 1) inside the connection holes 15A and 16A is formed.
7) and the wiring 10A of the first layer are in contact not only on the upper surface but also on the side surface of the wiring 10A, so that even if the diameters of the connection holes 15A and 16A are small, a sufficient contact area is secured and the contact resistance is reduced. can do. This also gives
The degree of freedom in circuit design is also improved.

Further, according to the manufacturing method of this embodiment, the horizontal distance from the end of the opening 13A (13B) of the photoresist 14 to the end of the first-layer wiring 10A (10B) is exposed. By setting the size to be equal to or smaller than the resolution of light, the diameter of the connection hole 16A (16B) in the lower layer of the wiring 10A (10B) can be set to be equal to or smaller than the minimum processing size of the device.
That is, according to the manufacturing method of the present embodiment, without using an expensive photomask such as a phase shift mask or using a low throughput device such as an electron beam direct writing device, the design rule Fine diameter connection hole 16A
Since (16B) can be formed, MOS / LS
The miniaturization and high integration of I can be promoted.

Example 2 Al which is Example 2 of the present invention
A method of manufacturing a MOS / LSI having a three-layer wiring is shown in FIGS.
This will be described with reference to FIG.

After forming the MOSFET Qn on the main surface of the well 2, the wirings 10A, 10B, 10C, 1 of the first layer are formed.
The steps until the interlayer insulating film 12 is deposited on the upper layer of 0D (see FIGS. 1 to 4) are the same as those in the first embodiment.

Next, as shown in FIG. 10, the interlayer insulating film 1
Second-layer wirings 20A, 20B, 20C are formed on the upper layer of No. 2, and then the second-layer interlayer insulating film 21 is deposited on the upper layer. The wirings 20A, 20B, 20C are made of, for example, TiN.
Film, an Al film, and a TiN film.
1 is composed of, for example, a silicon oxide film and a spin-on-glass film. At this time, the end portion of the wiring 20A near the connection hole formation region (a) is arranged so as to overlap the connection hole formation region (a). Further, the wiring 20C in the vicinity of the connection hole forming region (c) on the gate electrode 5 arranged on the field insulating film 3
Is arranged so as to overlap the connection hole forming region (c).

Next, as shown in FIG. 11, an opening 22 is formed above each of the connection hole forming regions (a), (b) and (c).
A photoresist 23 having A, 22B and 22C is deposited on the interlayer insulating film 21, and the photoresist 23, the second layer wirings 20A, 20B and 20C, and the first layer wiring 10
The interlayer insulating film 21, the interlayer insulating film 12, the insulating film 9, and the gate insulating film 4 are continuously etched by using A, 10B, and 10C as a mask to form a contact hole 24 in the interlayer insulating film 21.
A, 24B, and 24C are connected to the interlayer insulating film 12 by a connection hole 15
A, 15B and 15C are connected to the insulating film 9 with connection holes 16A and 16C.
B and 16C are formed respectively.

At this time, the connection holes 15A, 15B, 15C of the first-layer interlayer insulating film 12 are formed in self-alignment with the second-layer wirings 20A, 20B, 20C, respectively, and the insulating film 9 of the insulating film 9 is formed. The connection holes 16A, 16B, 16C are
The wirings 20A and 20C of the second layer and the wirings 10A, 10B and 10C of the first layer are formed by self-alignment.

Next, after removing the photoresist 23,
Connection holes with high aspect ratio (24A, 24B, 24
C, 15A, 15B, 15C, 16A, 16B, 16
As shown in FIG. 12, since the wiring material is surely embedded in the inside of C), TiN by the CVD method having excellent coverage is formed.
/ Ti film 17 is formed into a connection hole (24A, 24B, 24C, 15
A, 15B, 15C, 16A, 16B, 16C), and then an Al film 25, which is the third layer wiring material, is formed on the entire surface of the semiconductor substrate 1 including connection holes (24A, 24B, 2C).
4C, 15A, 15B, 15C, 16A, 16B, 16
It is deposited by sputtering on the entire surface of the semiconductor substrate 1 including the inside of C).

At this time, the Al film 25 is deposited while the semiconductor substrate 1 is heated to a high temperature. By doing so, the fluidity of Al, which is a metal material having a low melting point, increases, so that the connection holes (24A, 24B, 24C,
15A, 15B, 15C, 16A, 16B, 16C), the Al film 25 can be satisfactorily embedded.

After depositing the Al film 25 by a normal sputtering method, the semiconductor substrate 1 may be heated to a high temperature in a high pressure atmosphere. When the Al film 25 is deposited by the ordinary sputtering method, the connection holes (24A, 24B, 2) having a large aspect ratio are formed.
4C, 15A, 15B, 15C, 16A, 16B, 16
Voids (voids) occur inside C). Then Al
The semiconductor substrate 1 while keeping the surface of the film 25 from being oxidized
When Al is heated to a high temperature in a high pressure atmosphere, the flowability of Al becomes high and the voids are crushed at a high pressure. Therefore, the connection holes (24A, 24B, 24C, 15) having a large aspect ratio are formed.
(A, 15B, 15C, 16A, 16B, 16C), the Al film 25 can be satisfactorily embedded.

Thereafter, Ti is sputtered on the Al film 25.
After depositing the N film, as shown in FIG. 13, the TiN film and the Al film 25 are patterned to form third-layer wirings 25A, 25B, 25C. The wiring 25A is the wiring 2 of the second layer through the connection holes 24A, 15A, 16A.
0A, the wiring 10A of the first layer and the semiconductor region 6A of the MOSFET Qn, and the wiring 25B is connected to the wiring 2 of the second layer through the connection holes 24B, 15B and 16B.
0B, the wiring 10B of the first layer and the semiconductor region 6B of the MOSFET Qn, and the wiring 25C is connected to the gate electrode 5 on the field insulating film 3 through the connection holes 24C, 15C and 16C, respectively. The third
Wiring 25A, 25B, 25C of the second layer, wiring 2 of the second layer
0A, 20B, 20C, first layer wiring 10A, 10
Part of each of B and 10C may be configured with dummy wirings as needed.

According to the above-described manufacturing method of this embodiment, the connection holes (24A, 24B, 24) which have conventionally been formed in three steps are used.
C), connection holes (15A, 15B) and connection holes (16
A, 16B) can be formed in one step,
It is possible to significantly shorten the manufacturing process of a MOS / LSI having an Al3 layer wiring and improve the manufacturing yield.

(Embodiment 3) In Embodiment 2, the connection hole 15A of the first-layer interlayer insulating film 12 is formed in the second-layer wiring 20.
A is formed in self-alignment with respect to A, and the connection hole 16A of the insulating film 9 is provided with the second layer wiring 20A and the first layer wiring 1
Although it was formed by self-alignment with respect to 0 A, for example, as shown in FIG.
As shown in FIG. 4, the connection hole 26A reaching the semiconductor region 6A can be formed by etching the interlayer insulating film 12 and the insulating film 9 using the second layer wirings 20A and 20D as a mask.

Further, the connection holes (24A, 24B, 24C,
26A, 15B, 15C, 16C) and after the Al film 25 is embedded by the method described in the second embodiment, FIG.
, The Al film 25 on the interlayer insulating film 21 is removed by etching back, and then the connection holes 24A, 24B, 24C are removed.
The bump electrodes 28A, 28B, 28C may be formed on the respective upper portions of the above via the barrier metal 27. In this case, some of the bump electrodes 28A, 28B, 28C may be dummy bump electrodes.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above embodiment, the Al two-layer wiring and the Al
Although the example applied to the manufacture of the LSI having the three-layer wiring has been described, the present invention can be applied to the manufacture of the LSI having the four or more wiring layers.

FIG. 15 shows the second-layer wiring 30 and the first wiring.
The wiring 31 of the third layer is used as an etching mask and the wiring 32 of the third layer to the active region 33 (eg, MOSFE
FIG. 6 is a plan view showing an example of a wiring layout in the case of forming a connection hole 34 reaching a source region and a drain region of T). In this example, three layers of wirings 30, 31, 32 extend in the same direction. . This is effective when the alignment margin can be taken in only one of X and Y directions. In this case, some of the wirings 30, 31, 32 may be dummy wirings.

FIG. 16 shows a fourth layer wiring 35 and a third layer wiring 32 extending in the X direction, and a second layer wiring 30 and a first layer wiring extending in the Y direction. 3 is a plan view showing an example of a wiring layout in the case of forming a connection hole 34 reaching the active region 33 with 31. In this example,
In order to avoid a short circuit with the gate electrode 5, the wiring 35 of the fourth layer and the wiring 32 of the third layer are dummy wirings. This is effective when there is no room for alignment in both the X and Y directions.

[0049]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, it is possible to form the connection hole for connecting the wirings in the upper and lower layers and the connection hole for connecting the lower layer wiring and the semiconductor element in one step. The manufacturing process can be shortened and the manufacturing yield can be improved.

(2) According to the present invention, the contact resistance can be reduced and the contact resistance can be reduced even if the diameter of the connection hole is small, so that the reliability and the manufacturing yield of the LSI are improved. be able to.

(3) According to the present invention, it is possible to easily form a connection hole having a diameter equal to or smaller than the minimum processing size of the device, so that it is possible to promote high integration of the LSI.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 9 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 10 is a cross-sectional view of essential parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 15 is a plan view showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 16 is a plan view showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 well 3 field insulating film 4 gate insulating film 5 gate electrode 6A semiconductor region 6B semiconductor region 7 sidewall spacer 8 cap insulating film 9 insulating film 10 metal film 10A wiring 10B wiring 10C wiring 10D wiring 11 photoresist 12 interlayer insulation Film 13A Open hole 13B Open hole 14 Photoresist 15A Connection hole 15B Connection hole 15C Connection hole 16A Connection hole 16B Connection hole 16C Connection hole 17 TiN / Ti film 18 W Film 19A Wiring 19B Wiring 19C Wiring 20A Wiring 20B Wiring 20C Wiring 20D Wiring 21 Interlayer Insulating Film 22A Opening 22B Opening 22C Opening 23 Photoresist 24A Connection Hole 24B Connection Hole 24C Connection Hole 25 Al Film 25A Wiring 25B Wiring 25C Wiring 26A Connection Hole 27 Barrier Metal 28 Bump electrode 28B bump electrode 28C bump electrode 30 wiring 31 wiring 32 wiring 33 active area 34 connecting hole 35 wire

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers on a main surface of a semiconductor substrate, wherein a photoresist formed on a first insulating film covering a predetermined wiring layer is used as a mask. After forming the connection hole in the first insulating film by the etching, the etching is performed by using the photoresist and the wiring of the wiring layer arranged so as to partially overlap the connection hole as a mask. A method of manufacturing a semiconductor integrated circuit device, which further comprises forming a connection hole in the second lower insulating film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a part of the wiring of the wiring layer is formed by a dummy wiring. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a horizontal distance between one end of the opening portion of the photoresist and one end of the wiring of the wiring layer is set to a value of the exposure light. A method for manufacturing a semiconductor integrated circuit device, which is characterized in that the dimensions are equal to or less than the resolution. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming the connection hole in the first and second insulating films, Ti is formed inside the connection hole by a CVD method.
A method for manufacturing a semiconductor integrated circuit device, comprising depositing an N / Ti film. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming the connection hole in the first and second insulating films, a conductive film deposited on the entire surface of the semiconductor substrate is formed. A method of manufacturing a semiconductor integrated circuit device, wherein the conductive film is embedded in the connection hole by etching back. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the connection holes are formed in the first and second insulating films, the semiconductor substrate is heated to a high temperature. A method of manufacturing a semiconductor integrated circuit device, comprising: depositing an Al film on the entire surface to embed the Al film inside the connection hole. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming the connection holes in the first and second insulating films, an Al film is deposited on the entire surface of the semiconductor substrate. Then, by heating the semiconductor substrate to a high temperature in a high-pressure atmosphere, the Al film is embedded in the inside of the connection hole, thereby manufacturing a semiconductor integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the connection hole is formed in the first and second insulating films, and then the connection hole is formed. A method of manufacturing a semiconductor integrated circuit device, comprising forming a bump electrode on the upper part of the substrate.