KR100356482B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100356482B1 KR100356482B1 KR1020000080436A KR20000080436A KR100356482B1 KR 100356482 B1 KR100356482 B1 KR 100356482B1 KR 1020000080436 A KR1020000080436 A KR 1020000080436A KR 20000080436 A KR20000080436 A KR 20000080436A KR 100356482 B1 KR100356482 B1 KR 100356482B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 콘택 플러그를 형성한 후 금속 배선을 형성하는 과정에서 공정 마진을 확보하기 위하여, 콘택 플러그와 금속 배선간의 접촉면을 표면과 측벽으로 하는 3차원적 연결을 실시함으로써 정렬 오차나 금속 배선이 짧아서 발생하는 저항 증가를 방지하고 소자의 불량을 줄여 금속 배선의 전기적 특성 및 수율을 증가시킬 수 있는 반도체 소자의 금속 배선 형성 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In order to secure a process margin in the process of forming a metal wiring after forming a contact plug, a three-dimensional surface having a contact surface between the contact plug and the metal wiring as a sidewall and a sidewall Disclosed is a method of forming a metal wiring of a semiconductor device capable of increasing the electrical properties and yield of the metal wiring by preventing the increase in resistance caused by the alignment error or the short of the metal wiring and reducing the device defect.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 정렬 오차를 감안하여 공정 마진을 확보하고 배선의 저항을 줄여 전기적 특성을 향상시키고 불량을 줄일 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wires in semiconductor devices, and more particularly, to a method for forming metal wires in semiconductor devices that can secure process margins, reduce wiring resistance, improve electrical characteristics, and reduce defects in view of alignment errors. .
일반적인 Deep Sub Micron Logic 제조 공정시 MLM (Multi Level Metalization) 공정은 필수적이다. 그러나 소자의 집적도가 높아지면서 , 디자인 룰이 점점 더 작아지게 된다. 따라서, 오버랩 마진(Overlap Margin)이 거의 없게 된다.MLM (Multi Level Metalization) process is essential in general Deep Sub Micron Logic manufacturing process. However, as device integration increases, design rules become smaller and smaller. Thus, there is almost no overlap margin.
종래의 MLM 제조 방법은 상부 금속 배선(Upper Metal) 과 하부 콘택 플러그(Under Contact) 또는 상부 콘택 플러그(Upper Contact) 과 하부 금속 배선(Under Metal)과의 오버랩 마진(Overlap Margin) 및 금속 배선 정의(metal define)시 끝부분이 짧은 경우(End of line shortening)로 인하여 금속 배선(Metal)에 Opc 공정을 적용하거나, 또는 오버랩 마진 문제 즉 정렬 오차(Mis-align) 문제를 해결하기 위하여 정밀한(Tight) 공정 제어(Control) 및 마스크(Mask) 작업 후 재작업을 해야 하는 등 여러 가지 단점이 있으며, 더 미세한 구조에서는 작업을 할 수 없게 된다. 그리고, 정렬 오차와 배선의단축(Shortening)으로 인한 콘택 플러그와 배선간의 저항 증가 문제로 인해 소자의 신뢰성 문제 및 수율 감소에 결정적인 영향을 미친다.Conventional MLM manufacturing methods use the overlap margin and upper metal wiring definitions of upper metal and lower contact plugs or under contact or upper contact and under metal wiring. Due to the end of line shortening during the metal define, the Opc process is applied to the metal, or the Tight is used to solve the overlap margin problem, that is, the misalignment problem. There are a number of disadvantages, such as the need to rework after process control and masking, and it is impossible to work on finer structures. In addition, an increase in resistance between the contact plug and the wiring due to misalignment and shortening of the wiring has a decisive effect on the reliability and yield reduction of the device.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 콘택 플러그와 금속 배선간의 접촉면을 표면과 측벽으로 하는 3차원적 연결을 실시함으로써 정렬 오차나 금속 배선이 짧아서 발생하는 저항 증가를 방지하고 소자의 불량을 줄여 금속 배선의 전기적 특성 및 수율을 증가시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention prevents an increase in resistance caused by short alignment errors or short metal wires and prevents device defects by implementing a three-dimensional connection using the contact surface between the contact plug and the metal wires as surfaces and sidewalls. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can reduce the electrical characteristics and yield of the metal wiring.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1F are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판 2a : 게이트 산화막1 semiconductor substrate 2a gate oxide film
2b : 폴리실리콘층 2c : 게이트 스페이서2b: polysilicon layer 2c: gate spacer
2d : 소오스/드레인 2 : 트랜지스터2d: source / drain 2: transistor
3 : 층간 절연막 4 : 제 1 Ti막3: interlayer insulating film 4: first Ti film
5 : 제 1 알루미늄층 6 : 제 1 TiN막5: first aluminum layer 6: first TiN film
7 : 제 1 감광막 패턴 8 : 콘택홀7: first photosensitive film pattern 8: contact hole
9 : 제 2 Ti/TiN막 10a : 텅스텐층9: second Ti / TiN film 10a: tungsten layer
10 : 텅스텐 플러그 11 : 제 2 알루미늄층10 tungsten plug 11 second aluminum layer
12 : 제 3 TiN막 13 : 제 2 감광막 패턴12: 3rd TiN film 13: 2nd photosensitive film pattern
115 : 금속 배선 A : 접합면115: metal wiring A: junction surface
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 층간 절연막, 접착층, 제 1 금속 배선층 및 제 1 반사 방지막을 형성하는 단계, 제 1 반사 방지막, 제 1 금속 배선층, 접착층 및 층간 절연막의 소정 영역을 식각하여 반도체 기판의 접합 영역을 노출시키는 콘택홀을 형성하는 단계, 측벽에 제 1 금속 배선층의 측면이 노출된 콘택홀에 콘택 플러그를 형성하는 단계, 제 1 금속 배선층의 표면이 노출될 때까지 평탄화 공정을 실시하는 단계, 전체 상에 제 2 금속 배선층 및 제 2 반사 방지막을 형성하는 단계 및 제 2 감광막 패턴을 형성하여 제 2 반사 방지막의 소정 영역을 노출시킨 후 식각 공정으로 콘택 플러그를 분리하기 위하여 소정 영역의 제 2 반사 방지막, 제 2 금속 배선층 및 제 1 금속 배선층을 식각하여 제 1 및 제 2 금속 배선층으로 이루어진 금속 배선을 형성하는 단계로 이루어진다.Method of forming a metal wiring of a semiconductor device according to the present invention comprises the steps of forming an interlayer insulating film, an adhesive layer, a first metal wiring layer and a first antireflection film on a semiconductor substrate formed with a number of elements for forming a semiconductor device, a first antireflection film, Etching a predetermined region of the first metal interconnection layer, the adhesive layer, and the interlayer insulating layer to form a contact hole exposing a junction region of the semiconductor substrate, and forming a contact plug in the contact hole exposing the side surface of the first metal interconnection layer on the sidewall Performing a planarization process until the surface of the first metal wiring layer is exposed, forming a second metal wiring layer and a second antireflection film over the entire surface, and forming a second photoresist film pattern to form a predetermined region of the second antireflection film. The second anti-reflection film, the second metal wiring layer, and the first anti-reflection film in a predetermined area to expose the contact plug by an etching process after exposing By etching the wiring layer in a step of forming a metal wiring made of a first and second metal wiring layer.
접착층은 Ti막으로 형성제 1 및 제 2 금속 배선층은 알루미늄으로 형성한다. 이때, 제 1 금속 배선층은 상기 콘택 플러그의 접합 면적에 따라 형성 두께를 조절한다. 반사 방지막은 TiN막으로 형성하며, 콘택 플러그는 접착 활성층을 먼저 형성한 후 텅스텐으로 형성한다. 이때, 접착 활성층은 Ti/TiN막으로 형성한다.The adhesive layer is formed of Ti film, and the first and second metal wiring layers are formed of aluminum. At this time, the first metal wiring layer adjusts the formation thickness according to the junction area of the contact plug. The antireflection film is formed of a TiN film, and the contact plug is formed of tungsten after first forming an adhesive active layer. At this time, the adhesive active layer is formed of a Ti / TiN film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1F are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 1a를 참조하면, 게이트 산화막(2a), 폴리실리콘층(2b), 게이트 스페이서(2c) 및 소오스/드레인(2d)으로 구성되는 트랜지스터(2)를 포함한 여러 요소가 형성된 반도체 기판(1) 상에 층간 절연막(3)을 형성한 후 제 1 Ti막(4), 제 1 알루미늄층(5) 및 제 1 TiN막(6)을 순차적으로 형성한다.Referring to FIG. 1A, on a semiconductor substrate 1 on which various elements are formed, including a transistor 2 composed of a gate oxide film 2a, a polysilicon layer 2b, a gate spacer 2c, and a source / drain 2d. After the interlayer insulating film 3 is formed on the first Ti film 4, the first aluminum layer 5 and the first TiN film 6 are sequentially formed.
제 1 Ti막(4)은 층간 절연막(3)과 제 1 알루미늄층(5)의 접착층 역할을 하며, 제 1 TiN막(6)은 반사 방지막의 역할을 한다.The first Ti film 4 serves as an adhesive layer between the interlayer insulating film 3 and the first aluminum layer 5, and the first TiN film 6 serves as an antireflection film.
도 1b를 참조하면, 제 1 감광막 패턴(7)을 형성하여 콘택홀이 형성될 영역을 정의한 후 제 1 TiN막(6), 제 1 알루미늄층(5), 제 1 Ti막(4) 및 층간 절연막(3)을 식각하여 반도체 기판(1)의 접합면, 예를 들어 소오스/드레인(2d) 또는 폴리실리콘층(2b)이 노출되는 콘택홀(8)을 형성한다.Referring to FIG. 1B, the first photoresist film pattern 7 is formed to define a region where a contact hole is to be formed, and then the first TiN film 6, the first aluminum layer 5, the first Ti film 4, and the interlayer are formed. The insulating film 3 is etched to form a contact hole 8 exposing a bonding surface of the semiconductor substrate 1, for example, the source / drain 2d or the polysilicon layer 2b.
도 1c를 참조하면, 제 1 감광막 패턴(7)을 제거하고, 콘택홀(8)을 포함한 전체 상에 제 2 Ti/TiN막(9)을 형성한 후 텅스텐을 증착하여 텅스텐층(10a)을 형성하되 콘택홀(8) 내부에 텅스텐이 충분히 매립될 수 있도록 증착한다.Referring to FIG. 1C, the first photosensitive film pattern 7 is removed, the second Ti / TiN film 9 is formed on the whole including the contact hole 8, and then tungsten is deposited to form the tungsten layer 10a. It is formed to be deposited so that tungsten is sufficiently embedded in the contact hole (8).
제 2 Ti/TiN(9)막은 확산 방지막으로써의 역할도 하지만, 층간 절연막(3)으로는 텅스텐이 잘 증착되지 않기 때문에 텅스텐의 증착을 활성화시키는 역할을 하므로 텅스텐이 콘택홀(8) 내부로 용이하게 매립될 수 있도록 한다.The second Ti / TiN (9) film also serves as a diffusion barrier, but since tungsten is not deposited well as the interlayer insulating film 3, the second Ti / TiN (9) film serves to activate the deposition of tungsten. To be reclaimed.
도 1d를 참조하면, 화학적 기계적 연마(CMP)를 실시하여 텅스텐층(10a), 제 2 Ti/TiN막(9), 제 1 TiN막(6)을 제거하여 제 1 알루미늄층(5)을 노출시키고, 제 2 Ti/TiN막(9)과 텅스텐을 콘택홀(8) 내부에만 잔류시켜 텅스텐 플러그(10)를 형성한다. 이때, 텅스텐 플러그(10)는 제 1 알루미늄층(5)에 의해 모두 연결된다.Referring to FIG. 1D, chemical mechanical polishing (CMP) is performed to remove the tungsten layer 10a, the second Ti / TiN film 9, and the first TiN film 6 to expose the first aluminum layer 5. The tungsten plug 10 is formed by leaving the second Ti / TiN film 9 and tungsten only inside the contact hole 8. At this time, the tungsten plugs 10 are all connected by the first aluminum layer 5.
따라서, 제 1 알루미늄층(5)의 형성 두께는 텅스텐 플러그(10)와의 접촉 면적이 되므로, 도 1a에서 제 1 알루미늄층(5)을 형성할 때 텅스텐 플러그(10)와의 접촉 면적을 고려하여 형성 두께를 결정한다.Therefore, since the formation thickness of the first aluminum layer 5 becomes the contact area with the tungsten plug 10, the thickness is formed in consideration of the contact area with the tungsten plug 10 when the first aluminum layer 5 is formed in FIG. 1A. Determine the thickness.
도 1e를 참조하면, 텅스텐 플러그(10)를 포함한 제 1 알루미늄층(5) 상에 제 2 알루미늄층(11), 제 3 TiN막(12)을 형성한 후 제 2 감광막 패턴(13)을 형성하여 제 1 및 제 2 알루미늄층(5 및 11)의 식각 영역의 노출시킨다.Referring to FIG. 1E, after forming the second aluminum layer 11 and the third TiN film 12 on the first aluminum layer 5 including the tungsten plug 10, the second photosensitive film pattern 13 is formed. Thereby exposing the etching regions of the first and second aluminum layers 5 and 11.
여기서도, 제 3 TiN막(12)은 반사 방지막의 역할을 한다.Here, the third TiN film 12 also serves as an antireflection film.
도 1f를 참조하면, 텅스텐 플러그(10) 간의 연결이 필요한 부분은 제 1 및 제 2 알루미늄층(5 및 11)을 잔류시키고, 각각의 텅스텐 플러그(10)를 분리해야 할경우에는 노출된 제 3 TiN막(12), 제 2 알루미늄층(11) 및 제 1 알루미늄층(5)을 식각하여 제 1 및 제 2 알루미늄층(5 및 11)으로 이루어진 금속 배선(115)을 형성한다.Referring to FIG. 1F, the portion that needs to be connected between the tungsten plugs 10 leaves the first and second aluminum layers 5 and 11, and the exposed third when each tungsten plug 10 needs to be separated. The TiN film 12, the second aluminum layer 11, and the first aluminum layer 5 are etched to form a metal wiring 115 made of the first and second aluminum layers 5 and 11.
금속 배선(115)과 텅스텐 플러그(10)의 접합면(A)을 보면, 텅스텐 플러그(10)의 측벽과 상부 표면을 금속 배선(115)과의 접합면(A)으로 한다. 다시 말해, 접합면을 상부 표면만으로 국한하는 것이 아니라, 텅스텐 플러그(10)의 측벽까지 접합면으로 사용함으로써 3차원적 접합면을 형성한다. 이로 인해, 제 2 알루미늄층(11)이 짧게 형성되어 접합면이 줄어도 제 1 알루미늄층(5)이 보상해 줌으로써 텅스텐 플러그(10)와 금속 배선(115) 간의 저항을 줄이고, 공정 마진을 확보할 수 있다.When the joint surface A of the metal wiring 115 and the tungsten plug 10 is seen, the side wall and the upper surface of the tungsten plug 10 are made into the joint surface A with the metal wiring 115. In other words, the three-dimensional bonding surface is formed by not only limiting the bonding surface to the upper surface but also as the bonding surface up to the side wall of the tungsten plug 10. As a result, even if the second aluminum layer 11 is formed to be short and the bonding surface is reduced, the first aluminum layer 5 compensates to reduce the resistance between the tungsten plug 10 and the metal wiring 115 and to secure a process margin. can do.
상술한 바와 같이, 본 발명은 금속 배선을 다층 구조로 형성하여 텅스텐 플러그와 금속 배선간의 저항을 줄이고, 공정 마진을 확보하여 배선의 전기적 특성을 향상시키고 불량을 줄여 수율을 증가시키는 효과가 있다.As described above, the present invention has the effect of reducing the resistance between the tungsten plug and the metal wiring by forming a metal wiring in a multi-layer structure, to secure a process margin to improve the electrical characteristics of the wiring and reduce the defects to increase the yield.
Claims (7)
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291408A (en) * | 1992-04-15 | 1993-11-05 | Nippon Steel Corp | Semiconductor device and its manufacture |
| JPH09293790A (en) * | 1996-04-25 | 1997-11-11 | Nec Corp | Semiconductor device and manufacture thereof |
| US5744395A (en) * | 1996-10-16 | 1998-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure |
| JPH10335666A (en) * | 1997-05-27 | 1998-12-18 | Sharp Corp | Manufacture of semiconductor device |
| US5915197A (en) * | 1993-10-07 | 1999-06-22 | Nec Corporation | Fabrication process for semiconductor device |
| JP2000208623A (en) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | Semiconductor device and production thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291408A (en) * | 1992-04-15 | 1993-11-05 | Nippon Steel Corp | Semiconductor device and its manufacture |
| US5915197A (en) * | 1993-10-07 | 1999-06-22 | Nec Corporation | Fabrication process for semiconductor device |
| JPH09293790A (en) * | 1996-04-25 | 1997-11-11 | Nec Corp | Semiconductor device and manufacture thereof |
| US5744395A (en) * | 1996-10-16 | 1998-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure |
| JPH10335666A (en) * | 1997-05-27 | 1998-12-18 | Sharp Corp | Manufacture of semiconductor device |
| JP2000208623A (en) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | Semiconductor device and production thereof |
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