KR100452315B1 - Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole - Google Patents

Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole Download PDF

Info

Publication number
KR100452315B1
KR100452315B1 KR1019970081580A KR19970081580A KR100452315B1 KR 100452315 B1 KR100452315 B1 KR 100452315B1 KR 1019970081580 A KR1019970081580 A KR 1019970081580A KR 19970081580 A KR19970081580 A KR 19970081580A KR 100452315 B1 KR100452315 B1 KR 100452315B1
Authority
KR
South Korea
Prior art keywords
metal
film
forming
insulating film
interlayer insulating
Prior art date
Application number
KR1019970081580A
Other languages
Korean (ko)
Other versions
KR19990061322A (en
Inventor
손경목
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1019970081580A priority Critical patent/KR100452315B1/en
Publication of KR19990061322A publication Critical patent/KR19990061322A/en
Application granted granted Critical
Publication of KR100452315B1 publication Critical patent/KR100452315B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent contact resistance from being increased in a via hole by forming a metal pillar of the same size as the via hole on a metal interconnection and by filling a space between metal pillars with an insulation material. CONSTITUTION: The first metal interconnection(102) is formed in a predetermined portion on a semiconductor substrate(100) including an insulation layer. A temporary layer(104) is formed in a space between the first metal interconnections on the substrate. A metal pillar(106a) for a conductive plug is formed in a predetermined portion on the first metal interconnection. An interlayer dielectric is formed in a space between the metal pillars on the first metal interconnection and the temporary layer. The second metal interconnection is formed in a predetermined on the interlayer dielectric so as to be connected to the metal pillar.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 발명은 반도체 소자 제조방법에 관한 것으로, 보다 상세하게는 반도체 소자의 다층 배선 형성시 야기되는 공정 불량을 방지할 수 있도록 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a process defect caused when forming a multilayer wiring of a semiconductor device.

딥 서브마이크론(deep submicron) 시대로 접어들면서, 반도체 소자 제조시 더 적은 면적에 더 많은 단일 소자를 집적화하기 위하여, W-플러그, Al-플로우 및, CMP(chemical mechanical polishing) 공정을 조합한 다층 배선 공정의 적용이 필연적으로 요구되고 있다.Entering the era of deep submicron, multilayer wiring combining W-plug, Al-flow, and chemical mechanical polishing (CMP) processes to integrate more single devices in a smaller area when manufacturing semiconductor devices Application of the process is inevitably required.

상기 다층 배선은, 비어 홀이 구비된 절연막을 사이에 두고 그 상/하부에 형성된 임의의 금속 배선이 상기 비어 홀 내에 충진된 도전성 플러그(예컨대, W 플러그)를 매개체로하여 서로 전기적으로 연결되는 구조를 가지도록 형성되는데, 이러한 다층 배선 공정이 초고집적 반도체 소자 제조시 큰 비중을 차지하는 것은, 집적회로들을 구성하는 단일 소자들이 공정 불량없이 회로적으로 잘 연결될 때, 비로서 온전한 반도체 소자로서 동작할 수 있기 때문이다.The multi-layered wiring has a structure in which any metal wirings formed on and under the insulating film having via holes are electrically connected to each other via a conductive plug (eg, a W plug) filled in the via holes. This multi-layered wiring process takes up a large portion in the manufacture of ultra-high density semiconductor devices, which can operate as an intact semiconductor device when the single devices constituting the integrated circuits are connected well in a circuit without process failure. Because there is.

도 1에는 이 다층 배선 공정과 관련된 종래의 일반적인 반도체 소자 제조방법을 도시한 공정수순도가 제시되어 있다. 이를 참조하여 그 제조방법을 제 3 단계로 구분하여 살펴보면 다음과 같다.1 is a process flowchart showing a conventional method for manufacturing a semiconductor device related to the multilayer wiring process. Referring to this, looking at the manufacturing method divided into three steps as follows.

제 1 단계로서, 도 1에 도시된 바와 같이 절연막(미 도시)이 구비된 반도체 기판(10) 상의 소정 부분에 Al 합금이나 Cu 합금 재질의 제 1 금속 배선(12)을 형성한 후, 제 1 금속 배선(12)을 포함한 기판(10) 전면에 소정 두께의 층간 절연막(14)을 형성하고, 이를 화학적기계적연마법(이하, CMP라 한다)으로 평탄화한 다음, 비어 홀이 형성될 부분의 절연막(14) 표면이 소정 노출되도록 그 위에 감광막 패턴(16)을 형성한다.As a first step, as shown in FIG. 1, after forming the first metal wiring 12 of Al alloy or Cu alloy material on a predetermined portion on the semiconductor substrate 10 provided with an insulating film (not shown), An interlayer insulating film 14 having a predetermined thickness is formed on the entire surface of the substrate 10 including the metal wiring 12, and then planarized by chemical mechanical polishing (hereinafter referred to as CMP), and then an insulating film at the portion where the via hole is to be formed. (14) The photosensitive film pattern 16 is formed on it so that the surface may be exposed.

제 2 단계로서, 도 2에 도시된 바와 같이 감광막 패턴(16)을 마스크로 이용하여, 제 1 금속 배선(12)의 표면이 소정 부분 노출되도록 층간 절연막(14)을 선택 식각하여 상기 절연막(14) 내에 비어 홀(h)을 형성한다. 이 과정에서, 상기 감광막 패턴(16)도 함께 식각이 이루어지게 된다. 이어, 식각 공정 진행시 발생된 폴리머 성분과 식각 공정중에 제거되지 못하고 남겨진 감광막 패턴의 잔여분을 제거하기 위하여 에싱(ashing) 공정을 실시하고, 기판 세정 공정을 실시한 후, 비어 홀(h) 내부에만 선택적으로 Ti/TiN 적층막 구조의 장벽금속막(미 도시)을 형성해 준다. 이와 같이, 장벽 금속막을 형성해준 것은 후속 공정의 하나인 W 재질의 막질 증착 공정이 원활하게 이루어지도록 하기 위함이다. 그 다음, 상기 비어 홀(h) 내의 장벽 금속막을 포함한 층간 절연막(14) 상에 W 재질의 금속막을 CVD법으로 형성하고, 이를 CMP 공정으로 평탄화시켜, 비어 홀(h) 내에 W 플러그(18)를 형성한다.As a second step, using the photosensitive film pattern 16 as a mask, as shown in FIG. 2, the interlayer insulating film 14 is selectively etched to expose a predetermined portion of the surface of the first metal wire 12 to form the insulating film 14. The via hole h is formed in the (). In this process, the photoresist pattern 16 is also etched together. Subsequently, an ashing process is performed to remove the polymer components generated during the etching process and the remaining portions of the photoresist pattern left unremoved during the etching process, and after the substrate cleaning process, are selectively selected only inside the via hole h. As a result, a barrier metal film (not shown) having a Ti / TiN laminated film structure is formed. As such, the barrier metal film is formed so that the film quality deposition process of the W material, which is one of subsequent processes, is smoothly performed. Next, a metal film made of W material is formed on the interlayer insulating film 14 including the barrier metal film in the via hole h by CVD, and planarized by a CMP process, so that the W plug 18 is formed in the via hole h. To form.

제 3 단계로서, 도 3에 도시된 바와 같이 W 플러그(18)와 연결되도록, 층간 절연막(14) 상의 소정 부분에 Al 합금이나 Cu 합금 재질의 제 2 금속 배선(20)을 형성하므로써, 반도체 소자의 다층 배선 공정을 완료한다.As a third step, the semiconductor element is formed by forming the second metal wiring 20 made of Al alloy or Cu alloy in a predetermined portion on the interlayer insulating film 14 so as to be connected to the W plug 18 as shown in FIG. Complete the multi-layer wiring process.

그러나, 상기에 언급된 공정을 이용하여 반도체 소자의 다층 배선을 형성할 경우에는 비어 홀(h) 형성시와 그 내부에 W 플러그(18)를 형성해 주는 과정에서 다음과 같은 몇가지의 문제점이 발생하게 된다.However, when the multilayer wiring of the semiconductor device is formed using the above-mentioned process, several problems may occur when the via hole h is formed and in the process of forming the W plug 18 therein. do.

첫째, 비어 홀(h) 형성 이후에 실시되는 에싱 공정이 약 300℃ 내외의 온도에서 진행되므로, 이 과정에서 비어 홀(h)과 접촉되는 제 1 금속 배선(12)의 표면 노출부가 온도 변화에 따른 열팽창으로 인해, 비어 홀(h) 내부로 솟아 오르는 결함이 발생하게 되고 둘째, 기판 세정 공정 진행시, 세정 작업에 이용되는 케미컬 성분의 일부가 비어 홀(h) 하부의 제 1 금속 배선(12)을 옆으로 치고 들어가, 금속 배선을 언더컷(undercut)시키는 현상이 야기되며 셋째, CVD법을 이용한 W 재질의 금속막 형성시, 비어 홀(h) 내부에 기 형성된 장벽 금속막이 타겟 물질로 사용되는 WF6가스를 막아주지 못하여, 비어 홀(h)과 연결된 제 1 금속 배선(12)의 표면이 손상되는 단점이 발생하게 된다.First, since the ashing process performed after the formation of the via hole h is performed at a temperature of about 300 ° C., the exposed portion of the surface of the first metal wire 12 that is in contact with the via hole h in this process is affected by temperature change. Due to the thermal expansion, a defect that rises into the via hole h may occur. Second, when the substrate cleaning process is performed, a part of the chemical component used for the cleaning operation may be removed from the first metal wiring 12 under the via hole h. ) Sideways to undercut the metal wiring. Third, when the metal film of W material is formed by the CVD method, a barrier metal film previously formed inside the via hole h is used as a target material. Since the WF 6 gas is not blocked, the surface of the first metal wire 12 connected to the via hole h may be damaged.

이러한 단점들은, 비어 홀(h)의 콘택 저항을 증가시키는 결과를 초래하여 결국에는 반도체 소자의 공정 신뢰성 저하와 수율 저하 등과 같은 문제를 야기시키게 되므로, 이에 대한 개선책이 시급하게 요구되고 있다.These shortcomings lead to an increase in the contact resistance of the via hole h, which in turn causes problems such as lower process reliability and lower yield of the semiconductor device, and therefore an urgent need for improvement is required.

이에 본 발명의 목적은, 금속 배선 상에 비어 홀과 동일한 사이즈의 금속 필러(metal pillar)를 형성한 다음, 그 이후에 금속 필러 사이의 공간을 절연 물질(예컨대, SOG막)로 채워주는 방식으로 반도체 소자의 다층 배선을 형성해 주므로써, 기존 배선 공정 진행시 야기되던 비어 홀에서의 콘택 저항 증가 현상을 방지할 수 있도록 한 반도체 소자 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to form a metal pillar of the same size as a via hole on a metal wiring, and then fill the space between the metal pillars with an insulating material (for example, an SOG film). By providing a multi-layered wiring of the semiconductor device, to provide a semiconductor device manufacturing method that can prevent the increase in contact resistance in the via hole caused during the existing wiring process.

도 1 내지 도 3은 종래의 반도체 소자 제조방법을 도시한 공정수순도,1 to 3 is a process flowchart showing a conventional semiconductor device manufacturing method,

도 4 내지 도 10은 본 발명의 일 실시예에 의한 반도체 소자 제조방법을 도시한 공정수순도.4 to 10 are process flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

상기 목적을 달성하기 위하여 본 발명에서는, 절연막이 구비된 반도체 기판 상의 소정 부분에 제 1 금속 배선을 형성하는 공정과, 상기 기판 상의, 상기 제 1 금속 배선 사이의 공간에 임의막을 형성하는 공정과, 상기 제 1 금속 배선 상의 소정 부분에 도전성 플러그용 금속 필러를 형성하는 공정과, 상기 제 1 금속 배선과 상기 임의막 상의, 상기 금속 필러 사이의 공간에 층간 절연막을 형성하는 공정 및, 상기 금속 필러와 연결되도록, 상기 층간 절연막 상의 소정 부분에 제 2 금속 배선을 형성하는 공정으로 이루어진 반도체 소자 제조방법이 제공된다.In order to achieve the above object, in the present invention, a step of forming a first metal wiring on a predetermined portion on a semiconductor substrate with an insulating film, a step of forming an arbitrary film in the space between the first metal wiring on the substrate, Forming a conductive metal filler for a predetermined plug on the first metal wiring; forming an interlayer insulating film in a space between the metal filler on the first metal wiring and the arbitrary film; and the metal filler; A semiconductor device manufacturing method is provided, which comprises a step of forming a second metal wiring on a predetermined portion on the interlayer insulating film so as to be connected.

상기와 같이 공정을 진행할 경우, 기존의 다층 배선 형성시 요구되던 비어 홀 형성 공정없이도 도전성 플러그의 역할을 하는 금속 필러 형성이 가능하게 되므로, 비어 홀 형성시나 혹은 그 내부에 금속막 형성시 야기되던 공정 불량을 제거할 수 있게 된다.In the case of proceeding as described above, a metal filler serving as a conductive plug can be formed without a via hole forming process, which is required for forming a conventional multi-layer wiring, and thus a process caused when forming a via hole or forming a metal film therein. The defect can be eliminated.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

본 발명은, 다층 배선 공정중의 하나인 비어 홀 형성시와 그 내부에 금속막 증착시 야기되는 공정 불량을 제거하기 위하여, 임의의 금속 배선 간을 전기적으로 연결해 주는 금속 필러를 광식각 공정을 이용하여 비어 홀과 동일한 사이즈로 형성한 뒤, 그 이후에 금속 필러 사이의 공간을 절연 물질(예컨대, "HDP/TEOS" 적층 구조의 층간 절연막)로 채워주는 방식으로 반도체 소자의 다층 배선을 형성하고자 하는 기술로서, 이를 도 4 내지 도 10의 도면을 참조하여 살펴보면 다음과 같다.The present invention utilizes a photo-etching process using a metal filler that electrically connects any metal wiring to eliminate process defects caused during the formation of a via hole, which is one of the multilayer wiring processes, and the deposition of a metal film therein. To form the same size as the via hole, and then fill the space between the metal pillars with an insulating material (for example, an interlayer insulating film of a "HDP / TEOS" laminated structure). As a technique, this will be described with reference to the drawings of FIGS. 4 to 10.

여기서, 도 4 내지 도 10은 본 발명의 일 실시예에 의한 반도체 소자 제조방법을 도시한 공정수순도를 나타낸 것으로, 이를 참조하여 그 제조방법을 6 단계로 구분하여 살펴보면 다음과 같다.4 to 10 illustrate a process flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to this, the manufacturing method is classified into six steps as follows.

제 1 단계로서, 도 4에 도시된 바와 같이 절연막(미 도시)이 구비된 반도체 기판(100) 상의 소정 부분에 Al 합금이나 Cu 합금 재질의 제 1 금속 배선(102)을 형성한다.As a first step, as shown in FIG. 4, a first metal wire 102 made of Al alloy or Cu alloy is formed on a predetermined portion of the semiconductor substrate 100 provided with an insulating film (not shown).

제 2 단계로서, 도 5에 도시된 바와 같이 제 1 금속 배선(102)을 포함한 기판(100) 전면에 SOG(silicon 0n glass) 재질의 임의막(104)을 4500 ~ 5500Å의 두께로 형성하고, 제 1 금속 배선(102)의 표면이 노출될 때까지 상기 임의막(104)을 에치백하여, 제 1 금속 배선(102) 사이 사이의 공간(space)이 임의막(104)으로 채워지도록 한다.As a second step, as shown in FIG. 5, an arbitrary film 104 made of SOG (silicon 0n glass) material is formed on the entire surface of the substrate 100 including the first metal wiring 102 to a thickness of 4500 to 5500 Å. The arbitrary film 104 is etched back until the surface of the first metal wire 102 is exposed, so that the space between the first metal wires 102 is filled with the arbitrary film 104.

제 3 단계로서, 도 6에 도시된 바와 같이 제 1 금속 배선(102)과 임의막(104) 상에 W이나 Al 합금(예컨대, Al-X%Cu) 재질의 금속막(106)을 9000 ~ 11000Å의 두께로 형성한다. 이때, Al 합금으로는 주로, Al-0.5%Cu이나 Al-1.0%Cu가 사용된다.As a third step, as illustrated in FIG. 6, a metal film 106 made of W or an Al alloy (eg, Al-X% Cu) material is formed on the first metal wiring 102 and the arbitrary film 104. It is formed to a thickness of 11000Å. At this time, Al-0.5% Cu or Al-1.0% Cu is mainly used as Al alloy.

제 4 단계로서, 도 7에 도시된 바와 같이 금속막(106) 상에 감광막을 형성하고, 상기 금속막(106)의 표면이 소정 부분 노출되도록 이를 선택식각하여 금속 필러가 형성될 부분을 한정하는 감광막 패턴(108)을 형성한다.As a fourth step, as shown in FIG. 7, a photoresist film is formed on the metal film 106, and the surface of the metal film 106 is selectively etched to expose a predetermined portion to define a portion where the metal filler is to be formed. The photosensitive film pattern 108 is formed.

제 5 단계로서, 도 8에 도시된 바와 같이 감광막 패턴(108)을 마스크로 이용한 광식각 공정으로 상기 금속막(106)을 식각하여, 도전성 플러그로 사용될 금속 필러(106a)를 형성하고, 감광막 패턴(108)을 제거한다. 이 과정에서, 제 1 금속 배선(102)의 일부가 오버 에치(over etch)되므로, 금속막(106) 식각 공정이 완료된 이후에는 제 1 금속 배선(102)의 표면이 소정 두께 리세스(recess)된 구조를 가지게 된다.As a fifth step, as shown in FIG. 8, the metal film 106 is etched by a photoetch process using the photoresist pattern 108 as a mask to form a metal filler 106a to be used as a conductive plug, and the photoresist pattern Remove 108. In this process, a part of the first metal wire 102 is over etched, so that after the etching of the metal film 106 is completed, the surface of the first metal wire 102 is recessed by a predetermined thickness. It has a structure.

제 6 단계로서, 도 9에 도시된 바와 같이 금속 필러(106a)를 포함한 제 1 금속 배선(102)과 임의막(104) 상에, 6500 ~ 7500Å 두께의 HDP(high density plasma)와, 13500 ~ 14500Å의 두께의 TEOS를 순차적으로 증착하여, "HDP/TEOS" 적층 구조의 층간 절연막(110)을 형성한다. 이와 같이, 층간 절연막(110)을 이층 적층 구조로 형성해 준 것은 HDP의 막질 특성이 조밀하여 갭필(gapfill) 능력이 우수하기 때문이다.As a sixth step, as shown in FIG. 9, on the first metal wiring 102 including the metal filler 106a and the arbitrary film 104, a high density plasma (HDP) of 6500-7500 Å thickness and 13500- TEOS having a thickness of 14500 GPa is sequentially deposited to form an interlayer insulating film 110 having a "HDP / TEOS" laminated structure. The reason why the interlayer insulating film 110 is formed in a two-layered laminated structure is that HDP has a high film quality and excellent gap fill capability.

제 7 단계로서, 도 10에 도시된 바와 같이 금속 필러(106a)의 표면이 노출될 때까지 상기 층간 절연막(110)을 CMP처리하여 평탄화해 준 다음, 금속 필러(106a)와 연결되도록 그 위의 소정 부분에 Al 합금이나 Cu 합금 재질의 제 2 금속 배선(112)을 형성해 주므로써, 본 공정 진행을 완료한다. 이때, 상기 층간 절연막(110)은 도면 상에는 도시되지는 않았지만, 금속 필러(106a)보다 약 950 ~ 1050Å 정도 낮은 단차를 가지도록 CMP 처리해 주는 것이 바람직한데, 이것은 금속 필러(106a)와 제 2 금속 배선(112) 간의 접촉 불량을 방지하기 위함이다.As a seventh step, as shown in FIG. 10, the interlayer insulating film 110 is planarized by CMP until the surface of the metal filler 106a is exposed, and then the upper surface of the interlayer insulating film 110 is connected to the metal filler 106a. The process of this process is completed by forming the 2nd metal wiring 112 of Al alloy or Cu alloy material in a predetermined part. In this case, although not shown in the drawing, the interlayer insulating film 110 is preferably subjected to CMP treatment to have a step that is about 950 to 1050 낮은 lower than the metal filler 106a, which is the metal filler 106a and the second metal wiring. This is to prevent a poor contact between the 112.

이러한 공정 수순에 의거하여 반도체 소자의 다층 배선을 형성할 경우, 비어 홀 형성 공정없이도 광식각 공정을 이용하여 기존의 비어 홀과 동일한 사이즈의 금속 필러를 형성할 수 있게 되므로, 공정 신뢰성을 향상시킬 수 있게 되어, 비어 홀 형성시나 혹은 도전성 플러그 형성시 야기되던 공정 불량을 제거할 수 있게 된다.In the case of forming the multilayer wiring of the semiconductor device based on the above-described process procedure, it is possible to form a metal filler having the same size as the existing via hole using the photoetch process without the via hole forming process, thereby improving process reliability. As a result, process defects caused during the formation of the via hole or the formation of the conductive plug can be eliminated.

이상에서 살펴본 바와 같이 본 발명에 의하면, 광식각 공정을 이용하여 임의의 금속 배선 상에 비어 홀과 동일한 사이즈를 갖는 금속 필러를 형성한 다음, 그 이후에 금속 필러 사이의 공간을 갭 필 특성이 우수한 층간 절연막으로 채워주는 방식으로 반도체 소자의 다층 배선 공정을 진행해 주므로써, 다층 배선 형성시 통상적으로 요구되던 비어 홀 형성 공정과 금속막 증착 공정을 스킵할 수 있게 되므로, 이로 인해 야기되던 공정 불량(예컨대, 에싱 공정시 비어 홀 내부에 제 1 금속 배선의 일부가 솟아 오르는 결함, 세정 작업시 케미컬 성분의 일부가 비어 홀 하부의 제 1 금속 배선을 옆으로 치고 들어가 제 1 금속 배선을 언더컷시키는 현상, CVD법에 의한 금속막 증착시 야기되는 제 1 금속 배선의 표면 손상 등)을 제거할 수 있게 되어, 금속 필러와 금속 배선 간의 접촉 저항을 줄일 수 있게 된다.As described above, according to the present invention, a metal pillar having the same size as a via hole is formed on an arbitrary metal interconnection by using an optical etching process, and thereafter, the space between the metal pillars has excellent gap fill characteristics. By performing the multi-layer wiring process of the semiconductor device by filling it with an interlayer insulating film, it is possible to skip the via hole forming process and the metal film deposition process, which are typically required when forming the multi-layer wiring, and thus, process defects caused by , A defect in which a part of the first metal wiring rises inside the via hole during the ashing process, and a part of the chemical component hits the first metal wiring under the via hole to the side during the cleaning operation to undercut the first metal wiring, CVD Surface damage of the first metal wiring caused by the deposition of the metal film by the method, etc.) can be removed. It is possible to reduce the contact resistance between the wires.

Claims (13)

절연막이 구비된 반도체 기판 상의 소정 부분에 제 1 금속 배선을 형성하는 공정과,Forming a first metal wiring on a predetermined portion on the semiconductor substrate provided with the insulating film; 상기 기판 상의, 상기 제 1 금속 배선 사이의 공간에 임의막을 형성하는 공정과,Forming an arbitrary film in the space between the first metal wirings on the substrate; 상기 제 1 금속 배선 상의 소정 부분에 도전성 플러그용 금속 필러를 형성하는 공정과,Forming a metal filler for a conductive plug in a predetermined portion on the first metal wiring; 상기 제 1 금속 배선과 상기 임의막 상의, 상기 금속 필러 사이의 공간에 층간 절연막을 형성하는 공정 및,Forming an interlayer insulating film in a space between the metal filler and the metal film on the first metal wiring; 상기 금속 필러와 연결되도록, 상기 층간 절연막 상의 소정 부분에 제 2 금속 배선을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체 소자 제조방법.And forming a second metal wiring on a predetermined portion on the interlayer insulating film so as to be connected to the metal filler. 제 1항에 있어서, 상기 제 1 금속 배선 사이의 공간에 임의막을 형성하는 공정은, 상기 제 1 금속 배선을 포함한 상기 기판 전면에 임의막을 형성하는 공정과, 상기 제 1 금속 배선의 표면이 노출될 때까지 상기 임의막을 에치백하는 공정으로 이루어진 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the forming of the arbitrary film in the space between the first metal wires comprises: forming an arbitrary film on the entire surface of the substrate including the first metal wire and exposing a surface of the first metal wire. A method of manufacturing a semiconductor device, comprising the step of etching back the arbitrary film until the process. 제 2항에 있어서, 상기 임의막은 4500 ~ 5500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 2, wherein the optional film is formed to a thickness of 4500 to 5500 Å. 제 2항에 있어서, 상기 임의막은 SOG로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 2, wherein the optional film is formed of SOG. 제 1항에 있어서, 상기 제 1 금속 배선 상의 소정 부분에 도전성 플러그용 금속 필러를 형성하는 공정은, 상기 제 1 금속 배선과 상기 임의막 상에 금속막을 형성하는 공정과, 상기 금속막 상의 소정 부분에 감광막 패턴을 형성하는 공정 및, 상기 감광막 패턴을 마스크로 이용하여 상기 금속막을 식각하는 공정으로 이루어진 것을 특징으로 하는 반도체 소자 제조방법.The process of forming a metal filler for conductive plug in a predetermined portion on the first metal wiring comprises: forming a metal film on the first metal wiring and the arbitrary film; and a predetermined portion on the metal film. Forming a photoresist pattern on the substrate; and etching the metal film using the photoresist pattern as a mask. 제 5항에 있어서, 상기 금속막은 W이나 Al-X%Cu로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 5, wherein the metal film is formed of W or Al-X% Cu. 제 6항에 있어서, 상기 Al-X%Cu로는 Al-0.5%Cu이나 Al-1.0%Cu가 사용되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 6, wherein Al-X% Cu is selected from Al-0.5% Cu and Al-1.0% Cu. 제 5항에 있어서, 상기 금속막은 9000 ~ 11000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.6. The method of claim 5, wherein the metal film is formed to a thickness of 9000 to 11000 kPa. 제 1항에 있어서, 상기 금속 필러 사이의 공간에 층간 절연막을 형성하는 공정은, 상기 금속 필러를 포함한 상기 제 1 금속 배선과 상기 임의막 상에 층간 절연막을 형성하는 공정과, 상기 금속 필러의 표면이 노출될 때까지 상기 층간 절연막을 CMP하는 공정으로 이루어진 것을 특징으로 하는 반도체 소자 제조방법.The step of forming an interlayer insulating film in the space between the metal pillars, the step of forming an interlayer insulating film on the first metal wiring including the metal filler and the arbitrary film, and the surface of the metal filler And a step of CMPing said interlayer insulating film until it is exposed. 제 9항에 있어서, 상기 층간 절연막은 "HDP/TEOS"의 적층 구조로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.10. The method of claim 9, wherein the interlayer insulating film is formed in a stacked structure of “HDP / TEOS”. 제 10항에 있어서, 상기 HDP는 6500 ~ 7500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 10, wherein the HDP is formed to a thickness of 6500 ~ 7500 Å. 제 10항에 있어서, 상기 TEOS는 13500 ~ 14500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 10, wherein the TEOS is formed to a thickness of 13500 to 14500 GPa. 제 9항에 있어서, 상기 층간 절연막의 CMP 공정은 상기 층간 절연막이 상기 금속 필러보다 950 ~1050Å 정도 낮은 단차를 가지도록 진행하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 9, wherein the CMP process of the interlayer insulating film is performed such that the interlayer insulating film has a step that is about 950 to 1050 Å lower than that of the metal filler.
KR1019970081580A 1997-12-31 1997-12-31 Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole KR100452315B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970081580A KR100452315B1 (en) 1997-12-31 1997-12-31 Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970081580A KR100452315B1 (en) 1997-12-31 1997-12-31 Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole

Publications (2)

Publication Number Publication Date
KR19990061322A KR19990061322A (en) 1999-07-26
KR100452315B1 true KR100452315B1 (en) 2004-12-17

Family

ID=37372180

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970081580A KR100452315B1 (en) 1997-12-31 1997-12-31 Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole

Country Status (1)

Country Link
KR (1) KR100452315B1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
JPH01278043A (en) * 1988-04-28 1989-11-08 Fujitsu Ltd Manufacture of semiconductor device
JPH01307244A (en) * 1988-06-06 1989-12-12 Seiko Instr Inc Manufacture of semiconductor device
KR930009024A (en) * 1991-10-22 1993-05-22 정몽헌 Contact Forming Method of Semiconductor Device
KR0154804B1 (en) * 1994-09-29 1998-12-01 김광호 Fabrication method of semiconductor device
KR19990003152A (en) * 1997-06-24 1999-01-15 김영환 Manufacturing Method of Semiconductor Device
KR19990061060A (en) * 1997-12-31 1999-07-26 김영환 Contact formation method of semiconductor device
KR100253342B1 (en) * 1997-10-30 2000-04-15 김영환 Metalization method of semiconductor wafer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
JPH01278043A (en) * 1988-04-28 1989-11-08 Fujitsu Ltd Manufacture of semiconductor device
JPH01307244A (en) * 1988-06-06 1989-12-12 Seiko Instr Inc Manufacture of semiconductor device
KR930009024A (en) * 1991-10-22 1993-05-22 정몽헌 Contact Forming Method of Semiconductor Device
KR0154804B1 (en) * 1994-09-29 1998-12-01 김광호 Fabrication method of semiconductor device
KR19990003152A (en) * 1997-06-24 1999-01-15 김영환 Manufacturing Method of Semiconductor Device
KR100253342B1 (en) * 1997-10-30 2000-04-15 김영환 Metalization method of semiconductor wafer
KR19990061060A (en) * 1997-12-31 1999-07-26 김영환 Contact formation method of semiconductor device

Also Published As

Publication number Publication date
KR19990061322A (en) 1999-07-26

Similar Documents

Publication Publication Date Title
US5494853A (en) Method to solve holes in passivation by metal layout
KR100460771B1 (en) Method of fabricating multi-level interconnects by dual damascene process
KR100679822B1 (en) Semiconductor device and manufacturing method thereof
KR100452315B1 (en) Method for fabricating semiconductor device to prevent contact resistance from being increased in via hole
US7112537B2 (en) Method of fabricating interconnection structure of semiconductor device
KR20030058523A (en) Method for forming multi metal layer by dual damascene process
KR20050065744A (en) Metal interconnection structure in semiconductor device and method for manufacturing the same
KR100226727B1 (en) Method for forming multi-metal interconnection layer of semiconductor device
KR100613384B1 (en) Method of forming interconnection line for semiconductor device
KR100588661B1 (en) Structure Of Multi-level Metal Line And Method For Manufacturing The Same
KR100226258B1 (en) Method for forming multiple layer metal wiring in semiconductor device
KR100853800B1 (en) Method of forming dual damascene pattern in a semiconductor device
KR20020086100A (en) a forming method of a contact for multi-level interconnects
KR100398584B1 (en) Method for manufacturing semiconductor device
KR100503381B1 (en) Metal line in a semiconductor and method for forming the same
KR100422912B1 (en) Method for forming contact or via hole of semiconductor devices
JP2005057063A (en) Electronic device and manufacturing method thereof
KR100268810B1 (en) Manufacturing method of metal line of semiconductor device
KR100628222B1 (en) Method for Fabricating Cu Damascene
KR20040050515A (en) Method for forming multi level metal interconnection using self aligned via plug and air gap
KR20000044863A (en) Method for flattening interlayer insulation film in semiconductor device
KR20070055910A (en) Method of forming a via contact structure using a dual damascene technique
KR20010017652A (en) method for fabricating multi-layer metal interconnection of semiconductor device
KR19990084254A (en) Method of forming multilayer wiring of semiconductor device
KR20030002752A (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee