KR100268810B1 - Manufacturing method of metal line of semiconductor device - Google Patents

Manufacturing method of metal line of semiconductor device Download PDF

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KR100268810B1
KR100268810B1 KR1019970081262A KR19970081262A KR100268810B1 KR 100268810 B1 KR100268810 B1 KR 100268810B1 KR 1019970081262 A KR1019970081262 A KR 1019970081262A KR 19970081262 A KR19970081262 A KR 19970081262A KR 100268810 B1 KR100268810 B1 KR 100268810B1
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insulating film
insulation film
forming
tungsten
contact hole
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KR19990061008A (en
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최경근
심규철
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

PURPOSE: A method for forming a metal interconnection line of a semiconductor device is provided to improve the characteristics and the reliability of the device and accordingly to enable a large integration by forming a multi-layered planarization insulation film having a different density formed below the metal interconnection line. CONSTITUTION: The first metal interconnection line(11) is formed on a semiconductor substrate, and the first insulation film(13) of low density is deposited and then planarized by a CMP process. And, the second insulation film(15) of high density is deposited on the first insulation film and then is planarized by a CMP process, and then the third insulation film(17) of low density is deposited. The second insulation film is deposited using an HDP(High Density Plasma) CVD method, and the first and the third insulation film are formed with a SOG(Silicon On Glass) using a spin coater. And, a photo resist pattern is formed on the third insulation film, and a via contact hole is formed by performing an etching process to reveal the first metal interconnection line. And, the first and the second junction layer(23,25) are formed. And, the via contact hole is filled with a tungsten(27) on an upper part of the second junction layer. Then, a contact plug is formed with a tungsten by etching the tungsten and the second and the first junction layer with a CMP process or an etch back process. Then, the second metal interconnection line(29) is formed which is connected with the contact plug tungsten.

Description

반도체소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 고밀도 절연막 상부에 저밀도 절연막을 형성하고 콘택마스크를 이용한 식각공정을 실시함으로써 단차피복비를 향상시켜 보이드의 유발의 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method of forming a metal wiring of a semiconductor device, and in particular, by forming a low density insulating film on the high density insulating film and performing an etching process using a contact mask to improve the step coverage ratio to prevent the occurrence of voids and the characteristics of the semiconductor device accordingly And a technology capable of improving reliability.

일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.

상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착 (Physical Vapor Deposition, 이하에서 PVD라 함) 방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법이 가장 널리 이용되고 있다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low specific resistance and has excellent workability. The method of filling the contact hole and the via hole by sputtering of the method is most widely used.

도 1 내지 도 3은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.

먼저, 소잔분리막, 워드라인, 비트라인, 캐패시터가 형성된 반도체기판(31) 상부에 평탄화절연막(33)을 형성하고, 금속배선 콘택마스크(도시안됨)를 이용한 식각공정으로 콘택홀(35)을 형성한다.First, the planarization insulating layer 33 is formed on the semiconductor substrate 31 on which the small residue separator, the word line, the bit line, and the capacitor are formed, and the contact hole 35 is formed by an etching process using a metal wiring contact mask (not shown). do.

그리고, 상기 콘택홀(35)의 표면에 제1,2접합층(37,39)을 적층하여 형성한다.The first and second bonding layers 37 and 39 are stacked on the contact hole 35.

그 다음에, 상기 콘택홀(35)을 매립하는 콘택플러그용 텅스텐(41)을 증착한다. 이때, 상기 콘택플러그용 텅스텐(41) 증착공정시 상기 콘택홀(35)의 내부에 보이드(43)와 갈라진 틈(45)이 형성된다. (도 1)Then, the contact plug tungsten 41 for filling the contact hole 35 is deposited. At this time, during the deposition process of the contact plug tungsten 41, a void 45 and a gap 45 are formed in the contact hole 35. (Figure 1)

상기 도 2는 상기 도 1의 공정후 평탄화식각공정으로 상기 콘택홀(35)을 매립하는 콘택플러그를 형성한다.FIG. 2 forms a contact plug to bury the contact hole 35 in the planarization etching process of FIG. 1.

이때, 상기 평탄화식각공정시 식각용액이 상기 제1접합층(37)과 평탄화절연막(33)의 계면을 따라 주입되어 상기 콘택홀(35) 하부의 반도체기판(31)에 보이드(43)가 형성된다. (도 2)In this case, during the planarization etching process, an etching solution is injected along the interface between the first bonding layer 37 and the planarization insulating layer 33 to form voids 43 in the semiconductor substrate 31 under the contact hole 35. do. (Figure 2)

상기 도 3은 상기 도 2의 공정후에 반도체기판 상부에 금속배선(47)을 형성한다. 이때, 상기 금속배선(47)은 콘택홀(35)과의 공정마진이 감소됨에따라 금속배선 식각공정시 상기 콘택플러그를 식각하여 상기 콘택플러그가 손상되게 한다.(도 3)3 illustrates a metal wiring 47 formed on the semiconductor substrate after the process of FIG. 2. In this case, the metal wiring 47 etches the contact plug during the metal wiring etching process as the process margin with the contact hole 35 is reduced. The contact plug is damaged (FIG. 3).

상기 도 1 내지 도 3에서 설명한 바와 같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 보이드의 유발, 콘택플러그의 손상 등으로 인하여 소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above with reference to FIGS. 1 to 3, the method of forming a metal wiring of the semiconductor device according to the related art reduces the characteristics and the reliability of the device due to the generation of voids and damage to the contact plug, thereby making it difficult to achieve high integration of the semiconductor device. There is a problem.

본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 금속배선 하부에 형성되는 평탄화절연막을 밀도차를 갖는 다층으로 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by forming a planarization insulating film formed under the metal wiring in a multi-layer having a density difference to improve the characteristics and reliability of the semiconductor device and thereby high integration of the semiconductor device It is an object of the present invention to provide a method for forming metal wiring in a semiconductor device.

도 1 내지 도 3 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 to 3 are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.

도 4 내지 도 9 는 본 발명의 실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.4 to 9 are cross-sectional views illustrating a metal wiring forming method of a semiconductor device in an embodiment of the present invention.

〈 도면의 주요부분에 대한 부호의 설명 〉<Description of reference numerals for the main parts of the drawings>

11 : 제1금속배선 13 : 제1절연막11: first metal wiring 13: first insulating film

15 : 제2절연막 17 : 제3절연막15: second insulating film 17: third insulating film

19 : 감광막패턴 21 : 비아콘택홀19: photoresist pattern 21: via contact hole

23,37 : 제1접합층 25,39 : 제2접합층23,37: first bonding layer 25,39: second bonding layer

27,41 : 텅스텐 29 : 제2금속배선27,41: tungsten 29: second metal wiring

31 : 반도체기판 33 : 평탄화절연막31 semiconductor substrate 33 planarization insulating film

35 : 콘택홀 43 : 보이드35: contact hole 43: void

45 : 갈라진 틈 47 : 금속배선45: crack 47: metal wiring

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은, 반도체기판 상부에 제1절연막을 형성하는 공정과, 상기 제1절연막 상부에 상기 제1절연막보다 고밀도인 제2절연막을 평탄화시켜 형성하는 공정과, 상기 제2절연막 상부에 상기 제2절연막보다 저밀도인 제3절연막을 형성하는 공정과, 상기 제3,2,1절연막을 콘택마스크를 이용하여 식각함으로써 상측이 넓은 콘택홀을 형성하는 공정과, 상기 콘택홀을 매립하는 접합층과 콘택플러그를 형성하는 공정과, 상기 콘택플러그에 접속하는 금속배선을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention includes forming a first insulating film on a semiconductor substrate, and planarizing a second insulating film having a higher density than the first insulating film on the first insulating film. And forming a third insulating film having a lower density than the second insulating film on the second insulating film, and etching the third, second and first insulating films by using a contact mask. And forming a bonding layer and a contact plug to bury the contact hole, and forming a metal wiring connected to the contact plug.

한편, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법의 원리는, 반도체기판 상부에 고밀도 산화막으로 평탄화절연막을 형성하고 그 상부에 저밀도 산화막을 일정두께 형성한 다음, 콘택식각공정으로 콘택홀을 형성하되, 상기 저밀도 산화막이 상기 고밀도 산화막보다 넓게 식각되어 콘택홀의 상측이 넓게 형성되도록 함으로써 후속공정으로 형성되는 콘택플러그 및 금속배선 형성공정시 단차피복비를 향상시키고 그에 따른 보이드의 유발을 방지할 수 있어 반도체소자의 고집적화를 가능하게 하는 것이다.On the other hand, in order to achieve the above object, the principle of the metal wiring formation method of the semiconductor device according to the present invention, forming a planarization insulating film with a high-density oxide film on the semiconductor substrate and a low-density oxide film formed on the predetermined thickness, then contact etching process By forming a contact hole, the low-density oxide film is etched wider than the high-density oxide film so that the upper side of the contact hole is formed wider to improve the step coverage ratio during the process of forming a contact plug and metal wiring formed in a subsequent process, and thereby induce voids It is possible to prevent high integration of semiconductor devices.

이하, 본 발명을 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 4 내지 도 9는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도로서, 제1금속배선 상부에 제2금속배선을 콘택시키는 비아콘택공정을 도시한 것이다.4 through 9 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention, and illustrating a via contact process for contacting a second metal wiring on an upper portion of a first metal wiring.

먼저, 반도체기판(도시안됨) 상부에 제1금속배선(11)을 형성한다. 그리고, 저밀도의 제1절연막(13)을 500∼1500Å정도 증착하고, 상부를 화학기계연마 방법으로 평탄화식각한 다음, 그 상부에 고밀도의 제2절연막(15)을 2000∼20000Å 정도로 증착하고, 상부를 화학기계연마 방법으로 평탄화 식각한 다음, 상기 저밀도의 제3절연막(17)을 500∼2000Å 정도로 형성한다.First, the first metal wiring 11 is formed on the semiconductor substrate (not shown). Then, the low-density first insulating film 13 is deposited by 500 to 1500 kPa, the upper part is planarized by chemical mechanical polishing, and then the high-density second insulating film 15 is deposited on the upper part by 2000 to 20000 mW. After the planarization etching by the chemical mechanical polishing method, the low-density third insulating film 17 is formed to about 500 to 2000 GPa.

이때, 상기 제2절연막(15)은 HDP-CVD (high density plasma CVD) 장비를 이용해 종래의 방법으로 증착한다. 그리고, 상기 제1절연막(13)과 제3절연막(17)은 저밀도막인 에스.오.지 (spin on glass, 이하에서 SOG라 함)를 스핀 코터(spin coater)를 이용하여 형성한다. 여기서, 상기 제3절연막(17)의 두께는 디자인 룰에 따라 달라진다.In this case, the second insulating layer 15 is deposited by a conventional method using high density plasma CVD (HDP-CVD) equipment. In addition, the first insulating layer 13 and the third insulating layer 17 are formed of a low density S. O. paper (spin on glass, hereinafter referred to as SOG) using a spin coater (spin coater). Here, the thickness of the third insulating layer 17 depends on the design rule.

그 다음에, 상기 제3절연막(17) 상부에 비아콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(19)을 형성한다. (도 4, 도 5)Next, the photoresist pattern 19 is formed on the third insulating layer 17 by an exposure and development process using a via contact mask (not shown). (FIG. 4, FIG. 5)

그리고, 상기 감광막패턴(19)을 마스크로하여 상기 제1금속배선(11)이 노출되도록 식각공정을 실시하여 비아콘택홀(21)을 형성한다.The via contact hole 21 is formed by performing an etching process to expose the first metal wiring 11 using the photoresist pattern 19 as a mask.

이때, 상기 제3절연막(17)이 상기 제2절연막(15)보다 저밀도인 관계로 상기 제2절연막(15)보다 넓게 식각한다.(도 6)At this time, since the third insulating layer 17 is lower than the second insulating layer 15, the third insulating layer 17 is etched wider than the second insulating layer 15 (FIG. 6).

그 다음에, 전체표면상부에 제1,2접합층(23,25)을 형성한다. 이때, 상기 제1,2접합층(23,25)은 각각 Ti과 TiN 또는 Ti/TiN의 조합으로 형성된다.Then, first and second bonding layers 23 and 25 are formed on the entire surface. In this case, the first and second bonding layers 23 and 25 are formed of a combination of Ti and TiN or Ti / TiN, respectively.

그리고, 상기 제2접합층(25) 상부에 콘택플러그용 텅스텐(27)으로 상기 비아콘택홀(21)을 매립한다.(도 7)The via contact hole 21 is buried in the tungsten 27 for contact plug on the second bonding layer 25 (FIG. 7).

그 다음에, 상기 콘택플러그용 텅스텐(27)과 상기 제2,1접합층(25,23)을 평탄화식각하여 콘택플러그를 텅스텐으로 형성한다. 이때, 상기 평탄화식각공정은 화학기계연마 방법으로 실시하거나, 에치백공정으로 실시한다.Next, the contact plug tungsten 27 and the second and first bonding layers 25 and 23 are planarized to form a contact plug made of tungsten. In this case, the planarization etching process may be performed by a chemical mechanical polishing method or an etch back process.

그리고, 상기 콘택플러그인 텅스텐(27)과 접속되는 제2금속배선(29)을 형성한다.(도 8, 도 9)Then, a second metal wiring 29 is formed to be connected to the tungsten 27, which is the contact plug. (FIGS. 8 and 9).

본 발명의 다른 실시예는 금속배선이 반도체기판 또는 반도체기판 상부에 구비되는 구조물에 콘택되는 다른 공정에 적용하는 것이다.Another embodiment of the present invention is to apply to other processes in which the metal wiring contacts the semiconductor substrate or a structure provided on the semiconductor substrate.

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 고밀도 절연막 상부에 저밀도 절연막을 적층하고 콘택식각공정을 실시하여 콘택홀 상측이 넓게 형성되어 단차피복비를 향상시키고 그에 따른 보이드의 유발을 방지한다. 그리고, 후속공정인 평탄화식각공정시 접합층과 평탄화절연막 계면을 따라 주입될 수 있는 식각용액의 침투를 방지할 수 있어 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above, in the method of forming metal wirings of the semiconductor device according to the present invention, a low density insulating film is stacked on the high density insulating film and a contact etching process is performed to form a wide contact hole, thereby improving the step coverage ratio and inducing voids. To prevent. In addition, it is possible to prevent the penetration of the etching solution that can be injected along the interface between the bonding layer and the planarization insulating layer during the subsequent planarization etching process, thereby improving the characteristics and reliability of the device and thereby enabling high integration of the semiconductor device. have.

Claims (7)

반도체기판 상부에 제1절연막을 형성하는 공정과, 상기 제1절연막 상부에 상기 제1절연막보다 고밀도인 제2절연막을 평탄화시켜 형성하는 공정과, 상기 제2절연막 상부에 상기 제2절연막보다 저밀도인 제3절연막을 형성하는 공정과, 상기 제3,2,1절연막을 콘택마스크를 이용하여 식각함으로써 상측이 넓은 콘택홀을 형성하는 공정과, 상기 콘택홀을 매립하는 접합층과 콘택플러그를 형성하는 공정과, 상기 콘택플러그에 접속하는 금속배선을 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.Forming a first insulating film over the semiconductor substrate, and planarizing a second insulating film having a higher density than the first insulating film over the first insulating film, and lower density than the second insulating film over the second insulating film. Forming a third insulating film, forming a contact hole having a large upper side by etching the third, second, and first insulating film using a contact mask, and forming a bonding layer and a contact plug to fill the contact hole. And forming a metal wiring connected to said contact plug. 제1항에 있어서, 상기 제1,3절연막은 저유전율을 갖는 저밀도의 SOG로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the first and third insulating layers are formed of low density SOG having a low dielectric constant. 제1항 또는 제2항에 있어서, 상기 제1절연막은 500∼1500Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.3. The method of claim 1 or 2, wherein the first insulating film is formed to a thickness of 500 to 1500 Å. 제1항 또는 제2항에 있어서, 상기 제3절연막은 500∼2000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.3. The method of claim 1 or 2, wherein the third insulating film is formed to a thickness of 500 to 2000 GPa. 제1항에 있어서, 상기 제2절연막은 HDP-CVD (high density plasma CVD) 장비를 이용하여 2000∼20000Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the second insulating layer is formed to a thickness of about 2000 to about 20,000 μs by using high density plasma CVD (HDP-CVD) equipment. 제1항에 있어서, 상기 접합층은 Ti와 TiN 또는 Ti/TiN의 조합으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the bonding layer is formed of a combination of Ti and TiN or Ti / TiN. 제1항에 있어서, 상기 콘택플러그는 텅스텐, 알루미늄 또는 구리 등과 같은 금속으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the contact plug is formed of a metal such as tungsten, aluminum, copper, or the like.
KR1019970081262A 1997-12-31 1997-12-31 Manufacturing method of metal line of semiconductor device KR100268810B1 (en)

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