KR19990061008A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19990061008A KR19990061008A KR1019970081262A KR19970081262A KR19990061008A KR 19990061008 A KR19990061008 A KR 19990061008A KR 1019970081262 A KR1019970081262 A KR 1019970081262A KR 19970081262 A KR19970081262 A KR 19970081262A KR 19990061008 A KR19990061008 A KR 19990061008A
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- insulating film
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- metal wiring
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 33
- 239000002184 metal Substances 0.000 title claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체기판 상부에 저밀도의 제1절연막을 형성하고 상기 제1절연막 상부를 평탄화시키는 고밀도의 제2절연막을 형성한 다음, 상기 제2절연막 상부에 저밀도의 제3절연막을 형성하고 상기 제3,2,1절연막을 콘택마스크를 이용한 식각공정으로 상측이 넓은 콘택홀을 형성한 다음, 상기 콘택홀을 매립하는 접합층과 콘택플러그를 형성하고 상기 콘택플러그에 접속되는 금속배선을 형성하여 단차피복비 저하로 인한 보이드의 유발을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and to form a first insulating film of low density on the semiconductor substrate and to form a high density second insulating film to planarize the upper portion of the first insulating film, and then on the second insulating film A third insulating film having a low density is formed, and the third, second and first insulating films are etched using a contact mask to form contact holes having a wide upper side. Then, a contact layer and a contact plug to fill the contact holes are formed to form a contact plug. By forming a metal wiring connected to the plug to prevent the generation of voids due to the reduction in the step coverage ratio, thereby improving the characteristics and reliability of the semiconductor device, thereby enabling a high integration of the semiconductor device.
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 고밀도 절연막 상부에 저밀도 절연막을 형성하고 콘택마스크를 이용한 식각공정을 실시함으로써 단차피복비를 향상시켜 보이드의 유발의 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method of forming a metal wiring of a semiconductor device, and in particular, by forming a low density insulating film on the high density insulating film and performing an etching process using a contact mask to improve the step coverage ratio to prevent the occurrence of voids and the characteristics of the semiconductor device accordingly And a technology capable of improving reliability.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착 ( Physical Vapor Deposition, 이하에서 PVD 라 함 ) 방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법이 가장 널리 이용되고 있다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. The method of filling the contact hole and the via hole by sputtering of the method is most widely used.
도 1 내지 도 3 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
먼저, 소자분리막, 워드라인, 비트라인, 캐패시터가 형성된 반도체기판(31) 상부에 평탄화절연막(33)을 형성하고, 금속배선 콘택마스크(도시안됨)를 이용한 식각공정으로 콘택홀(35)을 형성한다.First, the planarization insulating layer 33 is formed on the semiconductor substrate 31 on which the device isolation layer, the word line, the bit line, and the capacitor are formed, and the contact hole 35 is formed by an etching process using a metal wiring contact mask (not shown). do.
그리고, 상기 콘택홀(35)의 표면에 제1,2접합층(37,39)을 적층하여 형성한다.The first and second bonding layers 37 and 39 are stacked on the contact hole 35.
그 다음에, 상기 콘택홀(35)을 매립하는 콘택플러그용 텅스텐(41)을 증착한다. 이때, 상기 콘택플러그용 텅스텐(41) 증착공정시 상기 콘택홀(35)의 내부에 보이드(43)와 갈라진 틈(45)이 형성된다. (도 1)Then, the contact plug tungsten 41 for filling the contact hole 35 is deposited. At this time, during the deposition process of the contact plug tungsten 41, a void 45 and a gap 45 are formed in the contact hole 35. (Figure 1)
상기 도 2 는 상기 도 1 의 공정후 평탄화식각공정으로 상기 콘택홀(35)을 매립하는 콘택플러그를 형성한다.FIG. 2 forms a contact plug to bury the contact hole 35 in the planarization etching process of FIG. 1.
이때, 상기 평탄화식각공정시 식각용액이 상기 제1접합층(37)과 평탄화절연막(33)의 계면을 따라 주입되어 상기 콘택홀(35) 하부의 반도체기판(31)에 보이드(43)가 형성된다. (도 2)In this case, during the planarization etching process, an etching solution is injected along the interface between the first bonding layer 37 and the planarization insulating layer 33 to form voids 43 in the semiconductor substrate 31 under the contact hole 35. do. (Figure 2)
상기 도 3 은 상기 도 2 의 공정후에 반도체기판 상부에 금속배선(47)을 형성한다. 이때, 상기 금속배선(47)은 콘택홀(35)과의 공정마진이 감소됨에따라 금속배선 식각공정시 상기 콘택플러그를 식각하여 상기 콘택플러그가 손상되게 한다. (도 3)3 shows the metal wiring 47 formed on the semiconductor substrate after the process shown in FIG. 2. In this case, the metal wire 47 may damage the contact plug by etching the contact plug during the metal wire etching process as the process margin with the contact hole 35 is reduced. (Figure 3)
상기 도 1 내지 도 3 에서 설명한 바와같이 종래기술에 따른 반도체소자의 금소배선 형성방법은, 보이드의 유발, 콘택플러그의 손상 등과 같은 손상으로 인하여 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above with reference to FIGS. 1 to 3, the method of forming a gold wire of the semiconductor device according to the related art improves the characteristics and reliability of the device due to damage such as the generation of voids and damage of contact plugs, and accordingly high integration of the semiconductor device. Has the effect of enabling.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 금속배선 하부에 형성되는 평탄화절연막을 밀도차를 갖는 다층으로 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by forming a planarization insulating film formed under the metal wiring in a multi-layer having a density difference to improve the characteristics and reliability of the semiconductor device and thereby high integration of the semiconductor device It is an object of the present invention to provide a method for forming metal wiring in a semiconductor device.
도 1 내지 도 3 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 to 3 are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
도 4 내지 도 9 는 본 발명의 실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.4 to 9 are cross-sectional views illustrating a metal wiring forming method of a semiconductor device in an embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11 : 제1금속배선 13 : 제1절연막11: first metal wiring 13: first insulating film
15 : 제2절연막 17 : 제3절연막15: second insulating film 17: third insulating film
19 : 감광막패턴 21 : 비아콘택홀19: photoresist pattern 21: via contact hole
23,37 : 제1접합층 25,39 : 제2접합층23,37: first bonding layer 25,39: second bonding layer
27,41 : 텅스텐 29 : 제2금속배선27,41: tungsten 29: second metal wiring
31 : 반도체기판 33 : 평탄화절연막31 semiconductor substrate 33 planarization insulating film
35 : 콘택홀 43 : 보이드35: contact hole 43: void
45 : 갈라진 틈 47 : 금속배선45: crack 47: metal wiring
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
반도체기판 상부에 플로우 및 평탄화 특성이 우수한 제1절연막을 형성하는 공정과,Forming a first insulating film having excellent flow and planarization characteristics on the semiconductor substrate;
상기 제1절연막 상부를 평탄화시키는 고밀도의 제2절연막을 형성하는 공정과,Forming a high density second insulating film for planarizing an upper portion of the first insulating film;
상기 제2절연막 상부에 저밀도의 제3절연막을 형성하는 공정과,Forming a third insulating film having a low density on the second insulating film;
상기 제3,2,1절연막을 콘택마스크를 이용한 식각공정으로 상측이 넓은 콘택홀을 형성하는 공정과,Forming a contact hole having a wide upper side by etching the third, second and first insulating layers using a contact mask;
상기 콘택홀을 매립하는 접합층과 콘택플러그를 형성하는 공정과,Forming a contact layer and a contact plug to bury the contact hole;
상기 콘택플러그에 접속되는 금속배선을 형성하는 공정을 포함하는 것을 특징으로한다.And forming a metal wiring connected to the contact plug.
한편, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법의 원리는,On the other hand, in order to achieve the above object, the principle of the metal wiring forming method of the semiconductor device according to the present invention,
반도체기판 상부에 고밀도 산화막으로 평탄화절연막을 형성하고 그 상부에 저밀도 산화막을 일정두께 형성한 다음, 콘택식각공정으로 콘택홀을 형성하되, 상기 저밀도 산화막이 상기 고밀도 산화막보다 넓게 식각되어 콘택홀의 상측이 넓게 형성되도록 함으로써 후속공정으로 형성되는 콘택플러그 및 금속배선 형성공정시 단차피복비를 향상시키고 그에 따른 보이드의 유발을 방지할 수 있어 반도체소자의 고집적화를 가능하게 하는 것이다.A planarization insulating film is formed on the semiconductor substrate with a high density oxide film, and a low density oxide film is formed on the semiconductor substrate, and a contact hole is formed by a contact etching process. It is possible to improve the step coverage ratio and prevent the occurrence of voids in the contact plug and metal wiring forming process formed in a subsequent process to enable high integration of the semiconductor device.
이하, 본 발명을 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 9 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도로서, 제1금속배선 상부에 제2금속배선을 콘택시키는 비아콘택공정을 도시한 것이다.4 through 9 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention, and illustrating a via contact process for contacting a second metal wiring on an upper portion of a first metal wiring.
먼저, 반도체기판(도시안됨) 상부에 제1금속배선(11)을 형성한다. 그리고, 저밀도의 제1절연막(13)을 500 ∼ 1500 Å 정도 증착하고, 상부를 화학기계연마 방법으로 평탄화식각한 다음, 그 상부에 고밀도의 제2절연막(15)을 2000 ∼ 20000 Å 정도로 증착하고, 상부를 화학기계연마 방법으로 평탄화 식각한 다음, 상기 저밀도의 제3절연막(17)을 500 ∼ 2000 Å 정도로 형성한다.First, the first metal wiring 11 is formed on the semiconductor substrate (not shown). Then, the low-density first insulating film 13 is deposited at about 500-1500 kPa, the upper part is flattened and etched by chemical mechanical polishing, and then the high-density second insulating film 15 is deposited at about 2000-20000 kPa. After the top is planarized and etched by chemical mechanical polishing, the third insulating film 17 having a low density is formed to about 500 to 2000 GPa.
이때, 상기 제2절연막(15)은 HDP-CVD ( high density plasma CVD ) 장비를 이용해 종래의 방법으로 증착한다. 그리고, 상기 제1절연막(13)과 제3절연막(17)은 저밀도막인 에스.오.지. ( spin on glass, 이하에서 SOG 라 함 ) 를 스핀 코터 ( spin coater ) 를 이용하여 형성한다. 여기서, 상기 제3절연막(17)의 두께는 디자인 룰에 따라 달라진다.In this case, the second insulating layer 15 is deposited by a conventional method using high density plasma CVD (HDP-CVD) equipment. The first insulating layer 13 and the third insulating layer 17 are low density films. (spin on glass, hereinafter referred to as SOG) is formed using a spin coater. Here, the thickness of the third insulating layer 17 depends on the design rule.
그 다음에, 상기 제3절연막(17) 상부에 비아콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(19)을 형성한다. (도 4, 도 5)Next, the photoresist pattern 19 is formed on the third insulating layer 17 by an exposure and development process using a via contact mask (not shown). (FIG. 4, FIG. 5)
그리고, 상기 감광막패턴(19)을 마스크로하여 상기 제1금속배선(11)이 노출되도록 식각공정을 실시하여 비아콘택홀(21)을 형성한다.The via contact hole 21 is formed by performing an etching process to expose the first metal wiring 11 using the photoresist pattern 19 as a mask.
이때, 상기 제3절연막(17)이 상기 제2절연막(15)보다 저밀도인 관계로 상기 제2절연막(15)보다 넓게 식각된다. (도 6)In this case, since the third insulating layer 17 is lower than the second insulating layer 15, the third insulating layer 17 is etched wider than the second insulating layer 15. (Figure 6)
그 다음에, 전체표면상부에 제1,2접합층(23,25)을 형성한다. 이때, 상기 제1,2접합층(23,25)은 각각 Ti 과 TiN 또는 Ti/TiN 의 조합으로 형성된다.Then, first and second bonding layers 23 and 25 are formed on the entire surface. In this case, the first and second bonding layers 23 and 25 are formed of a combination of Ti and TiN or Ti / TiN, respectively.
그리고, 상기 제2접합층(25) 상부에 콘택플러그용 텅스텐(27)으로 상기 비아콘택홀(21)을 매립한다. (도 7)The via contact hole 21 is buried in the tungsten 27 for contact plug on the second bonding layer 25. (Figure 7)
그 다음에, 상기 콘택플러그용 텅스텐(27)과 상기 제2,1접합층(25,23)을 평탄화식각하여 콘택플러그를 텅스텐으로 형성한다. 이때, 상기 평탄화식각공정은 화학기계연마 방법으로 실시하거나, 에치백공정으로 실시한다.Next, the contact plug tungsten 27 and the second and first bonding layers 25 and 23 are planarized to form a contact plug made of tungsten. In this case, the planarization etching process may be performed by a chemical mechanical polishing method or an etch back process.
그리고, 상기 콘택플러그인 텅스텐(27)과 접속되는 제2금속배선(29)을 형성한다. (도 8, 도 9)A second metal wiring 29 is formed to be connected to the tungsten 27 which is the contact plug. (Fig. 8, Fig. 9)
본 발명의 다른 실시예는 금속배선이 반도체기판 또는 반도체기판 상부의 구조물에 콘택되는 공정에 적용하는 것이다.Another embodiment of the present invention is applied to a process in which a metal wiring is contacted with a semiconductor substrate or a structure on the semiconductor substrate.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 고밀도 절연막 상부에 저밀도 절연막을 적층하고 콘택식각공정을 실시하여 콘택홀 상측이 넓게 형성되어 단차피복비를 향상시키고 그에 따른 보이드의 유발을 방지한다. 그리고, 후속공정인 평탄화식각공정시 접합층과 평탄화절연막 계면을 따라 주입될 수 있는 식각용액의 침투를 방지할 수 있어 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above, in the method of forming metal wirings of the semiconductor device according to the present invention, a low density insulating film is stacked on the high density insulating film and a contact etching process is performed to form a wide contact hole, thereby improving the step coverage ratio and inducing voids. To prevent. In addition, it is possible to prevent the penetration of the etching solution that can be injected along the interface between the bonding layer and the planarization insulating layer during the subsequent planarization etching process, thereby improving the characteristics and reliability of the device and thereby enabling high integration of the semiconductor device. have.
Claims (7)
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