KR100546208B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and forms a dual damascene pattern in the core region and the pad region, and fills the dual damascene pattern of the pad region having a wide line width when the dual damascene pattern is filled with copper by plating. The copper is lower than the upper end of the dual damascene pattern so that the groove is formed, and the copper diffusion preventing conductive film and the metal oxide layer are formed on the copper layer, and then the copper wiring is formed by the polishing process. Since the upper part of the wiring is covered with a metal oxide layer, a pad layer made of copper wiring and a metal oxide layer is formed at the same time, so that a separate pad layer is used to prevent oxidation of the copper wiring surface due to exposure of the copper wiring in the existing pad area. The deposition process, the mask process and the etching process can be omitted, resulting in improved productivity and cost savings due to the simplified process.

Copper wiring, pads, dual damascene

Description

Method of manufacturing in semiconductor device             

1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional semiconductor device.

2A to 2D are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

11, 41: substrate 12, 42: lower wiring

13, 43: copper diffusion preventing insulating film 14, 44: interlayer insulating film for via hole

15, 45: trench etch stop films 16, 46: trench interlayer insulating film

17, 47: dual damascene pattern 18, 48: first copper diffusion preventing conductive film

19, 49: copper seed layer 50: copper layer

21 and 51: second copper diffusion preventing conductive film 52: metal oxide layer

23, 53: passivation layer 200, 500: copper wiring

220, 520: pad layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, after a final copper wiring is formed by a dual damascene process, a separate pad layer forming process is omitted, thereby simplifying the process. It relates to a manufacturing method.

In general, as the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of devices continues to shrink into the sub-half-micron area, while improving performance and reliability. In terms of circuit density, circuit density is increasing. In response to these demands, copper has a higher melting point than aluminum in forming metal wirings of semiconductor devices, and thus has high resistance to electro-migration (EM), thereby improving reliability of the device and having low specific resistance. The speed of signal transmission can be increased, making it a useful interconnection material for integration circuits.

Currently available copper embedding methods include physical vapor deposition (PVD) method / reflow, chemical vapor deposition (CVD), electroplating method, electroless-plating method, etc. Among these, the preferred method is a plating method with relatively good copper embedding characteristics.

While adopting copper as a material for the metal wiring, a damascene technique for simultaneously forming a via contact hole and a trench in which the metal wiring is located for electrically connecting the lower layer to the copper wiring forming process of the semiconductor device is widely applied.

In order to form a copper wiring in the damascene pattern made of the via contact hole and the trench, the copper layer is buried by the chemical mechanical polishing (CMP) process after embedding the copper in the damascene pattern by various methods described above. Isolate with.

1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional semiconductor device. A substrate 11 having a lower wiring 12 is provided, and a copper diffusion preventing insulating layer 13 formed on the substrate 11 including the lower wiring 12, an interlayer insulating layer 14 for via holes, and a trench etch stop. The dual damascene pattern 17 is formed by applying the dual damascene process to the film 15 and the interlayer insulating layer 16 for the trench. The dual damascene pattern 17 is formed in the core region and the pad region, and the line width of the dual damascene pattern 17 of the pad region is the line width of the dual damascene pattern 17 of the core region. Is formed larger. The first copper diffusion preventing conductive film 18 and the copper seed layer 19 are formed on the entire structure including the dual damascene pattern 17, and the copper layer is completely embedded in the dual damascene pattern 17 by plating. After forming, the copper wiring 200 is formed in the dual damascene pattern 17 of the core region and the pad region by a chemical mechanical polishing (CMP) process. Subsequently, a passivation layer 23 having a single layer or a multilayer structure is formed, and the passivation layer 23 of the pad region is etched by using a pad mask process and an etching process to expose a part of the copper wiring 200 of the pad region. On the passivation layer 23 including the exposed copper wiring 200, a second copper diffusion preventing conductive film 21 and a metal oxide layer such as aluminum are formed, and the metal oxide layer and the second copper layer are formed by a mask process and an etching process. The diffusion barrier conductive layer 21 is patterned to form a pad layer 220 electrically connected to the copper wiring 200 in the pad region.

In the above-described conventional method, the copper wiring 200 is formed by a chemical mechanical polishing process, in which a probe is applied to a pad due to surface oxidation of the copper wiring due to the exposure of the copper wiring 200. Problems arise in the probing process for plugging in and checking the electrical properties and in the bonding process for connecting with external devices. That is, if the probing process is performed in a state where the surface of the copper wiring 200 is oxidized, accurate electrical characteristics cannot be examined, and if the bonding process is performed, there is a problem such as a poor contact, thereby degrading the reliability of the device. . In order to solve this problem, the passivation layer 23 of the pad region is etched by a pad mask process and an etching process to expose a portion of the copper wiring 200 of the pad region, and then separately deposited on the exposed copper wiring 200. The pad layer 220 may be formed by performing a process, a mask process, and an etching process.

Therefore, since the present invention finally forms a copper wiring in a dual damascene process, a separate pad layer forming process is omitted, and thus a method of manufacturing a semiconductor device capable of simplifying the process, improving productivity, and reducing costs can be achieved. The purpose is to provide.

A method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object comprises the steps of forming a dual damascene pattern in the core region and the pad region by etching a portion of the interlayer insulating film; The dual damascene pattern of the core region is sufficiently buried and the dual damascene pattern of the pad region forms a copper layer having a lower groove than the top of the dual damascene pattern; Forming a copper diffusion preventing conductive film and a metal oxide layer on the copper layer; Forming a copper wiring in the dual damascene pattern of the core region and the pad region by a polishing process, and forming a pad layer on the copper wiring of the pad region by leaving a metal oxide layer in the groove; Forming a passivation layer on top of the entire structure including a copper wiring and a pad layer; And etching the passivation layer of the pad region to expose the pad layer.

In the above, the line width of the dual damascene pattern of the pad region is wider than the line width of the dual damascene pattern of the core region, the copper layer is formed by the plating method, the metal oxide layer is formed of aluminum.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2A through 2D are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, in which a copper wiring is formed and applied by a damascene process.

Referring to FIG. 2A, a multilayer insulating film for performing a dual damascene process on the substrate 41 on which the lower wiring 42 is formed, for example, a copper diffusion preventing insulating film 43, an interlayer insulating film 44 for via holes, The trench etch stop layer 45 and the trench interlayer insulating layer 46 are stacked to form a dual damascene pattern 47 formed of via holes and trenches by a dual damascene process in the multilayer insulating layer. The dual damascene pattern 47 is formed in the core region and the pad region, and the line width of the dual damascene pattern 47 of the pad region is the line width of the dual damascene pattern 47 of the core region. It is formed more widely.

In the above, the copper diffusion preventing insulating layer 43 and the trench etch stop layer 45 are formed of SiC or SiN. The interlayer insulating film 44 for the via hole and the interlayer insulating film 46 for the trench are formed of a low dielectric oxide having a dielectric constant of about 1.5 to 4.0.

Referring to FIG. 2B, a first copper diffusion preventing conductive film 48 and a copper seed layer 49 are formed along the upper surface of the entire structure including the dual damascene pattern 47. A copper layer 50 is formed by embedding the dual damascene pattern 47 by copper plating, but when the copper is filled by the plating method, the dual damascene pattern 47 is formed on the dual damascene pattern 47 having a wide line width. The copper to be filled is lower than the upper end of the dual damascene pattern 47 so that grooves are formed, and the dual damascene pattern 47 of the core area having a small line width is sufficiently filled. As a result, the copper layer 50 is formed by filling the dual damascene pattern 47 of the core region with a sufficient amount of copper, and filling the dual damascene pattern 47 of the pad region with less copper and having a groove on the top. The depth and width of the groove can be formed to a desired depth and width by adjusting the conditions of the copper plating method. The second copper diffusion preventing conductive film 51 and the metal oxide-resistant layer 52 are sequentially formed on the copper layer 50.

In the above, the first and second copper diffusion preventing conductive films 48 and 51 are formed of Ta or TaN / Ta. The metal oxide layer 52 is preferably formed of a metal having excellent conductivity such as aluminum.

Referring to FIG. 2C, the chemical mechanical polishing process is performed until the surface of the trench interlayer insulating layer 46 is exposed to form the copper wiring 500 in the dual damascene pattern 47 of the core region and the pad region. At this time, the second copper diffusion preventing conductive film 51 and the metal oxide-resistant layer 52 remain in the grooves on the copper wiring 500 formed in the dual damascene pattern 47 of the pad region. A pad layer 520 of 52 is formed. That is, only the copper wiring 500 is formed in the core region, and in the pad region, the copper wiring 500, the second copper diffusion preventing conductive film 51, and the metal oxide-resistant layer 52 are stacked.

Referring to FIG. 2D, a passivation layer 53 having a single layer or a multilayer structure is formed on the entire structure including the copper wiring 500 and the pad layer 520, and the passivation layer of the pad region may be formed by a pad mask process and an etching process. 53 is etched to expose the pad layer 520 formed on the copper wiring 500 in the pad region. Thereafter, the pad layer 520 is subjected to a probing process, a bonding process, and the like which are common processes. Probing and bonding are performed on the pad layer 520 during the probing process and the bonding process.

As described above, in the present invention, when the copper is filled with the dual damascene pattern by the plating method, the copper filled in the dual damascene pattern of the wide pad area is lower than the upper end of the dual damascene pattern so that the groove is formed. A copper diffusion preventing conductive film and a metal oxide-resistant layer are formed on the copper layer, and then copper wiring is formed by a polishing process. The upper copper wiring of the pad region is covered with a metal oxide-resistant layer so that the copper wiring and the oxidation resistant layer are formed. Since a pad layer made of a metal layer is formed at the same time, a separate pad layer deposition process, a mask process and an etching process can be omitted in order to prevent oxidation of the copper wiring surface due to the exposure of the copper wiring in the existing pad region. Improvements and cost savings can be achieved.

Claims (4)

Etching a portion of the interlayer insulating film to form a dual damascene pattern in the core region and the pad region; Forming a copper layer in which the dual damascene pattern of the core region is sufficiently embedded and the dual damascene pattern of the pad region has a groove lower than an upper end of the dual damascene pattern; Forming a copper diffusion preventing conductive film and a metal oxide layer on the copper layer; A polishing process is performed such that the copper layer of the core region and the metal oxide layer of the pad region are simultaneously exposed to form a copper wiring made of the copper layer in the core region, and at the same time, the copper layer and the copper diffusion preventing conductivity in the pad region. Forming a pad layer comprising a film and a metal oxide layer; Forming a passivation layer on the entire structure including the copper wiring and the pad layer; And Etching the passivation layer of the pad region to expose the pad layer. The method of claim 1, The line width of the dual damascene pattern of the pad region is larger than the line width of the dual damascene pattern of the core region. The method of claim 1, The copper layer is formed by a plating method. The method of claim 1, The metal oxide layer is a method of manufacturing a semiconductor device formed of aluminum.

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