KR20030051040A - Method of forming a barrier metal layer in a semiconductor device - Google Patents
Method of forming a barrier metal layer in a semiconductor device Download PDFInfo
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- KR20030051040A KR20030051040A KR1020010081938A KR20010081938A KR20030051040A KR 20030051040 A KR20030051040 A KR 20030051040A KR 1020010081938 A KR1020010081938 A KR 1020010081938A KR 20010081938 A KR20010081938 A KR 20010081938A KR 20030051040 A KR20030051040 A KR 20030051040A
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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Abstract
Description
본 발명은 반도체 소자의 금속 확산 방지막 형성 방법에 관한 것으로, 특히 금속 확산 방지막 상부에 형성되는 금속층에 리프팅(Lifting) 현상이 발생되는 것을 방지하고, 금속 확산 방지막으로 인하여 금속 배선이나 플러그의 접촉 저항이 증가되는 것을 방지할 수 있는 반도체 소자의 금속 확산 방지막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal diffusion barrier of a semiconductor device. In particular, a lifting phenomenon is prevented from occurring in a metal layer formed on the metal diffusion barrier, and a contact resistance of a metal wire or a plug is increased due to the metal diffusion barrier. The present invention relates to a method for forming a metal diffusion barrier of a semiconductor device that can be prevented from increasing.
반도체 소자가 고집적화 되어감에 따라, 금속 배선을 다층으로 형성하면서, 금속 배선이나 플러그의 저항을 줄이기 위하여 많은 연구가 이루어지고 있다.As semiconductor devices have been highly integrated, many studies have been conducted to reduce the resistance of metal wires and plugs while forming metal wires in multiple layers.
금속 배선을 다층으로 형성할 경우 층층 마다의 금속 배선에 의해 단차가 발생되고, 이러한 단차는 후속 공정의 어려움을 유발한다.When the metal wiring is formed in multiple layers, a step is generated by the metal wiring for each layer layer, and this step causes a difficulty in subsequent processes.
따라서, 금속 배선을 형성하면서 단차가 발생되는 것을 방지하기 위하여, 층간 절연막에 라인 형태로 홈을 만들고, 홈에다 전도성 물질을 매립하여 금속 배선을 형성한다. 이러한 홈을 트렌치라 한다.Therefore, in order to prevent the generation of the step while forming the metal wiring, grooves are formed in the form of lines in the interlayer insulating film, and the metal wiring is formed by filling the groove with a conductive material. This groove is called a trench.
한편, 트렌치에 형성된 금속 배선과 하부 요소를 전기적으로 연결시키기 위하여 트렌치의 소정 영역에 홀을 형성하고, 홀에 전도성 물질이 매립하여 금속 배선과 하부 요소를 전기적으로 연결시킨다. 이러한 홀을 콘택홀 또는 비아홀이라 한다.Meanwhile, a hole is formed in a predetermined region of the trench to electrically connect the metal wiring and the lower element formed in the trench, and a conductive material is embedded in the hole to electrically connect the metal wiring and the lower element. Such holes are called contact holes or via holes.
상기와 같이, 층간 절연막에는 트렌치와 콘택홀이 형성되는데, 이를 합쳐서 듀얼 다마신 패턴이라 한다. 결국, 층간 절연막에 듀얼 다마신 패턴이 형성되고, 듀얼 다마신 패턴에 전도성 물질을 매립하여 콘택 플러그와 금속 배선을 동시에 형성한다. 여기서, 전도성 물질이 층간 절연막과 집적 접촉하게 되면, 전도성 물질이 후속 공정에 의해 층간 절연막과 반응하여 산화되거나, 전도성 물질이 층간 절연막으로 확산되어 소자의 전기적 특성을 저하키는 문제점이 발생된다.As described above, trenches and contact holes are formed in the interlayer insulating film, which are collectively referred to as a dual damascene pattern. As a result, a dual damascene pattern is formed on the interlayer insulating film, and a conductive material is embedded in the dual damascene pattern to simultaneously form a contact plug and a metal wiring. Here, when the conductive material is in contact with the interlayer insulating film, the conductive material reacts with the interlayer insulating film and oxidizes by a subsequent process, or the conductive material is diffused into the interlayer insulating film, thereby degrading the electrical characteristics of the device.
이를 방지하기 위하여, 층간 절연막에 듀얼 다마신 패턴을 형성한 후 듀얼 다마신 패턴의 측벽 및 저면에 금속 확산 방지막을 형성한다.In order to prevent this, the dual damascene pattern is formed on the interlayer insulating film, and then a metal diffusion barrier is formed on the sidewall and the bottom of the dual damascene pattern.
이하, 종래 기술에 따른 반도체 소자의 금속 확산 방지막 형성 방법을 설명하기로 한다.Hereinafter, a method of forming a metal diffusion barrier film of a semiconductor device according to the prior art will be described.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 금속 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of a device for explaining a metal diffusion barrier film formation method of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11) 상에 절연막 확산 방지막(Dielectric Barrier layer; 12), 제 1 절연막(13), 식각 방지막(14), 제 2 절연막(15) 및 캡핑층(Capping layer; 16)을 순차적으로 형성한다.Referring to FIG. 1A, an insulating barrier layer 12, a first insulating layer 13, an etch barrier 14, and a second insulating layer are formed on a semiconductor substrate 11 on which various elements for forming a semiconductor device are formed. 15 and a capping layer 16 are sequentially formed.
도 1b를 참조하면, 트렌치 마스크를 이용한 식각 공정으로 캡핑층(16) 및 제 2 절연막(15)을 식각하여 소정 영역에 트렌치(17)를 형성한다. 트렌치(17)의 저면에는 식각 정지층(14)이 노출되고, 제 1 절연막(13)은 식각 정지층(14)에 의해 식각되지 않는다.Referring to FIG. 1B, the capping layer 16 and the second insulating layer 15 are etched by an etching process using a trench mask to form a trench 17 in a predetermined region. The etch stop layer 14 is exposed on the bottom of the trench 17, and the first insulating layer 13 is not etched by the etch stop layer 14.
도 1c를 참조하면, 식각 정지층(14)의 소정 영역을 식각한 후 노출된 제 1 절연막(13)을 식각하여 콘택홀(18)을 형성한다. 콘택홀(18)을 통해 반도체 기판(11)의 접합 영역(도시되지 않음)이 노출된다. 이로써, 트렌치(17)와 콘택홀(18)로 이루어진 듀얼 다마신 패턴(19)이 형성된다.Referring to FIG. 1C, after the predetermined region of the etch stop layer 14 is etched, the exposed first insulating layer 13 is etched to form the contact hole 18. A junction region (not shown) of the semiconductor substrate 11 is exposed through the contact hole 18. As a result, a dual damascene pattern 19 including the trench 17 and the contact hole 18 is formed.
도 1d를 참조하면, 듀얼 다마신 패턴(19)을 포함한 전체 상부에 금속 확산 방지막(20)을 형성한다. 금속 확산 방지막(20)은 Ta 또는 TaN으로 형성한다.Referring to FIG. 1D, the metal diffusion barrier layer 20 is formed on the entire top including the dual damascene pattern 19. The metal diffusion barrier 20 is made of Ta or TaN.
도 1e를 참조하면, 듀얼 다마신 패턴(19)이 충분히 매립되도록 전체 상부에 전도성 물질층을 형성한 후 캡핑층(16) 상부의 전도성 물질층 및 금속 확산 방지막(20)을 제거하여 듀얼 다마신 패턴에만 전도성 물질층 및 금속 확산 방지막(20)을 잔류시킨다. 이로써, 콘택홀에는 전도성 물질층으로 이루어진 콘택 플러그(21)가 형성되고, 동시에 트렌치에는 금속 배선(22)이 형성된다.Referring to FIG. 1E, the conductive material layer is formed on the entire upper portion so that the dual damascene pattern 19 is sufficiently embedded, and then the dual damascene is removed by removing the conductive material layer and the metal diffusion barrier layer 20 on the capping layer 16. The conductive material layer and the metal diffusion barrier 20 are left only in the pattern. As a result, a contact plug 21 made of a conductive material layer is formed in the contact hole, and a metal wiring 22 is formed in the trench.
상기에서, 전도성 물질층은 알루미늄, 구리, 텅스텐 등을 포함하는 금속 물질로 형성한다. 이 중에서도, 알루미늄을 이용하여 금속 배선을 형성하는 공정에서 일렉트로마이그레이션(Electromigration)이나 상호 간섭(Cross talk)이 발생되는 문제점을 해결하기 위하여, 최근에는 구리를 이용하여 금속 배선(22)을 형성한다.In the above, the conductive material layer is formed of a metal material including aluminum, copper, tungsten and the like. Among these, in order to solve the problem that electromigration or cross talk occurs in the process of forming metal wiring using aluminum, metal wiring 22 is recently formed using copper.
도 1f를 참조하면, 후속 공정으로 열공정이 실시될 경우 금속 확산 방지막(20)은 콘택 플러그(21), 특히 구리로 이루어진 콘택 플러그(21)와의 접착력이 좋지 못하므로, 콘택 플러그(21)의 하부가 들뜨는 리프팅(Lifting) 현상을 유발한다. 이로 인하여, 콘택 플러그(21)의 하부에는 보이드(23)가 발생된다.Referring to FIG. 1F, when the thermal process is performed in a subsequent process, the metal diffusion barrier 20 may not have good adhesion with the contact plug 21, particularly, the copper contact plug 21, and thus, the lower portion of the contact plug 21. This causes a lifting phenomenon. For this reason, the void 23 is generated in the lower part of the contact plug 21.
보이드(23)는 콘택 저항을 증가시켜 소자의 전기적 특성을 저하시킬 뿐만 아니라, 심한 경우에는 불량이 발생될 수 있다.The voids 23 not only lower the electrical characteristics of the device by increasing the contact resistance, but also may cause defects in severe cases.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 트렌치와 콘택홀로 이루어진 듀얼 다마신 패턴을 형성하고, 비정질 구조를 가지며 확산 방지 특성이 우수한 금속 산화 절연물층을 층덮힘이 우수한 원자층 증착법으로 형성한 후 에치 백 공정을 실시하여 금속 산화 절연물층으로 이루어진 금속 확산 방지막을 트렌치 및 콘택홀의 측벽에만 형성함으로써, 콘택 플러그의 하부가 들뜨는 리프팅 현상에 의하여 콘택 플러그의 하부에 보이드가 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 금속 확산 방지막 형성 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention forms a dual damascene pattern consisting of trenches and contact holes, and has an amorphous structure and a metal oxide insulating layer having excellent diffusion prevention characteristics by forming an atomic layer deposition method with excellent layer covering. By performing an etch back process to form a metal diffusion barrier layer formed of a metal oxide insulating layer only on the sidewalls of the trench and the contact hole, the process prevents voids from occurring in the lower portion of the contact plug due to the lifting phenomenon in which the lower portion of the contact plug is lifted. And to provide a method for forming a metal diffusion barrier film of a semiconductor device capable of improving the electrical characteristics of the device.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 금속 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method for forming a metal diffusion barrier film of a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 금속 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도.2A to 2F are cross-sectional views of devices for explaining a method for forming a metal diffusion barrier film of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 31 : 반도체 기판12, 32 : 절연막 확산 방지층11 and 31: semiconductor substrate 12 and 32: insulating film diffusion prevention layer
13, 33 : 제 1 절연막14, 34 : 식각 방지막13, 33: first insulating film 14, 34: etching prevention film
15, 35 : 제 2 절연막16, 36 : 캡핑층15, 35: second insulating film 16, 36: capping layer
17, 37 : 트렌치18, 38 : 콘택홀17, 37: trench 18, 38: contact hole
19, 39 : 듀얼 다마신 패턴20, 40 : 금속 확산 방지막19, 39: dual damascene pattern 20, 40: metal diffusion barrier
40a : 금속 산화 절연물층21, 41 : 콘택 플러그40a: metal oxide insulating layer 21, 41: contact plug
22, 42 : 금속 배선23 : 보이드22, 42: metal wiring 23: void
본 발명에 따른 반도체 소자의 금속 확산 방지막 형성 방법은 금속 배선과 층간 절연막이 접하는 부분에서 금속 배선의 금속 성분이 산화막으로 확산되는 것을 방지하며, 층간 절연막에 의해 금속 배선이 산화되는 것을 방지하기 위하여 금속 배선 및 층간 절연막의 계면에 금속 확산 방지막을 형성하는 방법으로써, 금속 확산 빙지막은 금속 산화 절연물층으로 형성되는 것을 특징으로 한다.The method for forming a metal diffusion barrier film of a semiconductor device according to the present invention is to prevent the metal component of the metal wiring diffusion into the oxide film in the portion where the metal wiring and the interlayer insulating film contact, and to prevent the metal wiring from being oxidized by the interlayer insulating film A method of forming a metal diffusion barrier film at an interface between a wiring and an interlayer insulating film, wherein the metal diffusion ice film is formed of a metal oxide insulator layer.
본 발명의 다른 실시예에 따른 반도체 소자의 금속 확산 방지막 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 제 1 절연막,식각 방지막 및 제 2 절연막을 순차적으로 형성한 후 제 2 절연막에는 트렌치를 형성하고, 제 1 절연막에는 콘택홀을 형성하는 단계와, 전체 상부에 금속 산화 절연물층을 형성하는 단계와, 에치 백 공정으로 금속 산화 절연물층을 트렌치 및 콘택홀의 측벽에만 잔류시키는 단계와, 트렌치 및 콘택홀에 전도성 물질을 매립하여 금속 배선 및 콘택 플러그를 형성하는 단계로 이루어지는 것을 특징으로 한다.According to another exemplary embodiment of the present invention, a method for forming a metal diffusion barrier layer of a semiconductor device may be performed by sequentially forming a first insulating film, an etching prevention film, and a second insulating film on a semiconductor substrate on which various elements for forming a semiconductor device are formed. Forming a trench in the first insulating film, forming a contact hole in the first insulating film, forming a metal oxide insulator layer over the entire upper surface, and leaving the metal oxide insulator layer only on the sidewalls of the trench and the contact hole by an etch back process; And embedding a conductive material in trenches and contact holes to form metal wires and contact plugs.
금속 산화 절연물층은 비정질 구조로 형성되며, Al2O3, ZrO2, HfO2및 Ta2O5중 어느 하나로 형성된다. 이때, 금속 산화 절연물층은 원자층 증착법으로 형성한다.The metal oxide insulator layer is formed in an amorphous structure, and formed of any one of Al 2 O 3 , ZrO 2 , HfO 2, and Ta 2 O 5 . At this time, the metal oxide insulating layer is formed by atomic layer deposition.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 보다 더 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 금속 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2F are cross-sectional views of devices for explaining a method for forming a metal diffusion barrier film of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(31) 상에 절연막 확산 방지막(32), 제 1 절연막(33), 식각 방지막(34), 제 2 절연막(35) 및 캡핑층(36)을 순차적으로 형성한다.Referring to FIG. 2A, an insulating film diffusion barrier layer 32, a first insulating layer 33, an etch barrier layer 34, a second insulating layer 35, and a semiconductor layer 31 are formed on a semiconductor substrate 31 on which various elements for forming a semiconductor element are formed. The capping layer 36 is formed sequentially.
상기에서, 확산 방지막(32), 식각 방지막(34) 및 캡핑층(36)은 Si-N 계열의 화합물로 형성한다.In the above, the diffusion barrier 32, the etch barrier 34 and the capping layer 36 is formed of a Si-N-based compound.
도 2b를 참조하면, 트렌치 마스크를 이용한 식각 공정으로 캡핑층(36) 및 제2 절연막(35)을 식각하여 소정 영역에 트렌치(37)를 형성한다. 트렌치(37)의 저면에는 식각 정지층(34)이 노출되고, 제 1 절연막(33)은 식각 정지층(34)에 의해 식각되지 않는다.Referring to FIG. 2B, a trench 37 is formed in a predetermined region by etching the capping layer 36 and the second insulating layer 35 by an etching process using a trench mask. The etch stop layer 34 is exposed on the bottom of the trench 37, and the first insulating layer 33 is not etched by the etch stop layer 34.
도 2c를 참조하면, 식각 정지층(34)의 소정 영역을 식각한 후 노출된 제 1 절연막(33)을 식각하여 콘택홀(38)을 형성한다. 콘택홀(38)을 통해 반도체 기판(31)의 접합 영역(도시되지 않음)이 노출된다. 이로써, 트렌치(37)와 콘택홀(38)로 이루어진 듀얼 다마신 패턴(39)이 형성된다.Referring to FIG. 2C, after the predetermined region of the etch stop layer 34 is etched, the exposed first insulating layer 33 is etched to form the contact hole 38. The junction region (not shown) of the semiconductor substrate 31 is exposed through the contact hole 38. As a result, a dual damascene pattern 39 including the trench 37 and the contact hole 38 is formed.
도 2d를 참조하면, 듀얼 다마신 패턴(39)을 포함한 전체 상부에 비정질 구조를 가지며 확산 방지 특성이 우수한 금속 산화 절연물층(40a)을 층덮힘이 우수한 원자층 증착법으로 형성한다.Referring to FIG. 2D, a metal oxide insulator layer 40a having an amorphous structure on the entire top including the dual damascene pattern 39 and having excellent diffusion preventing characteristics is formed by an atomic layer deposition method having excellent layer covering.
금속 산화 절연물층(40a)은 Al2O3, ZrO2, HfO2및 Ta2O5중 어느 하나로 형성할 수도 있다.The metal oxide insulator layer 40a may be formed of any one of Al 2 O 3 , ZrO 2 , HfO 2, and Ta 2 O 5 .
도 2e를 참조하면, 에치 백 공정을 실시하여 캡핑층(36)의 상부, 트렌치(37)의 저면 및 콘택홀(38)의 저면에 형성된 금속 산화 절연물층을 제거하고, 트렌치(37) 및 콘택홀(38)의 측벽에만 잔류시켜, 금속 산화 절연물층으로 이루어진 금속 확산 방지막(40)을 형성한다.Referring to FIG. 2E, an etch back process is performed to remove the metal oxide insulator layer formed on the top of the capping layer 36, the bottom of the trench 37 and the bottom of the contact hole 38, and the trench 37 and the contact. The metal diffusion barrier film 40 formed of the metal oxide insulator layer is formed by remaining only on the sidewall of the hole 38.
에치 백 공정에 의하여 콘택홀(38)의 저면에는 반도체 기판(31)의 접합 영역(도시되지 않음)이 노출된다.A junction region (not shown) of the semiconductor substrate 31 is exposed on the bottom surface of the contact hole 38 by an etch back process.
도 2f를 참조하면, 듀얼 다마신 패턴(39)이 충분히 매립되도록 전체 상부에전도성 물질층을 형성한 후 캡핑층(36) 상부의 전도성 물질층을 제거하여 듀얼 다마신 패턴에만 전도성 물질층을 잔류시킨다. 이로써, 콘택홀에는 전도성 물질층으로 이루어진 콘택 플러그(41)가 형성되고, 동시에 트렌치에는 금속 배선(42)이 형성된다.Referring to FIG. 2F, the conductive material layer is formed on the entire upper portion so that the dual damascene pattern 39 is sufficiently buried, and then the conductive material layer remains only on the dual damascene pattern by removing the conductive material layer on the capping layer 36. Let's do it. As a result, a contact plug 41 made of a conductive material layer is formed in the contact hole, and a metal wiring 42 is formed in the trench.
마찬가지로, 전도성 물질층은 알루미늄, 구리, 텅스텐 등을 포함하는 금속 물질로 형성한다. 이 중에서도, 알루미늄을 이용하여 금속 배선을 형성하는 공정에서 일렉트로마이그레이션(Electromigration)이나 상호 간섭(Cross talk)이 발생되는 문제점을 해결하기 위하여, 주로 구리를 이용하여 금속 배선(22)을 형성한다.Likewise, the conductive material layer is formed of a metallic material including aluminum, copper, tungsten and the like. Among these, in order to solve the problem that electromigration or cross talk occurs in the process of forming metal wiring using aluminum, the metal wiring 22 is mainly formed of copper.
상기에서, 콘택 플러그(41)의 저면은 저항이 큰 금속 확산 방지막(40)과 접촉하지 않고, 콘택홀을 통해 노출된 반도체 기판(31)의 접합 영역(도시되지 않음)과 직접 접촉되므로, 접촉 저항을 낮출 수 있다.In the above, the bottom surface of the contact plug 41 is not in contact with the metal diffusion barrier film 40 having a high resistance, and is in direct contact with the junction region (not shown) of the semiconductor substrate 31 exposed through the contact hole. Can lower the resistance.
또한, 후속 공정으로 열공정이 실시될 경우에도, 콘택 플러그(41)의 하부가 반도체 기판(31)의 접합 영역과 직접 접촉된 상태에서 실시되므로 금속 확산 방지막(40)에 의하여 콘택 플러그(41)의 하부가 들뜨는 리프팅(Lifting) 현상을 방지할 수 있다. 이로써, 콘택 플러그(41)의 하부에는 보이드가 발생되지 않는다.In addition, even when the thermal process is performed in a subsequent process, since the lower portion of the contact plug 41 is carried out in direct contact with the bonding region of the semiconductor substrate 31, the contact plug 41 is formed by the metal diffusion barrier film 40. It is possible to prevent the lifting (Lifting) phenomenon that the lower part is lifted. As a result, no void is generated under the contact plug 41.
상기에서, 금속 배선(42)의 저면은 식각 방지막(34)에 의해 제 1 절연막(33)의 상부 표면과 접촉되지 않으므로, 금속 배선(42)이 제 1 절연막(33)으로 확산되거나 제 1 절연막(33)에 의해 금속 배선(42)이 산화되는 것을 방지할 수 있다.In the above, since the bottom surface of the metal wiring 42 is not in contact with the upper surface of the first insulating film 33 by the etch stop layer 34, the metal wiring 42 is diffused into the first insulating film 33 or the first insulating film is It is possible to prevent the metal wiring 42 from being oxidized by the reference numeral 33.
상술한 바와 같이, 본 발명은 원자층 증착법 및 에치 백 공정을 통해 비정질 구조를 가지며 확산 방지 특성이 우수한 금속 산화 절연물층을 트렌치 및 콘택홀의 측벽에만 형성함으로써, 콘택 플러그의 하부가 들뜨는 리프팅 현상에 의하여 콘택 플러그의 하부에 보이드가 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킨다.As described above, the present invention forms a metal oxide insulator layer having an amorphous structure and excellent diffusion preventing properties only on the sidewalls of the trench and contact hole through atomic layer deposition and etch back processes, thereby lifting the lower part of the contact plug by lifting. Preventing voids from occurring in the bottom of the contact plug improves process reliability and device electrical properties.
Claims (5)
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| KR1020010081938A KR20030051040A (en) | 2001-12-20 | 2001-12-20 | Method of forming a barrier metal layer in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7041582B2 (en) | 2003-11-13 | 2006-05-09 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| KR100876532B1 (en) * | 2004-08-27 | 2008-12-31 | 동부일렉트로닉스 주식회사 | Manufacturing Method of Semiconductor Device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7041582B2 (en) | 2003-11-13 | 2006-05-09 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| KR100876532B1 (en) * | 2004-08-27 | 2008-12-31 | 동부일렉트로닉스 주식회사 | Manufacturing Method of Semiconductor Device |
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| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |