KR100464267B1 - Method for manufacturing copper line of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, to form a first interlayer insulating film and a lower wiring on a semiconductor substrate, and to form a first diffusion prevention film, a second interlayer insulating film, and a second diffusion prevention film on a resultant in which the lower wiring is formed. Forming a via hole through which the lower wiring is exposed by etching the second diffusion preventing film and the first diffusion preventing film, forming a first barrier metal on the sidewall of the via hole, and embedding copper or a copper alloy in the via hole to form a plug. After forming the third interlayer insulating film and etching the third interlayer insulating film to form a groove defining a space of the upper wiring, a second barrier metal is formed on the groove sidewall of the third interlayer insulating film and the copper or copper alloy is embedded in the groove. To form the upper wiring. Accordingly, the present invention reduces the current concentration due to the flux discontinuity of copper and the barrier metal separated from each other on the upper wiring and the plug sidewall, leaving the diffusion barrier under the upper wiring, so that the yield of devices due to the EM failure of the copper wiring is reduced. And deterioration in reliability can be improved.

Description

Copper wiring formation method of a semiconductor device {METHOD FOR MANUFACTURING COPPER LINE OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a copper wiring of a semiconductor device.

In general, in the manufacture of semiconductor devices, metal wires are used to electrically connect the devices and the devices or the wires and the wires. Although aluminum (Al) or tungsten (W) is widely used as a metal wiring material, its low melting point and high resistivity make it difficult to apply to ultra-high density semiconductor devices.

Due to the ultra-high integration of semiconductor devices, it is necessary to use materials having low resistivity and highly reliable materials such as electromigration (EM) and stress migration (SM), and copper is the most suitable material to cope with this. In addition, the melting point of copper is relatively high as 1080 ° C. (aluminum; 660 ° C., tungsten; 3400 ° C.), and the specific resistance is 1.7 μΩ cm (aluminum; 2.7 μΩ cm, tungsten; 5.6). μΩcm) is very low. As a widely used metal wiring material such as copper, there is a copper alloy that is excellent in reliability and corrosion resistance without significantly higher specific resistance than pure copper.

1 and 2 are vertical cross-sectional views showing the shape of a copper wiring of a semiconductor device according to the prior art. With reference to these drawings, the manufacturing method of a conventional copper wiring is demonstrated.

First, the lower wiring 14 is formed on the first interlayer insulating film 10 of the semiconductor substrate. At this time, the barrier metal 12 is formed under the lower wiring 14 and sidewalls. The nitride film is deposited as a diffusion barrier 16 on the resultant on which the lower wiring 14 is formed, and at least one or more second interlayer insulating films 18 and 20 and a third interlayer insulating film 22 are sequentially formed thereon. Then, a dual damascene hole is formed by forming an upper wiring groove in the third interlayer insulating film 22 and via holes in the second interlayer insulating films 18 and 20 and the diffusion barrier film 16. Subsequently, the barrier metal 24 is formed in the dual damascene hole, and copper or a copper alloy is embedded in the dual damascene hole, and the surface thereof is planarized to form the upper wiring 26 connected to the lower wiring 14. In this conventional technique, as shown in FIG. 2, a diffusion barrier film 19 may be further formed below the third interlayer insulating film 22.

However, in the manufacturing method of the copper wiring for the prior art, the EM phenomenon which arises as the biggest problem is caused by the following causes.

First, in the dual damascene process of copper, copper ions are outdiffused into the interlayer insulating film due to the thermal process and the stress of each thin film layer. To prevent this, the copper wiring is protected by adding a barrier metal between the copper wiring and the interlayer insulating film. However, as shown in FIG. 1, electron flow (e) is generated during EM testing, and current flow is interrupted by barrier metal in the entire dual damascene hole, resulting in current concentration. In addition, the copper flux moves to the crowding point, so that the void f is generated at the bottom of the lower wiring, which causes EM failure.

Second, EM defects generated by the discontinuity of the copper flux by the barrier metal 24 inside the via holes of dual damascene. In order to prevent this phenomenon, the discontinuity point of the copper flux was solved by forming the upper barrier metal 24b on the groove sidewall of the dual damascene so as to be separated from the lower barrier metal 24a of the via hole sidewall of the dual damascene. However, the upper portion of the diffusion barrier layer 19 deposited after the via hole formation and the copper metal filling and the diffusion barrier layer 19 positioned below the insulation layer are etched together during the deposition and etching of the third interlayer dielectric layer 22 for forming the metal wiring. The copper of the wiring 26 is in direct contact with the second interlayer insulating film 20, and there is a problem in that it is out diffused into the second interlayer insulating film 20.

An object of the present invention is to form a dual damascene via hole and to form a barrier metal and plug in the via hole, and then to form a groove of the dual damascene and the barrier metal and the upper wiring in the via hole in order to solve the problems of the prior art. This reduces the concentration of current due to the flux discontinuity of the lower part of the upper wiring and the barrier metal separated from each other on the upper wiring and the plug sidewall, reducing the yield and reliability of the device due to the EM failure of the copper wiring. The present invention provides a method for forming a copper wiring of a semiconductor device that can be improved.

In order to achieve the above object, the present invention provides a method for forming a first interlayer insulating film on a semiconductor substrate, forming a lower wiring on the first interlayer insulating film, and forming a lower wiring between the first diffusion barrier layer and the second layer. Forming an insulating film and a second diffusion barrier layer, etching the second diffusion barrier layer to the first diffusion barrier layer, forming a via hole extending through the lower wiring, forming a first barrier metal on the sidewall of the via hole, and forming copper or copper in the via hole Embedding the alloy to form a plug, forming a third interlayer insulating film in the resultant, etching the third interlayer insulating film to form a groove defining a space of the upper wiring, and forming a groove on the sidewall of the groove of the third interlayer insulating film. Forming a barrier metal and embedding copper or a copper alloy in the groove to form the upper wiring.

In order to achieve the above object, another method of the present invention provides a method of forming a first interlayer insulating film on a semiconductor substrate, forming a lower wiring on the first interlayer insulating film, and forming a first wiring on the first interlayer insulating film. Forming a second interlayer insulating film and a second diffusion barrier layer, etching a second diffusion barrier layer or a first diffusion barrier layer to form a via hole in which lower wiring is exposed, and forming a first barrier metal on the sidewall of the via hole Forming a plug by embedding copper or a copper alloy, forming a third interlayer insulating film in the resultant, and etching a part of the third interlayer insulating film and the second diffusion preventing film to form a groove defining a space of the upper wiring; A second barrier metal is formed on the sidewalls of the grooves of the third interlayer insulating film and the second diffusion barrier layer, and the copper or copper alloy is buried in the grooves. It comprises the step of forming a line.

1 and 2 are vertical cross-sectional views showing the shape of a copper wiring of a semiconductor device according to the prior art,

3 to 7 are process flowcharts illustrating a method for forming a copper wiring of a semiconductor device according to an embodiment of the present invention;

8 is a flowchart illustrating a method of forming a copper interconnection of a semiconductor device in accordance with another embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

100: first interlayer insulating film of semiconductor substrate

102 barrier barrier 104 lower wiring

106: first diffusion barrier film 108, 110: second interlayer insulating film

112: second diffusion barrier film 114, 124: photoresist pattern

116: via hole 118: first barrier metal

120 plug 122 third interlayer insulating film

126: groove 128: second barrier metal 130: upper wiring

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 to 7 are process flowcharts illustrating a method for forming a copper wiring of a semiconductor device according to an embodiment of the present invention. Referring to this, a copper wiring manufacturing process according to an embodiment of the present invention is as follows.

First, as shown in FIG. 3, the barrier metal 102 and the lower wiring 104 are formed on the first interlayer insulating layer 100 of the semiconductor substrate. Then, a nitride film is deposited as a first diffusion barrier film 106 on the resultant on which the lower wiring 104 is formed, and at least one or more second interlayer insulating films 108 and 110 and a second diffusion barrier film 112 are formed thereon.

Next, a photoresist pattern 114 defining a via hole of dual damascene is formed on the second diffusion barrier layer 112.

Subsequently, as shown in FIG. 4, the second diffusion barrier 112, the second interlayer insulating layers 108 and 110, and the first diffusion barrier 106 are etched by a dry etching process using the photoresist pattern 114. A via hole 116 is formed through which the lower wiring 104 is exposed. The first barrier metal 118 is formed on the sidewall of the via hole 116. At this time, the first barrier metal 118 is Ta / TaN.

Subsequently, as shown in FIG. 5, the plug 120 is formed by embedding and planarizing copper or a copper alloy in the via hole 116. In addition, a third interlayer insulating layer 122 is formed on the entire surface of the resultant, and a photoresist pattern 124 defining a wiring area of dual damascene is formed thereon.

Then, as illustrated in FIG. 6, the third interlayer insulating layer 122 is etched by the dry etching process using the photoresist pattern 124 to form the groove 126 defining the space of the upper wiring.

Then, as shown in FIG. 7, the second barrier metal 128 is formed on the sidewall of the groove 126 of the third interlayer insulating layer 124, and the upper wiring 130 is embedded by embedding copper or a copper alloy in the groove 126. ). At this time, the second barrier metal 128 is Ta / TaN.

Therefore, in the method of manufacturing the copper wiring according to the exemplary embodiment of the present invention, the upper wiring 130 and the plug 120 are blocked by the second diffusion barrier layer 122 and are respectively separated from the via hole and the groove sidewall of the dual damascene. Since the first barrier metal 118 and the second barrier metal 128 are formed, the defects of the copper flux and defects caused by the outward diffusion of the copper ions of the upper wiring 130 generated in the conventional copper wiring to the interlayer insulating film 110 are caused. It prevents EM defects generated by discontinuities in advance.

8 is a flowchart illustrating a method of forming a copper wiring of a semiconductor device according to another exemplary embodiment of the present invention. Referring to FIG. 8, another embodiment of the present invention forms a copper wiring as in the above-described embodiment, wherein the third interlayer insulating layer 122 and the second diffusion barrier layer during the groove etching process of the dual damascene for the upper wiring are formed. A portion of the 112 is etched to form a groove defining the space of the upper wiring and the second barrier metal 128a is formed on the sidewall of the groove, and then the upper wiring 130a is formed by embedding and planarizing copper or a copper alloy. do.

As described above, the present invention forms a via hole of dual damascene, a barrier metal and a plug in the via hole, and then forms a groove of the dual damascene, and a barrier metal and an upper wiring in the via hole to form a diffusion barrier layer under the upper wiring. The flux discontinuity of the copper and the barrier metal separated from the upper wiring and the plug sidewall reduce current concentration, thereby improving the yield and reliability of the device due to the EM failure of the copper wiring.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (5)

Forming a first interlayer insulating film on the semiconductor substrate; Forming a lower wiring on the first interlayer insulating film; Forming a first diffusion barrier layer, a second interlayer insulating layer, and a second diffusion barrier layer on a resultant of the lower wirings; Etching the second diffusion barrier layer to the first diffusion barrier layer to form a via hole in which a lower wiring is exposed; Forming a first barrier metal on the sidewall of the via hole and embedding copper in the via hole to form a plug; Forming a third interlayer insulating film on the resultant and etching the third interlayer insulating film to form a groove defining a space of an upper wiring; And Forming a second barrier metal on the sidewalls of the grooves of the third interlayer insulating film and embedding copper or a copper alloy in the grooves to form the upper wirings. Forming a first interlayer insulating film on the semiconductor substrate; Forming a lower wiring on the first interlayer insulating film; Forming a first diffusion barrier layer, a second interlayer insulating layer, and a second diffusion barrier layer on a resultant of the lower wirings; Etching the second diffusion barrier layer to the first diffusion barrier layer to form a via hole in which a lower wiring is exposed; Forming a first barrier metal on the sidewalls of the via holes and embedding copper or a copper alloy in the via holes; Forming a third interlayer insulating film on the resultant and etching a part of the third interlayer insulating film and the second diffusion preventing film to form a groove defining a space of the upper wiring; And Forming a second barrier metal on the sidewalls of the grooves of the third interlayer insulating film and the second diffusion barrier layer, and forming an upper wiring by embedding copper or a copper alloy in the grooves. Forming method. The method of forming a copper wiring of a semiconductor device according to claim 1 or 2, wherein the second interlayer insulating film is composed of at least two insulating films. The method for forming a copper wiring of a semiconductor device according to claim 1 or 2, wherein the first and second diffusion barrier films are nitride films. The method for forming a copper wiring of a semiconductor device according to claim 1 or 2, wherein the first and second barrier metals are Ta / TaN.