KR20110071267A

KR20110071267A - Metal interconnection of semiconductor device and method for manufacturing the same

Info

Publication number: KR20110071267A
Application number: KR1020090127784A
Authority: KR
Inventors: 신은종
Original assignee: 주식회사 동부하이텍
Priority date: 2009-12-21
Filing date: 2009-12-21
Publication date: 2011-06-29

Abstract

The metallization of the semiconductor device according to the embodiment may include: a first insulating layer formed on the semiconductor substrate and including the first wiring; A capping layer formed on the first insulating layer; A second insulating layer formed on the capping layer; A via hole extending from the trench to expose a portion of the trench formed in the second insulating layer and the capping layer corresponding to the first wiring; A first recess groove formed by removing a capping layer under the via hole and a portion of the first wiring so that the first wiring is exposed; A barrier layer formed along sidewalls of the trench, via hole and first recess groove; A second recess groove formed by removing the barrier layer inside the first recess groove so that the first wiring is exposed; And a second interconnection gap formed in the trench and the via hole including the barrier layer.

Description

Metal interconnection of semiconductor device and its manufacturing method {METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The embodiment relates to metallization of a semiconductor device and a method of manufacturing the same.

Development of manufacturing technology of semiconductor devices is progressing rapidly, and accordingly, semiconductor devices are becoming smaller and more integrated.

As the semiconductor devices become more integrated, wiring becomes more fine. As a result, copper using copper, which is a material having a lower resistance and higher electro-migration than aluminum or an aluminum alloy, which has been widely used for wiring materials The development of wiring is proceeding rapidly.

Copper wiring can be formed using a "damacin process".

The damascene process forms trenches and via holes for exposing a lower interconnection to an insulation layer, deposits a copper layer in the trenches and via holes, and then uses the chemical mechanical polishing (CMP) process. The film is planarized to form copper wiring inside the trench and the via hole. In particular, since the etch stop layer formed of the nitride layer is formed on the lower interconnection, the etch stop layer is selectively removed after the via hole and the trench is formed to expose the lower interconnection.

In this copper wiring process, the cleaning process of the via hole bottom interface is one of the important factors in the operation of the device.

Furthermore, it contributes to minimizing the RC delay of the low-k Cu interconnection by lowering the serial resistance through the vias connecting the copper metal wires, and to electro-migration and SM. It is one of the typical processes that have a dominant influence on the stress-migration characteristics.

1 to 4 are cross-sectional views showing a conventional copper metal wiring manufacturing process.

Referring to FIG. 1, a second insulating layer 50 is formed on the semiconductor substrate 1-1 including the first insulating layer 20 on which the lower wiring 35 is formed.

For example, the lower wiring 35 is a copper wiring, and a barrier metal layer 31 is formed on the sidewall of the lower wiring.

Before forming the second insulating layer 50, a capping layer 40 made of a nitride film may be formed on the first insulating layer 20.

A damascene process is applied to the second insulating layer 50 to form a via trench 55.

After the via trench 55 is formed, a portion of the capping layer 40 may be removed to expose the lower interconnection 35.

Referring to FIG. 2, a barrier layer 60 formed of Ta / TaN is formed in the via trench 55.

The barrier layer 55 on the lower interconnection 35 is selectively removed through the etching process using Ar + gas to form the auxiliary via hole 65. Accordingly, the lower wiring 35 below the auxiliary via hole 65 may be exposed.

Referring to FIG. 3, after the Ta layer 70 and the copper seed layer 80 are sequentially formed along the inside of the via trench 55 in which the barrier layer 60 is formed, the copper layer is gapfilled and the upper wiring ( 90).

However, as described above, the etching process using Ar + is very sensitive to the fluctuation range of RC, and is affected by the uniformity of the etching process of the capping layer 40, which is an anti-oxidation layer of the lower wiring 35, and is controlled in the local region. The auxiliary via hole 65 may cause a failure that does not land.

In addition, as shown in FIG. 4, an EM (electro-migration effect) due to a locally high e-crowding effect (HE) in a region where the upper interconnection 90 and the lower interconnection 35 are connected. ) Problems may occur.

As a result, the deteriorated copper ions diffuse through the interface between the lower interconnection 35 and the auxiliary via hole 65, which may cause defects because they are fatal to the reliability and yield of the device.

The embodiment provides a metallization of a semiconductor device having electrically stable characteristics and a method of manufacturing the same.

In accordance with another aspect of the present disclosure, a method of forming metal wirings of a semiconductor device may include forming a first insulating layer including first wirings on a semiconductor substrate; Forming a capping layer on the first insulating layer; Forming a second insulating layer on the capping layer; Forming a trench in the second insulating layer and forming a via hole extending from the trench to expose a portion of the capping layer corresponding to the first wiring; Removing a portion of the capping layer and the first wiring below the via hole to expose the first wiring and forming a first recess groove; Forming a barrier layer along sidewalls of the trench, via hole and first recess groove; Removing the barrier layer inside the first recess groove to form the second recess groove so that the first wiring is exposed; Forming a second interconnection so that the trench and the via hole including the barrier layer are gap-filled.

In example embodiments, a lower capping layer remaining before the barrier layer is formed in the via hole and the trench is removed to form a copper wiring, and a first recess groove is formed through a sputtering process for the first wiring. In addition, a deposition process and a punch thru process may be performed on the barrier layer, and the barrier layer may extend on a sidewall of the first recess groove.

Accordingly, the series resistance of the copper metal wiring via the via hole may be lowered and stably maintained.

In addition, it is possible to implement the best via contact landing process for the lower copper metallization by minimizing the influence of the characteristic variation in forming the metallization.

In addition, the bottom surface of the via hole may form a U-shaped via bottom profile at the interface of the first wiring by the second recess groove.

As a result, localized and e-crowding effects may be lowered, and immunity may be doubled to improve SM (migration migration) and EM (electro-migration) characteristics.

At the same time, due to the depth of the first recess recess formed through the argon sputtering process, copper ions caused by EM can be prevented from spreading through the first wiring and the via interface.

Hereinafter, a metal wiring and a method of manufacturing the semiconductor device according to the embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

9 is a cross-sectional view illustrating metal wiring of a semiconductor device in accordance with an embodiment.

The metallization of the semiconductor device according to the embodiment may include a first insulating layer 110 formed on the semiconductor substrate 100 and including the first wiring 130; A capping layer 140 formed on the first insulating layer 110; A second insulating layer 150 formed on the capping layer 140; A via hole (V) extending from the trench (T) to expose a portion of the trench (T) formed in the second insulating layer (150) and the capping layer (140) corresponding to the first wiring (130); A first recess groove 161 formed by removing a capping layer 140 under the via hole V and a portion of the first wiring 130 so that the first wiring 130 is exposed; A barrier layer 170 formed along sidewalls of the trench T, via hole V, and first recess groove 161; A second recess groove 162 formed by removing the barrier layer 170 on the bottom surface of the first recess groove 161 so that the first wiring 130 is exposed; And a second wiring 200 having a gap fill formed in the trench T and the via hole V including the barrier layer 170.

For example, the first recess groove 161 may have a first depth D1 based on the surface of the first insulating layer 110. The second recess groove 162 may have a second depth D2 equal to or greater than the first depth D1.

The first wiring 130 and the second wiring 200 may be formed of copper.

A copper seed layer 190 and a Ta adhesive layer 180 may be disposed on sidewalls of the first wiring 130 and the second wiring 200.

In the image sensor according to the embodiment, the second wiring located above may be stably connected to the first wiring below through the via hole, the first and second recess grooves. Accordingly, the series resistance of the copper metal wiring can be lowered, and the operation of the device can be stably maintained.

Due to the depth of the first recess groove, copper ions may be prevented from being diffused through the first wiring and the via hole interface below.

Since the second wire is connected to the first wire through the first and second recess grooves, localized heating and current-e-crowiding characteristics are improved, and SM and EM characteristics are greatly improved. You can.

5 to 10, a metal wire manufacturing method of a semiconductor device according to an embodiment will be described in detail.

Referring to FIG. 5, a capping layer 140 is formed on the first insulating layer 110 including the first wiring 130 in the semiconductor substrate 100.

Although not shown, an isolation layer defining an active region and a field region may be formed in the semiconductor substrate 100, and elements such as a source / drain and a gate electrode of a transistor may be formed in the active region.

The first insulating layer 110 may be formed of an insulating film such as an oxide film or a nitride film.

The first wire 130 may pass through the first insulating layer 110 and be electrically connected to elements (not shown) in the lower portion.

For example, a trench is formed in the first insulating layer 110, and a barrier metal layer 120 and a copper seed layer (not shown) are sequentially formed in the trench. The copper plating layer may be gap-filled on the copper seed layer and planarized through a CMP process.

The capping layer 140 may be formed on the first wiring 130 and the first insulating layer 110 to prevent oxidation of the first wiring 130. In addition, the capping layer 140 may protect the first wiring 130 in a subsequent process.

For example, the capping layer 140 may be formed of a nitride film (SiN) through a PE-CVD process.

Referring to FIG. 5 again, a second insulating layer 150 is formed on the capping layer 140 and a trench T and a via hole V are formed through a dual damascene process.

For example, the second insulating layer 150 may be formed of a low-k dielectric (low-k IMD) through a PE-CVD process.

For reference, the damascene process includes a via first method (Via first dual damascene), a trench first method (Trench first dual damascene), and a self-aligned dual damascene method, Figure 1 is a trench first method For example, the trench and the via hole are formed through the dual damascene process.

Although not shown, the trenches T and the via holes V may be formed by forming a first photoresist pattern (not shown) on the second insulating layer 150 and using the first photoresist pattern as a mask. The trench T of depth is first formed. In addition, a second photoresist pattern (not shown) for selectively exposing a bottom surface of the trench T is formed on the first insulating layer 110 on which the trench T is formed, and then the second photoresist. The via hole V may be formed by etching the first insulating layer 110 under the trench T using the pattern as a mask. When forming the via hole V, the etching may be terminated by the capping layer 140. Therefore, the surface of the capping layer 140 corresponding to the first wiring 130 may be exposed by the via hole V. FIG.

Thereafter, the capping layer 140 exposed through the via hole V may be selectively removed through a reactive ion ecth, and the surface of the first wiring 130 may be exposed.

Referring to FIG. 6, the first interconnection 130 under the via hole V may be selectively removed to form a first recess groove 161.

The first recess groove 161 may be formed to have a first depth D1 based on the surface of the first insulating layer 110. For example, the first depth D1 may be 50˜100 mm.

The first recess groove 161 may be formed by a primary sputtering process using Ar +. The primary sputtering process may be a soft process of applying first power to minimize damage of the first wiring 130.

Although not shown, the first recess groove 161 may be formed by using a photoresist pattern that selectively exposes the first wiring 130 exposed by the via hole V as an etching mask. In this case, the capping layer 140 may be removed together.

Therefore, an exposed area of the first wiring 130 may extend in the first recess groove 161.

Referring to FIG. 7, the barrier layer 170 is formed along the surface profile of the trench T, the via hole V, and the first recess groove 161.

The barrier layer 170 may prevent diffusion of copper ions of the copper wirings formed in the trenches T and the via holes V into the second insulating layer 150.

For example, the barrier layer 170 may be formed of a Ta / TaN film.

The barrier layer 170 may contact the first wiring 130 through sidewalls and bottom surfaces of the first recess grooves 161.

The barrier layer 170 is formed to be in contact with the sidewall of the first recess 161, and then the copper ions of the copper wiring gap-filled through the via hole V are diffused into the capping layer 140. You can prevent it.

That is, the barrier layer 170 may be formed to extend to the first depth of the first recess groove 161 to prevent diffusion of copper ions.

Subsequently, the barrier layer 170 formed on the bottom surface of the first recess groove 161 is required to be connected to the copper metal wiring formed thereon and the first wiring 130.

Referring to FIG. 8, the bottom surface of the barrier layer 170 is selectively removed and a second recess groove 162 is formed.

The second recess groove 162 may remove the barrier layer formed on the bottom surface of the first recess groove 161 and expose the first wiring 130.

The second recess groove 162 may have the same first depth D1 as the first recess groove 161. Alternatively, the second recess groove 162 may have a second depth D2 deeper than the first depth D1.

For example, the second recess groove 162 is formed on the bottom surface of the first recess groove 161 through a secondary sputtering process using Ar + for 10 to 30 seconds. It can be formed by selectively removing the bay. The secondary sputtering process may be a hard process of applying a second power higher than the first power so that the barrier layer is removed.

The bottom surface of the second recess groove 162 may have a concave curved surface through a punch through process in which the argon ions are ionized.

That is, the via holes V and the first and second recess grooves 161 and 162 may be formed in a U shape.

According to the U-shaped bottom profile of the via hole V, a copper metallization deposition process formed in a subsequent process may be easily performed.

The barrier layer 170 may be selectively formed only on sidewalls of the trench T, the via hole V, and the first recess groove 161, and expose the first wiring 130.

In the first and second recessed grooves 161 and 162, the barrier layer 170 may have a first length that is equal to the first depth D1 of the first recessed groove 161.

Referring to FIG. 9, the Ta adhesive layer 180 and the seed layer 190 are formed along the step of the barrier layer 170.

For example, the Ta adhesive layer 180 is formed along sidewalls of the trench T, the via hole V, and the first and second recess grooves 161 and 162 including the barrier layer 170 through a PVD process. do.

The seed layer 190 may be easily formed by the Ta adhesive layer 180.

The seed layer 190 is formed on the Ta adhesive layer 180. The seed layer 190 is formed along the step of the Ta adhesive layer 180 to facilitate deposition of copper, which is a subsequent process.

For example, the seed layer 190 may be formed by depositing Cu, Au, or Pt.

Next, a copper film is deposited on the seed layer 190 so that the trenches T and the via holes V are gap-filled, and a heat treatment process is performed. Thereafter, the CMP process is performed on the copper film to form the second wiring 200.

The second wiring 200 may be electrically and physically connected to the first wiring 130 below through the first and second recess grooves 161 and 162 below the via hole V. Referring to FIG.

In this case, since the Ta adhesive layer 180 and the seed layer 190 are conductive metal layers under the second wire 200, the first wire 130 and the second wire 200 may be electrically connected to each other. .

Due to the U-shaped bottom profile of the via hole V, the deposition of a copper film may be easily deposited inside the via hole V, and voids may be prevented.

FIG. 10 is a cross-sectional view illustrating a current movement flow of the metal wiring shown in FIG. 9.

As shown in FIG. 10, since the barrier layer 170 is formed on the sidewall of the second wiring 200, copper ions constituting the second wiring 200 are formed on the second insulating layer 150 and the second wiring 200. The diffusion into the capping layer 140 may be prevented.

In particular, since the barrier layer 170 extends to the sidewall of the first recess 161, the barrier layer 170 may further prevent diffusion of copper ions of the second wiring 200.

In particular, since the second wiring 200 is formed to extend into the first wiring 130 through the first and second recess grooves 161 and 162, the current movement area is increased and a low current density effect is obtained. (low e-crowding effect: LE) characteristics can be improved.

In an embodiment, the lower capping layer remaining before the barrier layer is formed in the via trench is removed, and a first recess groove is formed through a sputtering process for the first wiring. In addition, a deposition process and a punch thru process may be performed on the barrier layer, and the barrier layer may extend on a sidewall of the first recess groove.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 to 4 are cross-sectional views illustrating a metal wire manufacturing process of a general semiconductor device.

5 to 10 are cross-sectional views illustrating a metallization manufacturing process of a semiconductor device according to an embodiment.

Claims

Forming a first insulating layer including a first wiring on the semiconductor substrate;

Forming a capping layer on the first insulating layer;

Forming a second insulating layer on the capping layer;

Forming a trench in the second insulating layer and forming a via hole extending from the trench to expose a portion of the capping layer corresponding to the first wiring;

Removing a portion of the capping layer and the first wiring below the via hole to expose the first wiring and forming a first recess groove;

Forming a barrier layer along sidewalls of the trench, via hole and first recess groove;

Selectively removing the barrier layer on the bottom surface of the first recess groove so as to expose the first wiring, and forming a second recess groove;

And forming a second wiring such that the trench and the via hole including the barrier layer are gap-filled.

The method of claim 1,

The first recess groove may be formed to a first depth with respect to the surface of the first insulating layer, and the second recess groove may be formed to a second depth that is equal to or greater than the first depth. Metal wire manufacturing method of a semiconductor device.

The method of claim 2,

The barrier layer formed on the sidewall of the first recess groove has a length equal to the first depth.

The method of claim 1,

The first recessed groove is formed through a first sputtering process having a first power, and the second recessed groove is a semiconductor device formed through a second sputtering process having a second power greater than a first power. Metal wiring manufacturing method.

The method of claim 1,

And a bottom surface of the second recess groove has a concave curved surface.

The method of claim 1,

And forming a Ta adhesive layer and a copper seed layer sequentially along surfaces of the trenches and via holes including the barrier layer, after forming the second recess grooves.

The method of claim 1,

The barrier layer is formed of Ta / TaN,

The first wiring and the second wiring is a metal wiring manufacturing method of a semiconductor device formed of copper.

A first insulating layer formed on the semiconductor substrate and including the first wiring;

A capping layer formed on the first insulating layer;

A second insulating layer formed on the capping layer;

A via hole extending from the trench to expose a portion of the trench formed in the second insulating layer and the capping layer corresponding to the first wiring;

A first recess groove formed by removing a capping layer under the via hole and a portion of the first wiring so that the first wiring is exposed;

A barrier layer formed along sidewalls of the trench, via hole and first recess groove;

A second recess groove formed by removing the barrier layer inside the first recess groove so that the first wiring is exposed; And

And a second interconnection gap formed in the trench and the via hole including the barrier layer.

The method of claim 8,

The first recess groove has a first depth with respect to the surface of the first insulating layer, and the second recess groove has a second depth that is equal to or greater than the first depth. Metal wiring.

The method of claim 8,

The barrier layer has a metal structure extending to the side wall of the first recess groove.

The method of claim 8,

The metal recess of claim 2, wherein the second recess groove has a concave curved surface.

The method of claim 8,

The first wiring and the second wiring are metal wirings of a semiconductor device formed of copper.

The method of claim 8,

Metal wiring of the semiconductor device is formed with a copper seed film and a Ta adhesive layer on the sidewall of the first wiring.