KR20080001905A - Method of forming a metal wire in a semiconductor device - Google Patents

Method of forming a metal wire in a semiconductor device

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Publication number
KR20080001905A
KR20080001905A KR1020060060363A KR20060060363A KR20080001905A KR 20080001905 A KR20080001905 A KR 20080001905A KR 1020060060363 A KR1020060060363 A KR 1020060060363A KR 20060060363 A KR20060060363 A KR 20060060363A KR 20080001905 A KR20080001905 A KR 20080001905A
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South Korea
Prior art keywords
forming
trench
layer
film
dished
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KR1020060060363A
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Korean (ko)
Inventor
김은수
홍승희
정철모
김정근
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주식회사 하이닉스반도체
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Priority to KR1020060060363A priority Critical patent/KR20080001905A/en
Publication of KR20080001905A publication Critical patent/KR20080001905A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a metal interconnection of a semiconductor device is provided to block a dishing problem and to prevent copper and an oxide layer from being bonded to each other by an oxidation phenomenon by using a BCB material having strong resistance as an insulation layer and by forming Sb2Te3 in a dishing region on a metal interconnection after a polishing process. After a first insulation layer(102) and a first hard mask layer(104) stacked on a semiconductor substrate(100) are etched to form a first trench, a first copper layer is formed on the resultant structure to fill the first trench. After a polishing process is performed to form a first metal interconnection(110) whose upper portion is dished, Sb2Te3(112) is formed only on the dished first metal interconnection. After a first dielectric layer(114), a second insulation layer(116), a second dielectric layer(118), a third insulation layer(120) and a second hard mask layer(122) are sequentially formed on the resultant structure, the second hard mask layer, the third insulation layer, the second dielectric layer, the second insulation layer and the first dielectric layer are sequentially etched to form a contact hole of a dual damascene structure and a second trench. After a second copper layer is formed on the resultant structure to fill the contact hole and the second trench, a polishing process is performed to form a second metal interconnection(130) whose upper portion is dished. Sb2Te3 is formed only on the dished second metal interconnection.

Description

반도체 소자의 금속 배선 형성방법{Method of forming a metal wire in a semiconductor device}Method of forming a metal wire in a semiconductor device

도 1은 일반적인 반도체 소자의 금속배선 형성방법으로서 이에 대한 문제점을 도시한 단면도이다. 1 is a cross-sectional view showing a problem as a method of forming a metal wiring of a general semiconductor device.

도 2a 내지 도 2f는 본 발명의 일 실시 예에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위해 도시한 단면도이다.2A through 2F are cross-sectional views illustrating a method of forming metal wires in a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 제1 절연막100 semiconductor substrate 102 first insulating film

104 : 제1 하드 마스크막 106 : 제1 트렌치104: first hard mask film 106: first trench

108 : 제1 베리어 메탈막 110 : 제1 금속배선108: first barrier metal film 110: first metal wiring

112, 132 : Sb2Te3 114 : 제1 유전체막112, 132: Sb 2 Te 3 114: First dielectric film

116 : 제2 절연막 118 : 제2 유전체막116: second insulating film 118: second dielectric film

120 : 제3 절연막 122 : 제2 하드 마스크막120: third insulating film 122: second hard mask film

124 : 콘택홀 126 : 제2 베리어 메탈막124: contact hole 126: second barrier metal film

128 : 제2 구리막 130 : 제2 금속배선128: second copper film 130: second metal wiring

134 : 제3 유전체막 136 : 패시베이션층134: third dielectric film 136: passivation layer

본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히, Sb2Te3를 이용하여 금속배선의 신뢰성(reliability)을 향상시키기 위한 반도체 소자의 금속 배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices for improving the reliability of metal wirings using Sb 2 Te 3 .

플래시 메모리 소자에서 금속배선 형성방법으로 텅스텐(W)을 플러그로 사용하는 다마신(damascene) 방법이 사용되고 있다. 소자가 고집적화되어 감에 따라, 디자인 률(Design rule) 감소와 함께 프로그램 속도의 발전을 요구하고 있어 비저항이 낮은 구리(Cu)와 저유전 물질을 이용하여 금속배선을 형성하는 방법이 연구되고 있다.A damascene method using tungsten (W) as a plug is used as a method for forming metal wiring in a flash memory device. As the devices become more integrated, a method of reducing the design rule and demand for the development of the program speed has been demanded. Therefore, a method of forming a metal wiring using low resistivity copper (Cu) and a low dielectric material has been studied.

도 1은 일반적인 반도체 소자의 금속배선 형성방법으로서 이에 대한 문제점을 도시한 단면도이다. 1 is a cross-sectional view showing a problem as a method of forming a metal wiring of a general semiconductor device.

도 1을 참조하면, 반도체 기판(10) 상부에 적층된 제1 절연막(11) 및 제1 하드 마스크막(12)의 일부를 식각하여 제1 트렌치를 형성한 후 전체 구조 표면에 제1 베리어 메탈막(13)을 형성한 후 제1 트렌치가 매립되도록 제1 트렌치 내에 구리(Cu) 막을 형성하여 제1 금속 배선(14)을 형성한다. 전체 구조 상부에 제1 유전 체막(15), 제2 절연막(16), 제2 유전막(17), 제3 절연막(18) 및 제2 하드 마스크막(19)를 순차적으로 형성한 후 제2 하드 마스크막(19), 제3 절연막(18), 제2 유전막(17), 제2 절연막(16) 및 제1 유전막(15)을 순차적으로 식각하여 듀얼 다마신 구조의 콘택홀과 제2 트렌치를 형성한다. 전체 구조 표면에 제2 베리어 메탈막(20)을 형성한 후 듀얼 다마신 구조의 콘택홀과 제2 트렌치가 매립되도록 구리(Cu)막을 형성한 후 연마하여 제2 금속배선(21)을 형성한다. 전체 구조 상부에 제3 유전체막(22)을 형성한다. Referring to FIG. 1, a portion of the first insulating layer 11 and the first hard mask layer 12 stacked on the semiconductor substrate 10 are etched to form a first trench, and then a first barrier metal is formed on the entire structure surface. After the film 13 is formed, a copper (Cu) film is formed in the first trench so that the first trench is buried to form the first metal wiring 14. The first hard film 15, the second insulating film 16, the second dielectric film 17, the third insulating film 18 and the second hard mask film 19 are sequentially formed on the entire structure, and then the second hard film The mask layer 19, the third insulating layer 18, the second dielectric layer 17, the second insulating layer 16, and the first dielectric layer 15 are sequentially etched to form a contact hole and a second trench having a dual damascene structure. Form. After forming the second barrier metal layer 20 on the entire structure surface, a copper (Cu) layer is formed and polished to fill the contact hole and the second trench of the dual damascene structure to form the second metal wiring 21. . The third dielectric film 22 is formed over the entire structure.

그러나, 상기 공정으로 금속 배선을 형성할 경우 다음과 같은 문제점이 발생한다. However, when the metal wiring is formed by the above process, the following problems occur.

첫째, 제1 금속 배선과 제2 금속 배선을 연결하는 콘택의 바텀(bottom) 부분에 형성된 베리어 메탈막이 두꺼울 경우, 전자가 베리어 메탈막을 지나 금속 배선을 통과할 때 베리어 마탈막과 제1 금속 배선 상부의 경계면에서 물질의 공급이 차단되어 구리 이온이 절연막 쪽으로 확산되어 보이드(void; a)가 발생하거나, 베컨시(vacancy; b)가 발생한다. 이로 인하여 금속 배선 자체가 단락되는 EM(electro-migration) 또는 SM(stress-migration) 페일(fail)이 발생한다. First, when the barrier metal film formed in the bottom portion of the contact connecting the first metal wire and the second metal wire is thick, the barrier metal layer and the upper part of the first metal wire when electrons pass through the metal wire through the barrier metal film. The supply of material is interrupted at the interface of the copper ions to diffuse the copper ions toward the insulating film to generate voids (a) or vacancies (b). This causes an electro-migration (EM) or stress-migration (SM) fail in which the metal wires themselves are shorted.

둘째, 듀얼 다마신 구조의 콘택홀과 트렌치 내에 베리어 메탈막 형성 공정시 콘택홀과 트렌치 상부 영역에 오버행(over hang; c)이 발생한다. Second, an overhang (c) occurs in the contact hole and the trench upper region during the barrier metal film forming process in the contact hole and the trench of the dual damascene structure.

셋째, 금속 배선을 형성하기 위해 구리막 연마 공정시 금속 배선 상부가 디싱(dishing; b)되는 문제가 발생한다. Third, a problem arises that the upper portion of the metal wiring is dished (b) during the copper film polishing process to form the metal wiring.

넷째, 구리는 산소와의 친밀도가 크기 때문에 노출시 산화도가 크다. 이로 인하여 금속 배선의 저항(resistance)이 증가하는 문제점이 발생한다.Fourth, copper has a high degree of oxidation upon exposure because of its high affinity with oxygen. This causes a problem in that the resistance of the metal wiring increases.

다섯째, 상기의 문제점들로 인하여 RC 딜레이, 누설 전류, TDDB(Time Dependent Dielectric Breakdown)와 같은 특성이 나빠져 소자의 축소화가 어렵다.Fifth, due to the problems described above, characteristics such as RC delay, leakage current, and time dependent dielectric breakdown (TDDB) deteriorate, making it difficult to reduce the size of the device.

상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 절연막으로 강한 저항력을 갖는 BCB 물질을 사용하고, 연마 공정 후 금속 배선 상부의 디싱 영역에 Sb2Te3를 형성함으로써 디싱 문제를 방지함과 동시에 산화 현상으로 인하여 구리와 산화막이 결합하는 것을 방지할 수 있을 뿐만 아니라, 구리 확산에 의한 보이드 발생을 방지할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 데 있다. An object of the present invention devised to solve the above problems is to use a BCB material having a strong resistance as an insulating film, and to prevent the dishing problem by forming Sb 2 Te 3 in the dishing area of the upper portion of the metal wiring after the polishing process The present invention provides a method of forming a metal wiring of a semiconductor device capable of preventing the copper and the oxide film from bonding due to oxidation and preventing the generation of voids due to copper diffusion.

본 발명의 다른 목적은 메모리 소자의 배선 형성과정에서 문제시되는 RC 딜레이를 줄여 파워 소비(power consumption)를 줄일 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 데 있다. Another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can reduce power consumption by reducing RC delay, which is a problem in forming a memory device.

본 발명의 또 다른 목적은 금속 배선의 신뢰성 특성을 향상시켜 EM 및 SM 페일을 감소시키고, TDDB 특성을 향상시킴으로써 소자의 축소화를 가능하도록 하는 반도체 소자의 금속 배선 형성방법을 제공하는 데 있다. It is still another object of the present invention to provide a method for forming a metal wiring of a semiconductor device, which can reduce the EM and SM fail by improving the reliability characteristics of the metal wiring, and reduce the size of the device by improving the TDDB characteristics.

본 발명의 일 실시 예에 따른 반도체 소자의 금속 배선 형성방법은, 반도체 기판 내에 트렌치를 형성한 후 상기 트렌치가 매립되도록 전체 구조 상부에 구리막을 형성하는 단계와, 연마 공정을 실시하여 상부가 디싱(dishing)된 금속 배선을 형성하는 단계와, 상기 디싱된 금속 배선 상부에만 Sb2Te3를 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법을 제공한다.According to an embodiment of the present disclosure, a method of forming a metal wiring of a semiconductor device may include forming a trench in a semiconductor substrate and forming a copper film on the entire structure such that the trench is buried, and performing a polishing process on the top of the dish to form a dish. It provides a method for forming a metal wiring of a semiconductor device comprising the step of forming a dished metal wiring, and forming Sb 2 Te 3 only on the dished metal wiring.

본 발명의 일 실시 예에 따른 반도체 소자의 금속 배선 형성방법은, 반도체 기판 상부에 적층된 제1 절연막 및 제1 하드 마스크막을 식각하여 제1 트렌치를 형성한 후 상기 제1 트렌치가 매립되도록 전체 구조 상부에 제1 구리막을 형성하는 단계와, 연마 공정을 실시하여 상부가 디싱(dishing)된 제1 금속 배선을 형성한 후 상기 디싱된 제1 금속 배선 상부에만 Sb2Te3를 형성하는 단계와, 전체 구조 상부에 제1 유전체막, 제2 절연막, 제2 유전막, 제3 절연막 및 제2 하드 마스크막을 순차적으로 형성한 후 상기 제2 하드 마스크막, 제3 절연막, 제2 유전막, 제2 절연막 및 제1 유전막을 순차적으로 식각하여 듀얼 다마신 구조를 갖는 콘택홀 및 제2 트렌치를 형성하는 단계와, 상기 콘택홀 및 제2 트렌치가 매립되도록 전체 구조 상부에 제2 구리막을 형성한 후 연마 공정을 실시하여 상부가 디싱된 제2 금속 배선을 형성하는 단계와, 상기 디싱된 제2 금속 배선 상부에만 Sb2Te3를 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법을 제공한다. In the method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention, the first structure is formed by etching the first insulating film and the first hard mask layer stacked on the semiconductor substrate, and then forming the first trench to fill the first trench. Forming a first copper film on the upper surface, performing a polishing process to form a first metal wiring on which the top is dished, and then forming Sb 2 Te 3 only on the dished first metal wiring; A first dielectric film, a second insulating film, a second dielectric film, a third insulating film, and a second hard mask film are sequentially formed on the entire structure, and then the second hard mask film, the third insulating film, the second dielectric film, the second insulating film, and Sequentially etching the first dielectric layer to form a contact hole and a second trench having a dual damascene structure; forming a second copper layer on the entire structure to fill the contact hole and the second trench, and then polishing Conducting constant to provide a step, and the dishing of the second metal wiring formation method of a semiconductor device including forming a Sb 2 Te 3 only upper metal wiring to form a second metal interconnection of the upper dishing.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명의 일 실시 예에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.2A through 2F are cross-sectional views of devices sequentially illustrated to explain a method for forming metal wires of a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 소자분리막, 게이트, 소오스 콘택 플러그, 드레인 콘택 플러그 등 소정의 구조가 형성된 반도체 기판(100) 상부에 제1 절연막(102) 및 제1 하드 마스크막(104)을 순차적으로 형성한 후 사진 및 식각 공정을 이용하여 및 제1 하드 마스크막(104) 및 제1 절연막(102)을 식각하여 제1 금속배선 트렌치(106)를 형성한다. 이때, 제1 절연막(102)은 저유전 물질인 BCB로 형성하고, 제1 하드 마스크막(104)은 SiCN으로 형성한다. Referring to FIG. 2A, a first insulating layer 102 and a first hard mask layer 104 are sequentially formed on a semiconductor substrate 100 having a predetermined structure such as an isolation layer, a gate, a source contact plug, and a drain contact plug. The first metal wiring trench 106 is formed by etching the first hard mask film 104 and the first insulating film 102 using a photolithography and an etching process. In this case, the first insulating layer 102 is formed of BCB, which is a low dielectric material, and the first hard mask layer 104 is formed of SiCN.

도 2b를 참조하면, 제1 금속배선 트렌치(106) 내에 팔라듐(palladium; Pd)을 스퍼터링(sputtering) 방식으로 얇게 형성한 후 전체 구조 표면에 제1 베리어 메탈막(108)을 형성한다. 이때, 제1 베리어 메탈막(108)은 탄탈륨(Ta) 또는 탄탈륨질화막(TaN)으로 형성한다. 제1 금속배선 트렌치(106)가 매립되도록 전체 구조 상부에 제1 구리(Cu)막을 형성한다. 이때, 제1 구리(Cu)막은 전체 구조 상부에 물리기상 증착방법(Physical Vapor Deposition; PVD) 또는 화학기상 증착방법(Chemical Vapor Deposition; CVD)으로 구리 시드 층(Cu seed layer)을 먼저 형성한 후 전기 도금(electroplating) 방법을 실시하여 제1 금속배선 트렌치(106)를 매립한다. Referring to FIG. 2B, palladium (Pd) is thinly formed in the first metal wiring trench 106 by sputtering and then the first barrier metal layer 108 is formed on the entire structure surface. In this case, the first barrier metal film 108 is formed of tantalum (Ta) or tantalum nitride film (TaN). A first copper (Cu) film is formed on the entire structure so that the first metal wiring trench 106 is buried. At this time, the first copper (Cu) film is formed on the entire structure by first forming a copper seed layer (Cu seed layer) by physical vapor deposition (Physical Vapor Deposition; PVD) or chemical vapor deposition (CVD) The first metal wiring trench 106 is embedded by performing an electroplating method.

그런 다음, 제1 금속배선 트렌치(106) 내에만 제1 구리(Cu)막이 매립되도록 연마 공정을 실시하여 제1 금속배선(110)을 형성한다. 이때, 연마 공정시 제1 금속배선(110) 상부 영역이 디싱된다. Then, a polishing process is performed such that the first copper (Cu) film is embedded only in the first metal wiring trench 106 to form the first metal wiring 110. At this time, the upper region of the first metal wiring 110 is dished during the polishing process.

도 2c를 참조하면, 구리(Cu) 확산을 방지하기 위하여 전체 구조 상부에 Sb2Te3(112)를 형성한 후 디싱된 제1 금속배선(110) 상부에만 Sb2Te3(112)가 존재하도록 식각 공정을 실시한다.Referring to FIG. 2C, after forming Sb 2 Te 3 112 on the entire structure to prevent copper diffusion, Sb 2 Te 3 112 is present only on the dished first metal wire 110. The etching process is performed.

도 2d를 참조하면, 전체 구조 상부에 제1 유전체막(114), 제2 절연막(116), 제2 유전막(118), 제3 절연막(120) 및 제2 하드 마스크막(122)을 순차적으로 형성한 후 제2 하드 마스크막(122), 제3 절연막(120), 제2 유전막(118), 제2 절연막(116) 및 제1 유전막(114)을 순차적으로 식각하여 듀얼 다마신 구조를 갖는 콘택홀(124) 및 제2 트렌치를 형성한다. 이때, 제2 및 제3 절연막(116 및 120)은 저유전 물질인 BCB로 형성하고, 제2 하드 마스크막(122)은 SiCN으로 형성한다. Referring to FIG. 2D, the first dielectric film 114, the second insulating film 116, the second dielectric film 118, the third insulating film 120, and the second hard mask film 122 are sequentially disposed on the entire structure. After forming, the second hard mask layer 122, the third insulating layer 120, the second dielectric layer 118, the second insulating layer 116, and the first dielectric layer 114 are sequentially etched to have a dual damascene structure. The contact hole 124 and the second trench are formed. In this case, the second and third insulating layers 116 and 120 are formed of BCB, which is a low dielectric material, and the second hard mask layer 122 is formed of SiCN.

도 2e를 참조하면, 듀얼 다마신 구조를 갖는 콘택홀(124) 및 제2 트렌치 내에 팔라듐(Pd)을 스퍼터링(sputtering) 방식으로 얇게 형성한 후 전체 구조 표면에 제2 베리어 메탈막(126)을 형성한다. 이때, 제2 베리어 메탈막(126)은 탄탈륨(Ta) 또는 탄탈륨질화막(TaN)으로 형성한다. 듀얼 다마신 구조를 갖는 콘택홀(124) 및 제2 트렌치가 매립되도록 전체 구조 상부에 제2 구리(Cu)막(128)을 형성한다. 이때, 제2 구리(Cu)막(128)은 전체 구조 상부에 물리기상 증착방법(PVD) 또는 화학기상 증착방법(CVD)으로 구리 시드 층을 먼저 형성한 후 전기 도금법을 실시하여 콘택홀(124) 및 제2 트렌치를 매립한다. Referring to FIG. 2E, palladium (Pd) is thinly formed in the contact hole 124 having the dual damascene structure and the second trench by sputtering, and then the second barrier metal layer 126 is formed on the entire structure surface. Form. In this case, the second barrier metal film 126 is formed of tantalum (Ta) or tantalum nitride film (TaN). A second copper (Cu) film 128 is formed on the entire structure to fill the contact hole 124 and the second trench having the dual damascene structure. At this time, the second copper (Cu) film 128 is formed by first forming a copper seed layer on the entire structure by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and then performing electroplating to contact holes 124. ) And the second trench.

도 2f를 참조하면, 콘택홀(124) 및 제2 트렌치 내에만 제2 구리(Cu)막(128)이 매립되도록 연마 공정을 실시하여 제2 금속배선(130)을 형성한다. 이때, 연마 공정시 제2 금속배선(130) 상부 영역이 디싱된다. 구리(Cu) 확산을 방지하기 위하여 전체 구조 상부에 Sb2Te3(132)를 형성한 후 디싱된 제2 금속배선(130) 상부에만 Sb2Te3(132)가 존재하도록 식각 공정을 실시한다. 전체 구조 상부에 제3 유전체막(134) 및 패시베이션층(136)을 순차적으로 형성한다. Referring to FIG. 2F, the second metal wiring 130 is formed by performing a polishing process so that the second copper (Cu) film 128 is embedded only in the contact hole 124 and the second trench. At this time, the upper region of the second metal wiring 130 is dished during the polishing process. In order to prevent copper diffusion, Sb 2 Te 3 132 is formed on the entire structure, and an etching process is performed such that Sb 2 Te 3 132 exists only on the dished second metal wiring 130. . The third dielectric film 134 and the passivation layer 136 are sequentially formed on the entire structure.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명의 효과는 다음과 같다.As described above, the effects of the present invention are as follows.

첫째, 절연막으로 강한 저항력을 갖는 BCB 물질을 사용하고, 연마 공정 후 금속 배선 상부의 디싱 영역에 Sb2Te3를 형성함으로써 디싱 문제를 방지함과 동시에 산화 현상으로 인하여 구리와 산화막이 결합하는 것을 방지할 수 있을 뿐만 아니라, 구리 확산에 의한 보이드 발생을 방지할 수 있다. First, by using a BCB material having a strong resistance as an insulating film, and forming a Sb 2 Te 3 in the dishing area of the upper portion of the metal wiring after the polishing process to prevent the dishing problem and prevent the copper and the oxide film from bonding due to the oxidation phenomenon. Not only can this be done, but voids by copper diffusion can be prevented.

둘째, 메모리 소자의 금속 배선 형성과정에서 문제시되는 RC 딜레이를 줄여줌으로써 소자의 속도를 향상시키고, 소자의 신뢰성을 확보할 수 있다. Second, by reducing the RC delay which is a problem in the formation of the metal wiring of the memory device, it is possible to improve the speed of the device and secure the reliability of the device.

셋째, 금속 배선의 신뢰성 특성을 향상시켜 EM 및 SM 페일을 감소시키고, TDDB 특성을 향상시킴으로써 소자의 축소화가 가능하다. Third, it is possible to reduce the size of the device by improving the reliability characteristics of the metal wiring to reduce EM and SM fail, and improve the TDDB characteristics.

Claims (7)

반도체 기판 내에 트렌치를 형성한 후 상기 트렌치가 매립되도록 전체 구조 상부에 구리막을 형성하는 단계;Forming a trench in the semiconductor substrate and forming a copper film on the entire structure to fill the trench; 연마 공정을 실시하여 상부가 디싱(dishing)된 금속 배선을 형성하는 단계; 및Performing a polishing process to form a metal wiring having a top dished; And 상기 디싱된 금속 배선 상부에만 Sb2Te3를 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법.Forming Sb 2 Te 3 only on the dished metal wires; 반도체 기판 상부에 적층된 제1 절연막 및 제1 하드 마스크막을 식각하여 제1 트렌치를 형성한 후 상기 제1 트렌치가 매립되도록 전체 구조 상부에 제1 구리막을 형성하는 단계;Forming a first trench by etching the first insulating layer and the first hard mask layer stacked on the semiconductor substrate, and then forming a first copper layer on the entire structure to fill the first trench; 연마 공정을 실시하여 상부가 디싱(dishing)된 제1 금속 배선을 형성한 후 상기 디싱된 제1 금속 배선 상부에만 Sb2Te3를 형성하는 단계;Performing a polishing process to form a first metal interconnection on which the upper portion is dished and then forming Sb 2 Te 3 only on the dished first metal interconnection; 전체 구조 상부에 제1 유전체막, 제2 절연막, 제2 유전막, 제3 절연막 및 제2 하드 마스크막을 순차적으로 형성한 후 상기 제2 하드 마스크막, 제3 절연막, 제2 유전막, 제2 절연막 및 제1 유전막을 순차적으로 식각하여 듀얼 다마신 구조를 갖는 콘택홀 및 제2 트렌치를 형성하는 단계;A first dielectric film, a second insulating film, a second dielectric film, a third insulating film, and a second hard mask film are sequentially formed on the entire structure, and then the second hard mask film, the third insulating film, the second dielectric film, the second insulating film, and Sequentially etching the first dielectric layer to form a contact hole and a second trench having a dual damascene structure; 상기 콘택홀 및 제2 트렌치가 매립되도록 전체 구조 상부에 제2 구리막을 형성한 후 연마 공정을 실시하여 상부가 디싱된 제2 금속 배선을 형성하는 단계; 및Forming a second copper layer on the entire structure to fill the contact hole and the second trench, and then performing a polishing process to form a second metal wiring on which the upper portion is dished; And 상기 디싱된 제2 금속 배선 상부에만 Sb2Te3를 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법.And forming Sb 2 Te 3 only on the dished second metal wires. 제2항에 있어서, 상기 제1, 제2 및 제3 절연막은 저유전 물질인 BCB로 형성하고, 상기 제1 및 제2 하드 마스크막은 SiCN으로 형성하는 반도체 소자의 금속 배선 형성방법.The method of claim 2, wherein the first, second, and third insulating layers are formed of BCB, which is a low dielectric material, and the first and second hard mask layers are formed of SiCN. 제2항에 있어서, 상기 제1 트렌치를 형성한 후,The method of claim 2, wherein after forming the first trench, 상기 제1 트렌치 내에 팔라듐을 스퍼터링 방식으로 얇게 형성한 후 전체 구조 표면에 베리어 메탈막을 형성하는 단계를 더 포함하는 반도체 소자의 금속 배선 형성방법.And forming a barrier metal film on the entire structure surface of the first trench by thinly forming palladium in the first trench by sputtering. 제2항에 있어서, 상기 제1 구리막은 전체 구조 상부에 물리기상 증착방법 또는 화학기상 증착방법으로 구리 시드 층을 먼저 형성한 후 전기 도금법을 실시하여 상기 제1 트렌치를 매립하는 반도체 소자의 금속 배선 형성방법.3. The metal wiring of claim 2, wherein the first copper layer is formed by first forming a copper seed layer on the entire structure by a physical vapor deposition method or a chemical vapor deposition method, and then performing electroplating. Formation method. 제2항에 있어서, 상기 듀얼 다마신 구조를 갖는 콘택홀 및 제2 트렌치를 형성한 후,The method of claim 2, wherein after forming the contact hole and the second trench having the dual damascene structure, 상기 듀얼 다마신 구조를 갖는 콘택홀 및 제2 트렌치 내에 팔라듐을 스퍼터링 방식으로 얇게 형성한 후 전체 구조 표면에 베리어 메탈막을 형성하는 단계를 더 포함하는 반도체 소자의 금속 배선 형성방법.And forming a barrier metal layer on the entire structure surface of the contact structure having the dual damascene structure and thinly forming palladium in the second trench by sputtering. 제2항에 있어서, 상기 제2 구리막은 전체 구조 상부에 물리기상 증착방법 또는 화학기상 증착방법으로 구리 시드 층을 먼저 형성한 후 전기 도금법을 실시하여 상기 콘택홀 및 제2 트렌치를 매립하는 반도체 소자의 금속 배선 형성방법.The semiconductor device of claim 2, wherein the second copper layer is formed by first forming a copper seed layer on the entire structure by a physical vapor deposition method or a chemical vapor deposition method, and then performing electroplating to fill the contact hole and the second trench. Method of forming metal wiring.
KR1020060060363A 2006-06-30 2006-06-30 Method of forming a metal wire in a semiconductor device KR20080001905A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142452B2 (en) 2013-07-22 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask removal scheme
CN109427649A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US10734309B2 (en) 2014-11-03 2020-08-04 Samsung Electronics Co., Ltd. Semiconductor device having a trench with a convexed shaped metal wire formed therein

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142452B2 (en) 2013-07-22 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask removal scheme
US9373541B2 (en) 2013-07-22 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask removal scheme
US10734309B2 (en) 2014-11-03 2020-08-04 Samsung Electronics Co., Ltd. Semiconductor device having a trench with a convexed shaped metal wire formed therein
CN109427649A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109427649B (en) * 2017-08-24 2020-09-08 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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