KR20080091990A - Methods of forming interconnection structures of semiconductor devices and interconnection structures fabricated thereby - Google Patents

Abstract

A method for forming an interconnection structure of a semiconductor device and the interconnection structure fabricated thereby are provided to prevent an electric field at the topmost region of barrier metal layer patterns, keep conductive channels from being formed between the metal wires, and prevent diffusion of the metal ions by covering the metal wires and the diffusion barrier layer patterns with capping layers. A method for forming an interconnection structure of a semiconductor device comprises the steps of: forming an insulating layer(103) on a semiconductor substrate(101); etching a predetermined region of the insulating layer to form grooves(105); forming diffusion barrier layer patterns(107) covering inner walls of the grooves, and metal wires(109) filling spaces which are surrounded by the diffusion barrier layer patterns; removing upper regions of the diffusion barrier layer patterns selectively to form recessed diffusion barrier layer patterns; and forming capping layers(111) which cover the recessed diffusion barrier layer patterns and the metal wires. The recessed diffusion barrier layer patterns are formed by using a CMP method.

Description

FIELD OF THE INVENTION A method of forming a wiring structure of a semiconductor device and a wiring structure manufactured thereby.

1 is a cross-sectional view for explaining a method of forming a conventional wiring structure.

2A to 2E are cross-sectional views illustrating a method of forming a wiring structure according to the present invention.

The present invention relates to a method for forming a semiconductor integrated circuit and an integrated circuit, and more particularly, to a method for forming a wiring structure of a semiconductor device and a wiring structure manufactured thereby.

The semiconductor device includes individual elements such as transistors and conductive wires electrically connecting the individual elements to each other. As the degree of integration of the semiconductor device increases, the width of the conductive wires and the gap therebetween are gradually decreasing. As a result, the parasitic capacitance between the conductive wires as well as the electrical resistance of the conductive wires can be increased. In this case, the transmission speed of the electrical signals applied to the conductive wires may be slow due to the increase in the electrical resistance and parasitic capacitance of the conductive wires. Therefore, when the degree of integration of the semiconductor device is increased, there may be a limit in improving the operating speed of the semiconductor device.

Recently, in order to improve the RC delay of the electrical signal transmitted through the metal wires, a technique of forming the metal wires with a low resistivity metal film, for example, a copper film, has been widely used.

1 is a cross-sectional view for explaining a method of forming a conventional wiring structure.

Referring to FIG. 1, an intermetallic insulating film 3 is formed on a semiconductor substrate 1, and the intermetallic insulating film 3 is etched to form a pair of grooves having a predetermined depth and adjacent to each other. do. A barrier metal film and a copper film are sequentially formed on the substrate having the grooves, and the copper film and the barrier metal film are planarized using a chemical mechanical polishing (CMP) process to form an upper surface of the intermetallic insulating film 3. Expose As a result, barrier metal film patterns 5 remaining on the inner walls of the grooves and copper wirings 7 surrounded by the barrier metal film patterns 5 are formed.

The copper film may be recessed during the planarization process. As a result, upper surface edges of the copper wirings 7 may be lower than the uppermost regions T of the barrier metal film patterns 5, as shown in FIG. 1. In other words, the uppermost regions T of the barrier metal layer patterns 5 may protrude relatively from the upper edges of the copper wires 7.

Subsequently, an etch stop film 9 is formed on the substrate having the copper wirings 7 and the barrier metal film patterns 5. The etch stop layer 9 is formed of a silicon nitride film (SiN) or a silicon carbide nitride film (SiCN).

According to the above-described prior art, a time for measuring the reliability of the intermetallic insulating film 3 between the copper wirings 7 by continuously applying a high voltage of several tens of volts between the adjacent copper wirings 7 for a predetermined time. During a Time Dependent Dielectric Breakdown (TDDB) test, a strong electric field can be formed from the protrusion of the barrier metal film pattern 5. This strong electric field can promote the phenomenon that one of the copper wirings 7 diffuses toward the other copper wiring adjacent thereto to form a conductive channel between the copper wirings 7. have. The conductive channel may be formed at an interface between the intermetallic insulating layer 3 and the etch stop layer 9. The conductive channel may provide a leakage current path between the adjacent copper wirings 7 to cause a malfunction of the semiconductor device.

An object of the present invention is to provide a method for forming a wiring structure of a semiconductor device capable of suppressing diffusion of metal ions between adjacent metal wires.

Another object of the present invention is to provide a wiring structure of a semiconductor device suitable for suppressing diffusion of metal ions between adjacent metal wires.

According to one aspect of the present invention for achieving the above technical problem, a method for forming a wiring structure of a semiconductor device is provided. The wiring structure of the semiconductor device includes forming an insulating film on a semiconductor substrate. The groove is formed by etching a predetermined region of the insulating film. A diffusion barrier layer pattern covering the inner wall of the groove and a metal wiring filling the space surrounded by the diffusion barrier layer pattern are formed. The upper region of the diffusion barrier layer pattern adjacent to the upper surface of the insulating layer is selectively removed to form a recessed diffusion barrier layer pattern. A capping layer covering the recessed diffusion barrier layer pattern and the metal line is formed.

In some embodiments of the present invention, the recessed diffusion barrier layer pattern may be chemically mechanically polished using a slurry having a relatively high removal rate of the diffusion barrier layer pattern relative to the metal lines and the insulating layer. It may be formed using the Chemical Mechanical Polishing (CMP) method.

In another embodiment, the diffusion barrier layer pattern may include a tantalum (Ta) film, a tantalum nitride (TaN) film, a titanium (Ti) film, a titanium nitride (TiN) film, a titanium silicon nitride (TiSiN) film, and a tungsten nitride (WN) film. It may be one material film selected from the group consisting of a film or a film composed of a combination of these material films.

In another embodiment, a blocking layer may be formed on the insulating layer and the capping layer.

In another embodiment, when the diffusion barrier layer pattern is formed of tantalum (Ta) or tantalum nitride (TaN), the slurry may be a silica slurry having an OH content of 100 PPM or more.

In another embodiment, the capping layer may be one of a cobalt tungsten phosphide (CoWP) film, a cobalt tungsten boron (CoWB) film, a cobalt iron carbon (CoFC) film and a tungsten (W) film.

In another embodiment, the metal wires may be formed of copper wires.

According to another aspect of the present invention for achieving the above technical problem, there is provided a wiring structure of a semiconductor device. The wiring structure includes an insulating film formed on a semiconductor substrate. The insulating film has a groove having a predetermined depth. The groove is filled with metal wiring. A diffusion barrier film pattern recessed between the metal wiring and sidewalls of the groove is provided. The recessed diffusion barrier layer pattern has an upper surface lower than an upper surface of the metal wiring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

First, a method of forming a wiring structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2E.

2A to 2E are cross-sectional views illustrating a method of forming a wiring structure according to the present invention.

2A and 2B, an insulating film 103 is formed on the semiconductor substrate 101. The semiconductor substrate 101 may have individual elements such as transistors, resistors, and capacitors, and may have a circuit pattern inside the semiconductor substrate 101. The insulating film 103 may be formed using a process well known to those skilled in the art, for example, a chemical vapor deposition (CVD) process. The insulating layer 103 may be formed of a TEOS (Tetra Ethyl Ortho Silicate) film. A predetermined region of the insulating layer 103 is etched to form grooves 105 adjacent to each other.

A conventional deposition process is formed on the grooves 105 to form a diffusion barrier layer 107a covering the inner wall of each of the grooves 105. The diffusion barrier layer 107a includes a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, a titanium nitride (TiN) layer, a titanium silicon nitride (TiSiN) layer, and a tungsten nitride (WN) layer. It may be one material layer selected from the group. Alternatively, the diffusion barrier layer 107a may be a layer formed by sequentially stacking at least two material layers of the material layers.

A metal wiring layer 109a is formed to fill the space surrounded by the diffusion barrier layer 107a. In addition, the metal wiring layer 109a may be formed on the insulating layer 103. The metal wiring layer 109a may be formed using a process well known to those skilled in the art, for example, an electroplating method. In more detail, a lower seed layer is formed on the diffusion barrier layer 107a. The lower seed layer may be formed of one material selected from the group consisting of copper (Cu), platinum (Pt), palladium (Pd), nickel (Ni), silver (Ag), ruthenium (Au), and gold (Au). Can be. Alternatively, the lower seed layer may be formed by sequentially stacking at least two materials among the materials. Therefore, the metal wiring layer 109a can be formed on the lower seed layer by using an electroplating method. The metal wiring layer 109a can be formed using a metal, for example, copper (Cu).

Subsequently, a planarization process may be performed on the metal wiring layer 109a to expose the top surface A-A ′ of the insulating layer 103. The planarization process may be, for example, primary and secondary chemical mechanical planarization (CMP) processes. In more detail, the diffusion barrier layer 107a may be exposed by performing a first CMP process on the metal wiring layer 109a. The first CMP process may be performed to remove the metallization layer 109a at a rate of about 7000 kW / min. A secondary CMP process may be performed on the exposed diffusion barrier layer 107a to expose the insulating layer 103 by removing the diffusion barrier layer pattern 107a at a rate of about 3000 mA / min. In this case, the primary and secondary CMP processes can be performed using the same slurry. As a result, the metal interconnection layer 109a and the diffusion barrier layer 107a may be formed of the metal interconnection 109 and the diffusion barrier layer pattern 107b surrounding the interconnection layer 109b.

The metal wire 109 may be a wire used in a volatile memory device or a non-volatile memory device. When the metal wire 109 is used in a nonvolatile memory device, the metal wire 109 is a bit line for exchanging an electrical signal with an active region of a transistor formed in a flash memory device. Can be.

2C to 2E, a planarization process such as a chemical mechanical polishing (CMP) process for removing a portion of the diffusion barrier layer pattern 107b may be performed. The CMP process may be performed using a slurry having a relatively high removal rate of the diffusion barrier layer pattern 107b compared to the metal line 109 and the insulating layer 103. In an embodiment of the present invention, the slurry may be a silica slurry having a content of hydroxyl group (OH) of 100 parts per million (PPM) or more.

When the diffusion barrier layer pattern 107b is formed of tantalum (Ta) or tantalum nitride (TaN), the diffusion barrier layer pattern 107b includes a silica slurry having a content of hydroxyl group (OH) of 100 PPM or more. It can be removed at a rate of about 75nm / min through the CMP process used. In addition, when the metal wire 109 is formed of copper (Cu), the metal wire 109 may be removed at a speed slower than about 5 nm / min using the silica slurry. Therefore, the diffusion barrier layer pattern 107b may be removed relatively faster than the metal line 109. As a result, an upper surface of the diffusion barrier layer pattern 107b may be formed at a level lower than an upper surface of the metal wiring 109. That is, the diffusion barrier layer pattern 107b may be formed as a recessed diffusion barrier layer pattern 107. In addition, the recessed diffusion barrier layer pattern 107 may have a lower upper surface than the upper surface of the insulating layer 103.

The recessed diffusion barrier layer pattern 107 is located near the top regions T of the barrier metal layer patterns 5 during a Time Dependent Dielectric Breakdown (TDDB) test as shown in FIG. 1. This prevents the generation of strong electric fields. In other words, different voltages may be applied between the metal wires 109 adjacent to each other during the time-dependent insulation breakdown test. In this case, an electric field may be formed from the metal wiring to which the high voltage is applied to the adjacent metal wiring to which the low voltage is applied.

The electric field is formed in the top regions T of the barrier metal film patterns 5 as shown in FIG. 1, and a conductive channel is formed between the barrier metal film patterns adjacent to each other by the electric field. Can be formed. As a result, leakage currents may occur along the conduction channel even when atoms constituting the barrier metal layer patterns are diffused along the conductive channel so that a low voltage is applied to the barrier metal layer patterns. However, as shown in FIG. 2C of the present invention, the recessed diffusion barrier layer pattern 107 may prevent the electric field from being strongly formed at the top surface. As a result, the recessed diffusion barrier layer pattern 107 may prevent a conductive channel from being formed between the metal lines 109 adjacent to each other.

Subsequently, a capping layer 111 is formed on the recessed diffusion barrier layer pattern 107 and the metal line 109. The capping layer 111 may be formed by a process well known to those skilled in the art, for example, using an electroless plating method or a selective chemical vapor deposition (CVD) method. The capping layer 111 may be one of a cobalt tungsten phosphide (CoWP) film, a cobalt tungsten boron (CoWB) film, a cobalt iron carbon (CoFC) film, and a tungsten (W) film. An etch stop layer 113 may be formed on the semiconductor substrate 111 having the capping layer 111. The etch stop layer 113 may be formed using a silicon nitride (SiN) film or a silicon carbonitride (SiCN) film. As a result, the capping layer 111 and the etch stop layer 113 may prevent the metal line 109 from directly contacting the insulating layer 103. In addition, although not illustrated, the etch stop layer 113 may be used as an etch stopper while forming an interlayer insulating layer on the etch stop layer 113 and partially etching the interlayer insulating layer.

Hereinafter, a wiring structure according to an exemplary embodiment of the present invention will be described with reference to FIG. 2E again.

Referring again to FIG. 2E, an insulating film 103 is provided on the semiconductor substrate 101. The insulating layer 103 includes a groove 105 that exposes a predetermined region of the semiconductor substrate 101. The semiconductor substrate 101 may have transistors, resistors, and capacitors, and may also have circuit patterns. Metal wiring 109 is provided to fill the interior of the groove 105. The metal wiring 109 may be formed using copper wiring. Meanwhile, a diffusion barrier film pattern 107 recessed between the groove 105 and the metal wiring 109 is interposed. In addition, the recessed diffusion barrier layer pattern 107 may be interposed between the semiconductor substrate 101 and the metal wiring 109.

In this case, the recessed diffusion barrier layer pattern 107 has an upper surface having a level lower than that of the metal line 109. In addition, the recessed diffusion barrier layer pattern 107 may have an upper surface having a level lower than that of the insulating layer 103. The recessed diffusion barrier layer pattern 107 includes a tantalum (Ta) film, a tantalum nitride (TaN) film, a titanium (Ti) film, a titanium nitride (TiN) film, a titanium silicon nitride (TiSiN) film, and a tungsten nitride (WN) film. It may be one material film selected from the group consisting of a film. Alternatively, the recessed diffusion barrier layer pattern 107 may be a layer in which at least two material layers of the material layers are sequentially stacked.

A capping layer 111 is provided to cover the top surface of the recessed diffusion barrier layer pattern 107 and the metal line 109. The capping film may be any one selected from a cobalt tungsten phosphide (CoWP) film, a cobalt tungsten boron (CoWB) film, a cobalt iron carbon (CoFC) film, and a tungsten (W) film. An etch stop layer 113 may be provided on the semiconductor substrate 101 having the insulating layer 103 and the capping layer 111. The etch stop layer 113 may be formed of a silicon nitride (SiN) layer or a silicon carbonitride (SiCN) layer. As a result, the capping layer 111 and the etch stop layer 133 may prevent the metal wire 109 and the insulating layer 103 from directly contacting each other.

According to the present invention as described above, the diffusion barrier film pattern recessed between the metal wiring and the insulating film is provided. A capping film covering the metal line and the recessed diffusion barrier layer pattern is provided. The recessed diffusion barrier film pattern may prevent the electric field from increasing in the vicinity of the top regions of the barrier metal film patterns as described in the prior art during a time dependent dielectric breakdown (TDDB) test. Accordingly, the recessed diffusion barrier layer pattern may prevent the formation of a conductive channel between the metal lines. As a result, the recessed diffusion barrier layer pattern may prevent diffusion of metal ions between the metal wires adjacent to each other, thereby increasing reliability of the semiconductor device.

Claims (12)

An insulating film is formed on the semiconductor substrate, Etching a predetermined region of the insulating film to form a groove, Forming a diffusion barrier layer pattern covering an inner wall of the groove and a metal wiring filling a space surrounded by the diffusion barrier layer pattern, Selectively removing an upper region of the diffusion barrier layer pattern adjacent the upper surface of the insulating layer to form a recessed diffusion barrier layer pattern, And forming a capping layer covering the recessed diffusion barrier layer pattern and the metal interconnection. The method of claim 1, The recessed diffusion barrier layer pattern may be formed using a chemical mechanical polishing (CMP) using a slurry having a relatively high removal rate of the diffusion barrier layer pattern relative to the metal lines and the insulating layer. The formation method of the wiring structure characterized by forming using the method. The method of claim 1, The diffusion barrier layer pattern includes a group consisting of a tantalum (Ta) film, a tantalum nitride (TaN) film, a titanium (Ti) film, a titanium nitride (TiN) film, a titanium silicon nitride (TiSiN) film, and a tungsten nitride (WN) film. A method of forming a wiring structure, characterized in that the film is made of one material film selected from or a combination of these material films. The method of claim 1, And forming a blocking film on the insulating film and the capping film. The method of claim 2, When the diffusion barrier film pattern is formed of tantalum (Ta) or tantalum nitride (TaN), the slurry is a silica slurry having an OH content of 100 PPM or more. The method of claim 1, And the capping film is one of a cobalt tungsten phosphide (CoWP) film, a cobalt tungsten boron (CoWB) film, a cobalt iron carbon (CoFC) film, and a tungsten (W) film. The method of claim 1, And the metal wiring is formed of copper wiring. An insulating film formed on the semiconductor substrate and having a groove having a predetermined depth; A metal wiring filling the groove; A recessed diffusion barrier layer pattern provided between the metal interconnection and the sidewalls of the groove, the recessed diffusion barrier layer pattern having an upper surface lower than an upper surface of the metal interconnection; And And a capping layer covering the recessed diffusion barrier layer pattern and the metal line. The method of claim 8, And a blocking film provided on the insulating film and the capping film. The method of claim 8, The recessed diffusion barrier layer pattern includes a tantalum (Ta) film, a tantalum nitride (TaN) film, a titanium (Ti) film, a titanium nitride (TiN) film, a titanium silicon nitride (TiSiN) film, and a tungsten nitride (WN) film. A wiring structure, characterized in that the film is made of one material film selected from the group consisting of or a combination of these material films. The method of claim 8, The capping film is a wiring structure, characterized in that any one selected from a cobalt tungsten phosphide (CoWP) film, cobalt tungsten boron (CoWB) film, cobalt iron carbon (CoFC) film and tungsten (W) film. The method of claim 8, The metal wiring is a wiring structure, characterized in that the copper wiring.

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