JP2012080133A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of reducing capacitance between wiring lines of a semiconductor device, and implementing a countermeasure against misalignment vias.SOLUTION: The manufacturing method of a semiconductor device comprises processes of: forming insulator films 74 in space areas on wiring lines and between wiring lines; removing the insulator films 74 in regions other than the peripheral regions of through holes which expose the top face of wiring lines whose intervals between adjacent wiring lines are narrow while leaving the insulator films 74 in the peripheral regions as reservoirs; and forming insulator films 77 on the wiring lines while leaving gaps in the space areas between the wiring lines where the insulator films 74 are removed.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a technology effective when applied to a semiconductor device having a wiring including a main conductor film containing copper as a main component.

  The embedded wiring structure has Damascene technology (Single-Damascene technology and Dual-Damascene technology) in wiring openings such as wiring trenches and holes formed in insulating films. It is formed by embedding a wiring material by a so-called wiring forming technique. However, when the main wiring material is copper (Cu), copper is more easily diffused into the insulating film than a metal such as aluminum (Al), so the embedded wiring made of copper is directly connected to the insulating film. By covering the surface (bottom surface and side surface) of the embedded wiring with a thin barrier metal film so as not to contact, copper in the embedded wiring is suppressed or prevented from diffusing into the insulating film. Further, by forming a barrier insulating film for wiring cap made of, for example, a silicon nitride film on the upper surface of the insulating film in which the wiring opening is formed, the copper in the embedded wiring is buried. The diffusion from the upper surface of the embedded wiring into the insulating film is suppressed or prevented.

  In recent years, the interval between such embedded wirings has been reduced as semiconductor devices are highly integrated. As a result, the parasitic capacitance between the wirings increases, causing a signal delay, and crosstalk occurs between adjacent wirings. For this reason, it is desired to reduce the parasitic capacitance between the wirings. In order to reduce the parasitic capacitance between the wirings, a low dielectric constant material is used as the insulating film between the wirings. For example, Patent Document 1 discloses a technique in which wirings are formed in an inversely tapered shape, and an interlayer insulating film is formed so that an air gap is formed in a space between the wirings. By this air gap, the wiring capacitance is reduced. As another technique for forming an air gap between wirings, there is Patent Document 2.

JP 2001-85519 A JP 2003-297918 A

However, according to the examination results of the present inventors, it has been found that the embedded wiring technology using the copper as the main conductor layer has the following problems.
When copper is used as a wiring material, there is a problem that a TDDB (Time Dependence on Dielectric Breakdown) life is significantly shorter than other metal materials (for example, aluminum and tungsten). Furthermore, in addition to the trend toward finer wiring pitches and increased effective electric field strength, in recent years, insulating materials having a dielectric constant lower than that of silicon oxide have been used as insulating films between wirings in order to reduce wiring capacitance. However, since an insulating film having a low dielectric constant generally has a low withstand voltage, it is increasingly difficult to ensure the TDDB life.

  The deterioration of the TDDB life is generally considered that copper applied to the wiring material diffuses to the periphery, which reduces the dielectric breakdown voltage between the wirings. For example, Patent Document 1 does not consider the barrier metal film and the barrier insulating film at all. For this reason, even if the inter-wiring capacitance is reduced due to the air gap of the interlayer insulating film, copper used as the wiring material diffuses into the interlayer insulating film and the TDDB life is reduced. Further, since the air gap is formed by giving the wiring an inverse taper, the electric field concentrates on the upper end portion of the wiring, and the TDDB life is further reduced. Further, Patent Document 1 does not disclose the formation of vias connected to wiring.

  Patent Document 2 discloses a technique for taking measures against deterioration of the TDDB life. However, in Patent Document 2, no countermeasures against misalignment and vias are taken into consideration, and an alignment device with a wiring is generated at the through hole position for forming the via by an exposure apparatus in the lithography process, and the lower part of the through hole is formed. When the air gap exists, the cleaning solution or the Cu plating solution permeates thereafter, causing problems such as poor electrical connection and increased capacity.

An object of the present invention is to provide a semiconductor device capable of improving the dielectric breakdown resistance between wirings using copper as a main conductor layer, and a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor device capable of reducing the capacitance between wirings using copper as a main conductor layer and a method for manufacturing the same while taking measures against misalignment vias (vias misaligned). The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A manufacturing method of a semiconductor device according to the present invention includes the following steps.
(A) forming a plurality of wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductor film on the first insulating film including each of the plurality of wiring grooves;
(C) forming a wiring made of the first conductive film inside each of the plurality of wiring grooves by removing the first conductive film outside the plurality of wiring grooves;
(D) The first insulating film in the lower region of the through hole that exposes the upper surface of the wiring to be formed in a later step and the peripheral region thereof are left, and the first insulating film other than the regions is removed. Process,
(E) forming a second insulating film on the wiring while leaving a gap in the space region between the wirings from which the first insulating film has been removed;
(F) forming a through hole penetrating the second insulating film above the wiring;
(G) A step of forming a second conductor film inside the through hole.

A manufacturing method of a semiconductor device according to the present invention includes the following steps.
(A) forming a plurality of wiring grooves in the first insulating film on the semiconductor substrate;
(B) forming a first conductor film on the first insulating film including each of the plurality of wiring grooves;
(C) forming a wiring made of the first conductor film inside each of the plurality of wiring grooves by removing the first conductor film outside the plurality of wiring grooves by a CMP method;
(D) forming a first barrier insulating film on the first insulating film and the plurality of wirings;
(E) The first barrier insulating film and the first insulating film in the lower region of the through hole exposing the upper surface of the wiring formed in a later step and the peripheral region, and the first insulating film are left, and the regions other than the respective regions Removing the first barrier insulating film and the first insulating film;
(F) forming a second barrier insulating film on the first barrier insulating film and on a side surface and an upper surface of the wiring;
(G) forming a second insulating film on the second barrier insulating film while leaving a gap in the space region between the wiring from which the first barrier insulating film and the first insulating film have been removed; Process,
(H) forming a through hole penetrating the first barrier insulating film, the second barrier insulating film, and the second insulating film above the wiring;
(I) A step of forming a second conductor film inside the through hole.

A manufacturing method of a semiconductor device according to the present invention includes the following steps.
(A) forming a first conductor film on the semiconductor substrate;
(B) forming a plurality of first wirings by selectively removing the first conductor film by a dry etching method using a photoresist pattern as a mask;
(C) forming a first insulating film on the wiring and in a space region between the wiring;
(D) The first insulating film in the lower region of the through hole that exposes the upper surface of the wiring to be formed in a later step and the peripheral region thereof are left, and the first insulating film other than the regions is removed. Process,
(E) forming a second insulating film on the wiring while leaving a gap in the space region between the wirings from which the first insulating film has been removed;
(F) forming a through hole penetrating the first insulating film and the second insulating film above the wiring;
(G) A step of forming a second conductor film inside the through hole.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
The dielectric breakdown resistance between the wirings can be improved, and the capacitance between the wirings can be reduced while taking measures against misalignment vias (aligned vias).

It is a top view of the layout of the semiconductor device which is one embodiment of this invention. 2 is a fragmentary plan view taken along line AA of FIG. 1 during the manufacturing process of the semiconductor device according to the embodiment of the present invention; FIG. It is sectional drawing of the AA line of FIG. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; It is a top view of the AA line of FIG. FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing step following that of FIG. 7; FIG. 12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 11. FIG. 13 is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 12. FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 14 is an essential part cross sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing step following FIG. 13; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 10 and 15; It is a top view of the AA line of FIG. FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; It is a top view of the AA line of FIG. FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing step following that of FIG. 3; FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38; FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39; FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  First, the cause of deterioration of the TDDB life between the embedded wirings using the above copper as the main conductor layer studied by the present inventors will be described. The TDDB (Time Dependence on Dielectric Breakdown) lifetime is a measure for objectively measuring the time dependency of dielectric breakdown, and is relatively high between electrodes under a predetermined temperature (eg, 140 ° C.) measurement condition. Create a graph in which the time from voltage application to dielectric breakdown is plotted against the applied electric field by applying voltage, and the time (lifetime) obtained by extrapolating from this graph to the actual electric field strength (for example, 0.2 MV / cm) ).

  The deterioration of the TDDB life is generally considered that copper applied to the wiring material diffuses to the periphery, which reduces the dielectric breakdown voltage between the wirings. However, according to the examination results by the present inventors, the following factors are dominant in the copper diffusion phenomenon. That is, first, in copper diffused in the insulating film between adjacent wirings, ionized copper supplied from copper oxide (CuO) or copper silicide drifts and diffuses at the potential between the wirings rather than atomic copper. The factor is dominant. Second, the copper diffusion path is dominated by the interface between the insulating film on which the copper wiring is formed and the wiring cap film (barrier insulating film). From these facts, it was found that the deterioration of the TDDB life is due to the following mechanism.

That is, copper oxide (CuO) is formed on the surface of the embedded wiring using copper as a main conductor film by a surface process after CMP, and copper silicide (CuSi) is formed when a cap film (silicon nitride film) is formed. _x ) is formed. Such copper oxide or copper silicide is easily ionized as compared with pure copper. The copper ionized in this way is drifted by the electric field between the wirings and diffused into the insulating film between the wirings. On the other hand, the interface between the insulating film (silicon oxide film) and the cap film (silicon nitride film) forming the embedded wiring is discontinuous due to the formation of a lot of CMP damage, organic matter or dangling bonds. poor. The presence of such dangling bonds has an effect of promoting the diffusion of the copper ions, and the copper ions are drifted and diffused along the interface. That is, a leak path is formed at the interface between the wirings. The leakage current flowing through the leakage path is also subjected to a long-term leakage action and thermal stress due to the current, and then the current value increases at an accelerated rate, leading to dielectric breakdown (decrease in TDDB life).

  Therefore, in the present embodiment, it has been studied to improve the TDDB characteristics by eliminating the CMP surface (surface polished by CMP) that is an interface acting as a leak path from between the same-layer wirings. In addition, measures were taken to prevent misaligned vias and to reduce parasitic capacitance between wires.

  The semiconductor device of this embodiment and its manufacturing process will be described with reference to the drawings. FIG. 1 is a plan view of a layout of an integrated circuit chip 9 which is an embodiment of the present invention. A general integrated circuit includes a dense pattern portion 19a such as a RAM (Random Access Memory) and a sparse pattern portion 19b including peripheral circuits. In the dense pattern portion 19a, wiring patterns, contacts, and through holes are dense. On the other hand, the sparse pattern portion 19b has a feature that there is a relatively large space between wirings, and the number of through holes to be connected is smaller than that of the dense pattern portion 19a.

FIG. 2 is a plan view of an essential part during a manufacturing process of a semiconductor device according to an embodiment of the present invention, for example, CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor), and is a plan view excerpted from AA in FIG. FIG. 3 is a cross-sectional view taken along the line AA in FIG.
As shown in FIGS. 2 and 3, a wafer or semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, has an element isolation region 2 formed on its main surface. The element isolation region 2 is made of silicon oxide or the like, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method.

  A p-type well 3 and an n-type well 4 are formed in the semiconductor substrate 1 from the main surface to a predetermined depth. The p-type well 3 is formed by ion-implanting impurities such as boron, and the n-type well 4 is formed by ion-implanting impurities such as phosphorus.

  In the p-type well 3 region, an n-channel MISFET (Qn) is formed in the active region surrounded by the element isolation region 2. In the region of the n-type well 4, a p-channel type MISFET (Qp) is formed in the active region surrounded by the element isolation region 2. The gate insulating film 5 of the n-type MISFET (Qn) and the p-type MISFET (Qp) is made of, for example, a thin silicon oxide film or a silicon oxynitride film, and is formed by, for example, a thermal oxidation method.

For the gate electrode 6 of the n-type MISFET (Qn) and the p-type MISFET (Qp), for example, a titanium silicide (TiSi _x ) layer or a cobalt silicide (CoSi _x ) layer 10 is laminated on a low-resistance polycrystalline silicon film. It is formed by. On the side wall of the gate electrode 6, a side wall spacer or side wall 7 made of, for example, silicon oxide is formed.

  The n-type semiconductor region 8 which is the source and drain regions of the n-type MISFET (Qn) is formed, for example, with phosphorus in the regions on both sides of the gate electrode 6 and the sidewall 7 of the p-type well 3 after the sidewall 7 is formed. These impurities are formed by ion implantation. The p-type semiconductor region 9, which is the source and drain region of the p-type MISFET (Qp), includes, for example, boron in the regions on both sides of the gate electrode 6 and the sidewall 7 of the n-type well 4 after the sidewall 7 is formed. These impurities are formed by ion implantation. A silicide layer 10 such as a titanium silicide layer or a cobalt silicide layer is formed on part of the upper surface of the n-type semiconductor region 8 and the p-type semiconductor region 9.

  A silicon nitride film 11 is formed on the semiconductor substrate 1 so as to cover the gate electrode 6 and the sidewalls 7. The insulating film 12 is made of a highly reflowable insulating film capable of filling a narrow space between the gate electrodes 6, for example, a BPSG (Boron-doped Phospho Silicate Glass) film. A contact hole 13 is formed in the insulating film 12. At the bottom of the contact hole 13, part of the main surface of the semiconductor substrate 1, for example, part of the n-type semiconductor region 8 and p-type semiconductor region 9, part of the gate electrode 6, and the like are exposed.

  A conductive film made of tungsten (W) or the like is formed in the contact hole 13. For example, after forming a titanium nitride film, a tungsten film is formed by CVD (Chemical Vapor Deposition) so as to fill the contact hole 13 on the titanium nitride film, and an unnecessary tungsten film and titanium nitride film on the insulating film 12 are CMPed. It is formed by removing by (Chemical Mechanical Polishing) method or etch back method.

  On the insulating film 12 in which the through hole 13 is embedded, a groove is formed in an interlayer insulating film made of, for example, an insulating film 14a and an insulating film 14b, and then a conductive film made of tungsten or the like is embedded by a CMP (Chemical Mechanical Polishing) method. The first layer wiring 15 is formed by a damascene method that is manufactured by removing the excess conductor film. The first layer wiring 15 is electrically connected to the semiconductor regions 8 and 9 for the source / drain of the n-type MISFET (Qn) and p-type MISFET (Qp) and the gate electrode 6 through the through hole 13. The first layer wiring 15 is not limited to tungsten and can be variously modified. For example, a single film such as aluminum (Al) or an aluminum alloy, or titanium (Ti) or titanium nitride (at least one of upper and lower layers of these single films) is used. A laminated metal film in which a metal film such as TiN) is formed may be used.

When the groove is processed by the damascene method, the insulating film 14a has a role as an etching stopper film and can reduce resistance variation. As the insulating film 14a, for example, a silicon nitride (Si _x N _y ) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film may be used. These silicon nitride film, silicon carbide film, or silicon carbonitride film can be formed by, for example, a plasma CVD method. As a silicon carbide film formed by the plasma CVD method, for example, there is BLOk (manufactured by AMAT, relative permittivity = 4.3 to 5.0). In the formation, for example, a mixed gas of trimethylsilane and helium (or N ₂ , NH ₃ ) is used.
A silicon oxide film (for example, a TEOS (Tetraethoxysilane) oxide film) is used for the insulating film 14b. Further, in order to reduce the capacitance between wirings, the insulating film 14b is made of a low dielectric constant material (so-called Low-K insulating film, Low-K material) such as organic polymer or organic silica glass. Note that the low dielectric constant insulating film (Low-K insulating film) can be exemplified by an insulating film having a dielectric constant lower than that of a silicon oxide film (eg, TEOS (Tetraethoxysilane) oxide film) included in the passivation film. . Generally, the dielectric constant ε = 4.1 to 4.2 or less of the TEOS oxide film is called an insulating film having a low dielectric constant.

  Examples of the organic polymer as the low dielectric constant material include SiLK (manufactured by The Dow Chemical Co., USA, relative dielectric constant = 2.7, heat resistant temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0 to 5.0 MV / Vm). ) Or FLARE of polyallyl ether (PAE) material (manufactured by Honeywell Electronic Materials, relative permittivity = 2.8, heat-resistant temperature = 400 ° C. or higher). This PAE material is characterized by high basic performance and excellent mechanical strength, thermal stability and low cost. Examples of the organic silica glass (SiOC-based material) as the low dielectric constant material include, for example, HSG-R7 (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.8, heat resistant temperature = 650 ° C.), Black Diamond (Applied Materials, USA) Inc., relative dielectric constant = 3.0 to 2.4, heat-resistant temperature = 450 ° C.) or p-MTES (manufactured by Hitachi Development Co., Ltd., relative dielectric constant = 3.2). Other SiOC materials include, for example, CORAL (manufactured by Novellus Systems, Inc., relative permittivity = 2.7 to 2.4, heat-resistant temperature = 500 ° C.), Aurora 2.7 (manufactured by Japan ASM Co., Ltd.) , Relative dielectric constant = 2.7, heat-resistant temperature = 450 ° C.).

  Other low dielectric constant materials for the insulating film 14b include, for example, FSG (SiOF-based material), HSQ (hydrogen silsesquioxane) -based material, MSQ (methyl silsesquioxane) -based material, porous HSQ-based material, porous MSQ material, or porous organic material. A system material can also be used. Examples of the HSQ-based material include OCD T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 3.4 to 2.9, heat-resistant temperature = 450 ° C.), FOx (manufactured by Dow Corning Corp., USA), dielectric constant = 2.9) or OCL T-32 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.5, heat-resistant temperature = 450 ° C.). Examples of the MSQ material include OCD T-9 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.7, heat-resistant temperature = 600 ° C.), LKD-T200 (manufactured by JSR, relative dielectric constant = 2.7-2. 5, heat-resistant temperature = 450 ° C., HOSP (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.5, heat-resistant temperature = 550 ° C.), HSG-RZ25 (manufactured by Hitachi Chemical, relative dielectric constant = 2.5, heat-resistant Temperature = 650 ° C.), OCL T-31 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 2.3, heat-resistant temperature = 500 ° C.) or LKD-T400 (manufactured by JSR, dielectric constant = 2.2-2, heat-resistant temperature) = 450 ° C.).

Examples of the porous HSQ material include XLK (manufactured by Dow Corning Corp., relative dielectric constant = 2.5-2), OCL T-72 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2-1.9). , Heat resistant temperature = 450 ° C), Nanoglass (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.2 to 1.8, heat resistant temperature = 500 ° C or higher) or MesoELK (US Air Products and Chemicals, Inc, relative dielectric constant = 2) There are following). Examples of the porous MSQ material include HSG-6221X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.4, heat-resistant temperature = 650 ° C.), ALCAP-S (manufactured by Asahi Kasei Kogyo Co., Ltd., relative dielectric constant = 2.3-1). .8, heat resistant temperature = 450 ° C.), OCLT-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2 to 1.9, heat resistant temperature = 600 ° C.), HSG-6210X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant) = 2.1, heat-resistant temperature = 650 ° C.) or silica aerogel (manufactured by Kobe Steel, relative dielectric constant: 1.4 to 1.1). Examples of the porous organic material include PolyELK (US Air Products and Chemicals, Inc., dielectric constant = 2 or less, heat-resistant temperature = 490 ° C.). The SiOC material and the SiOF material are formed by, for example, a CVD method. For example, the Black Diamond is formed by a CVD method using a mixed gas of trimethylsilane and oxygen. The p-MTES is formed by, for example, a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. The other low dielectric constant insulating materials are formed by, for example, a coating method.

When such a Low-K material is used, an insulating film for a Low-K cap may be necessary on the insulating film 14b. As the insulating film for the Low-K cap, for example, a silicon oxide (SiO _x ) film typified by silicon dioxide (SiO ₂ ) or a pSiOC film having a relatively high film strength is used. These Low-k cap films have functions such as ensuring the mechanical strength of the insulating film 14b, surface protection, and ensuring moisture resistance during the CMP process.

  There is a through-hole interlayer structure composed of insulating films 16 and 17 above the first layer wiring, and the insulating films 16 and 17 are the same as the insulating films 14a and 14b, as in the case of manufacturing the first layer wiring. And can be made of materials. The insulating films 16 and 17 are formed with vias or through holes 18 in which a part of the first layer wiring 15 is exposed. A conductive film made of tungsten or the like is embedded in the through hole 18.

  4 to 6 are fragmentary cross-sectional views of the semiconductor device during the manufacturing process subsequent to FIG. For easy understanding, the portions corresponding to the structure below the insulating film 17 in FIG. 3 are not shown in FIGS.

First, in the present embodiment, as shown in FIG. 4, the insulating film 20 is formed on the insulating film 17 in which the through holes 18 are buried by a plasma CVD method or the like. The insulating film 20 is made of, for example, a silicon nitride film formed by a plasma CVD method, and the thickness thereof is, for example, about 25 nm to 50 nm. As another material of the insulating film 20, for example, a silicon carbide film formed by a plasma CVD method, a SiCN film formed by a plasma CVD method, or a single film of a silicon oxynitride (SiON) film formed by a plasma CVD method is used. May be. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. An example of the silicon carbide film formed by the plasma CVD method is the BLOk (manufactured by AMAT). In forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH ₃ ), and trimethylsilane (3MS) is used. Moreover, as a silicon oxynitride film formed by the plasma CVD method, for example, there is PE-TMS (manufactured by Canon, dielectric constant = 3.9), and in the formation thereof, for example, trimethoxysilane (TMS) gas and nitrogen oxide are used. A mixed gas with (N ₂ O) gas is used.

  Next, an insulating film 21 is formed on the insulating film 20. For the insulating film 21, the Low-K material, for example, a Low-K insulating film such as a SiOF film or a SiOC film is used. Further, for example, a silicon oxide film or the like is used for the insulating film 22 that forms a cap on the insulating film 21. In order to simplify the process, it is possible to omit the insulating film 22 and use a silicon oxide or SiOC film alone for the insulating film 21.

  Next, an antireflection film 23 and a photoresist film are sequentially formed on the insulating film 22, and the photoresist film is patterned by exposure to form a photoresist pattern 24. Then, the antireflection film 23 is selectively removed by a dry etching method using the photoresist pattern 24 as an etching mask. Thereafter, the insulating films 22 and 21 are selectively removed by a dry etching method using the photoresist pattern 24 as an etching mask to form an opening. Then, ashing is performed to remove the photoresist pattern 24 and the antireflection film 23 by ashing, and finally the insulating film 20 exposed from the openings of the insulating films 22 and 21 is etched. Thereby, as shown in FIG. 5, an opening or a wiring groove 25 is formed. The upper surface of the plug 18 is exposed from the bottom surface of the wiring groove 25. The insulating films 20, 21 and 22 are selectively removed by dry etching using the photoresist pattern 24 as an etching mask to form openings or wiring grooves 25, and then the photoresist pattern 24 and the antireflection film 23 are formed. Can also be removed.

  Next, as shown in FIG. 6, a thin conductive barrier film (first conductor film) 26 a made of, for example, titanium nitride (TiN) or the like and having a thickness of about 5 to 50 nm is sputtered on the entire main surface of the substrate 1. It is formed using a method. The conductive barrier film 26a has, for example, a function of preventing diffusion of copper for forming a main conductor film, which will be described later, and a function of improving the wettability of copper when the main conductor film is reflowed. As the material of the conductive barrier film 26a, refractory metal nitride such as tungsten nitride (WN) or tantalum nitride (TaN) that hardly reacts with copper can be used instead of titanium nitride. Further, as a material of the conductive barrier film 26a, a material obtained by adding silicon (Si) to refractory metal nitride, tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten ( It is also possible to use a TaN / Ta multilayer barrier in which a high melting point metal such as a (TiW) alloy or the like, or TaN having good adhesion to an insulating film and Ta having good wettability with Cu are combined.

  Subsequently, a main conductor film (second conductor film) 26b made of relatively thick copper having a thickness of, for example, about 800 to 1600 nm is formed on the conductive barrier film 26a. The main conductor film 26b can be formed using, for example, a CVD method, a sputtering method, a plating method, or the like. Thereafter, the main conductor film 26b is reflowed by performing a heat treatment on the substrate 1 in a non-oxidizing atmosphere (for example, a hydrogen atmosphere or a nitrogen atmosphere) at about 150 to 400 ° C. Embed without.

  Next, the main conductor film 26b and the conductive barrier film 26a are polished by the CMP method. Thereby, as shown in FIG. 6, a second layer wiring (wiring) 26 composed of a relatively thin conductive barrier film 26 a and a relatively thick main conductor film 26 b is formed in the wiring groove 25. The second layer wiring 26 is electrically connected to the first layer wiring 15 through the plug 18.

  FIG. 7 shows a plan view of the main part of the region corresponding to FIG. In FIG. 7, the second layer wiring 26 and the formation position 27 of the through hole connected to the second layer wiring and the upper layer are shown. If this through-hole position is misaligned by the exposure device in the lithography process and there is a gap (air gap) below the through-hole, then the cleaning solution or Cu plating solution will not penetrate, resulting in poor electrical connection. And cause capacity increase problems. Therefore, in order to take measures against this misaligned through hole (misalignment through hole), even if misalignment occurs, a reservoir of an insulating film exists under the via so that it is in the same state as the normal interlayer structure. The reservoir forming position 28 needs to be set. The reservoir forming method will be described with reference to FIG.

FIG. 8 is a cross-sectional view taken along the line AA of FIG. In FIG. 8 as well, the portion corresponding to the structure below the insulating film 17 in FIG. 3 is not shown. A barrier insulating film 29 is formed to a thickness of 20 to 50 nm on the insulating film 22 and the second layer wiring 26. The insulating film 29 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 29 suppresses or prevents the copper in the main conductor film 26b of the second layer wiring 26 from diffusing into the interlayer insulating film 36 to be formed later. As another material of the insulating film 29, for example, a single film of a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. An example of the silicon carbide film formed by the plasma CVD method is BLOk (manufactured by AMAT). The film forming gas is as described above. In forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH ₃ ), and trimethylsilane (3MS) is used. Moreover, as a silicon oxynitride film formed by the plasma CVD method, for example, PE-TMS (manufactured by Canon, dielectric constant = 3.9) is available. In forming the silicon oxynitride film, for example, a mixed gas of trimethoxysilane (TMS) gas and nitrogen oxide (N ₂ O) gas is used.

  Thereafter, a photoresist film is sequentially formed on the insulating film 29, and the photoresist film is patterned by exposure to form a photoresist pattern 30. At this time, the insulating film 29 functions as a reaction preventing film between the photoresist pattern 30 and the copper wiring 26. When forming such a reservoir layer, an antireflection film can be used below the photoresist film and above the barrier insulating film 29 in order to further improve accuracy. Thus, a structure in which at least one insulating film layer is inserted between the photoresist pattern for the reservoir and the lower layer wiring is important.

Then, the insulating films 29, 22, 21, and 20 are selectively removed by dry etching using the photoresist pattern 30 as an etching mask to form openings (FIG. 9). At this time, the semiconductor substrate 1 is formed by plasma CVD. The substrate 1 (especially the CMP surface where the second layer wiring 26 is exposed) is subjected to CF ₄ plasma treatment by placing CF ₄ gas and applying a plasma power supply in the processing chamber of the apparatus to insulate the substrate 1. The films 29, 22, 21, and 20 are removed. By such CF ₄ plasma treatment, the surface of the Cu wiring of 26b temporarily generates a slight amount of organic by-products and fluorinated by-products, but after-cleaning (for example, organic acid cleaning, It can be removed by hydrofluoric acid cleaning, organic alkali cleaning or a mixed solution thereof) or hydrogen annealing treatment. In the case where an organic film not containing silicon such as SiLK is used for the insulating film 21, reducing plasma such as ammonia or N ₂ / H ₂ mixed gas is used for etching the insulating film 21. The plasma treatment means that the surface of the substrate or the surface of the member such as an insulating film or a metal film is formed on the substrate in an environment in a plasma state, and the chemical surface of the plasma is exposed. It means that the surface is treated with mechanical (bombardment) action. In addition, the plasma in a reducing atmosphere refers to a plasma environment in which reactive species such as radicals, ions, atoms, and molecules that have a reducing action, that is, an action of extracting oxygen, exist predominantly.

FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during the manufacturing step following that of FIG. 9. In FIG. 10 as well, portions corresponding to the structure below the insulating film 17 in FIG. 2 are not shown. After the insulating films 22, 21, and 20 are removed, post-cleaning is performed, and then an insulating film 31 is formed on the entire main surface of the semiconductor substrate 1 by a plasma CVD method or the like. That is, the insulating film 31 is formed to a thickness of 20 to 50 nm so as to cover the upper and side surfaces of the second layer wiring 26, the barrier insulating film 29 used for forming the reservoir, and the insulating film 17. The insulating film 31 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 31 suppresses or prevents the copper in the main conductor film 26b of the second layer wiring 26 from diffusing into the interlayer insulating film 36 formed later. As another material of the insulating film 31, for example, a single film of a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. An example of the silicon carbide film formed by the plasma CVD method is BLOk (manufactured by AMAT). The film forming gas is as described above. In forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH ₃ ), and trimethylsilane (3MS) is used. Moreover, as a silicon oxynitride film formed by the plasma CVD method, for example, PE-TMS (manufactured by Canon, dielectric constant = 3.9) is available. In forming the silicon oxynitride film, for example, a mixed gas of trimethoxysilane (TMS) gas and nitrogen oxide (N ₂ O) gas is used.

  As shown in FIG. 10, in the wiring structure manufactured in this way, the barrier insulating film in the region where the through hole is formed is relatively thicker than the upper and side portions of the wiring where the through hole is not formed. The structure is completed. The barrier insulating film below the through hole also has a role as an etching stopper layer during the through hole processing, and therefore needs to be about 40 to 50 nm or more. Therefore, for example, if the barrier insulating films 29 and 31 are each formed to a thickness of 25 nm, the barrier insulating film has a thickness of 50 nm in the reservoir region where a through hole may exist, and only 25 nm of the barrier insulating film 31 around other wirings. Thus, it is possible to efficiently achieve capacity reduction and securing a through-hole processing margin.

Next, regarding FIGS. 11 to 17, a reservoir forming method different from the contents described in FIGS. 8 to 10 will be described.
FIG. 11 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing step following that of FIG. 7. In the through-hole reservoir forming method described with reference to FIGS. 8 to 10, a Cu residue film is generated around the barrier insulating film 29 and the second layer wiring 26 depending on the dry etching apparatus because of etching using the resist mask pattern 30. There is a possibility that. Therefore, FIGS. 11 to 15 describe a method of forming a reservoir regardless of the dry etching apparatus. First, as shown in FIG. 11, an insulating film 32, for example, a silicon oxide film or a SiOC film is formed to a thickness of 100 to 400 nm on the barrier insulating film 29. Thereafter, a photoresist film is sequentially formed on the insulating film 32, and the photoresist film is patterned by exposure to form a photoresist pattern 33. When forming such a reservoir layer, an antireflection film can be used below the photoresist film and above the barrier insulating film 32 in order to further improve accuracy.

  Next, as shown in FIG. 12, the insulating film 32 is etched using the photoresist pattern 33 as a mask, and the etching is once stopped on the barrier insulating film 29. Here, ashing is performed as shown in FIG. 13 to remove the resist pattern 33. By doing so, the Cu residue film resputtered on the resist side wall can be prevented. Thereafter, as shown in FIG. 14, the insulating films 29, 22, 21, and 20 are etched using the insulating film mask 32. Thereafter, after performing post-cleaning and hydrogen annealing treatment, the insulating film 31 is formed so as to cover the upper and side surfaces of the second layer wiring 26, the barrier insulating film 29 used for forming the reservoir, and the insulating film 17. Is deposited in a thickness of 20 to 50 nm. By such a process, as shown in FIG. 15, a wiring structure equivalent to FIG. 10 is obtained.

As another embodiment, FIG. 16 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process following FIG. When the insulating films 22, 21, and 20 are etched using the insulating film pattern 32, if the selectivity between the insulating film 32 and the barrier insulating film 29 is low, the barrier insulating film 29 is completely removed and then as shown in FIG. Then, a new barrier insulating film 34 is formed on the insulating film 22, the second layer wiring 26 and the insulating film 17. The insulating film 34 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 34 suppresses or prevents the copper in the main conductor film 26b of the second layer wiring 26 from diffusing into the interlayer insulating film 36 formed later. As another material of the insulating film 34, for example, a single film of a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. An example of the silicon carbide film formed by the plasma CVD method is BLOk (manufactured by AMAT). The film forming gas is as described above. In forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH ₃ ), and trimethylsilane (3MS) is used. Moreover, as a silicon oxynitride film formed by the plasma CVD method, for example, PE-TMS (manufactured by Canon, dielectric constant = 3.9) is available. In forming the silicon oxynitride film, for example, a mixed gas of trimethoxysilane (TMS) gas and nitrogen oxide (N ₂ O) gas is used.

  FIG. 18 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention during the manufacturing process following FIG. 10 or FIG. 15. Insulating films 36 and 37 are formed on the barrier insulating film 31. A low-K insulating film such as SiOF or SiOC is used for the insulating film 36, and a silicon oxide film or the like is used for the insulating film 37 as a cap for the low-K insulating film. In order to simplify the process, it is possible to omit the insulating film 37 and form a single insulating film 36 such as a silicon oxide film or a SiOC film.

  In the present embodiment, the insulating film 36 is formed under the condition that the insulating film 36 is not formed conformally between the nearest wirings (between the minimum adjacent wirings and the minimum pitch wirings). Here, the closest wiring corresponds to a wiring in which the distance between adjacent wirings (distance between adjacent wirings) in the same layer wiring is minimum. It is more important to reduce the parasitic capacitance between the closest wirings.

  As the deposition of the insulating film 36 progresses between the closest wirings, the reactive species are less likely to enter the lower side gradually by being blocked by deposits in the vicinity of the upper portion of the opposing wiring side surface (wiring facing surface). For this reason, the deposition rate near the lower part of the opposing wiring side surface is smaller than the deposition rate near the upper part. Therefore, the thickness of the insulating film 36 deposited on the opposing wiring side surface is not uniform, and the thickness in the vicinity of the upper portion is thicker than that in the vicinity of the lower portion. Such a phenomenon is more conspicuous between the closest wirings of the second layer wirings 26, that is, between the closest wirings of the second layer wirings 26.

  Therefore, the insulating film 36 does not have a conformal shape reflecting the shape of the second layer wiring 26 between the closest wirings of the second layer wiring 26, and a gap (air gap) as shown in FIG. 35 is produced. Further, the insulating film 36 can be formed by a plasma CVD method or the like. By adjusting the film forming conditions of the insulating film 36, the gap (air gap) portion 35 as described above is connected to the nearest wiring. It can be easily formed in between. In the present embodiment, since the upper surface and the side surface of the second layer wiring 26 are covered with the insulating film 31 as the barrier insulating film, the conductive barrier film 26a is omitted from the second layer wiring 26, and the main conductor made of copper is used. The second layer wiring 26 can also be formed only by the film 26b. After the insulating films 36 and 37 are formed, interlayer CMP is performed to planarize the steps generated between the wirings.

  Next, as shown in FIG. 19, after forming an insulating film 39, an antireflection film 40 and a photoresist film are sequentially formed on the insulating film 39, and the photoresist film is patterned by exposure to form a photoresist pattern 41. To do. Then, the antireflection film 40 and the insulating film 39 are selectively removed by dry etching using the photoresist pattern 41 as an etching mask, and ashing is performed to remove the antireflection film and the photoresist film. As a result, as shown in FIG. 20, an opening 42 to be a wiring groove later can be manufactured.

  Next, patterning for forming a through hole is performed. As shown in FIG. 21, an antireflection film 43 and a photoresist film are sequentially formed on the insulating films 37 and 39, and the photoresist film is patterned by exposure to form a photoresist pattern 44. FIG. 22 is a plan view of a principal part of a region corresponding to FIG. 2 in the manufacturing process of the semiconductor device subsequent to FIG. In FIG. 22, the second layer wiring position 26c, the misaligned through-hole position 38 connected to the second layer wiring and the third layer wiring, and the reservoir forming position 28 formed around the second layer wiring are shown. Yes. Here, a position where the through hole 38 is actually misaligned during exposure of the via pattern of FIG. 21 is shown.

FIG. 23 is a cross-sectional view taken along the line AA of FIG. 22 following FIG. Through the dry etching method using the photoresist pattern 44 as an etching mask, the antireflection film 43 and the insulating films 39, 37, and 36 are selectively removed, ashing is performed to remove the antireflection film and the photoresist film, and a through hole is obtained. An opening 45 is formed.
Next, as shown in FIG. 24, groove processing is performed using the insulating film mask 39 to produce a groove opening 46. Subsequently, as shown in FIG. The barrier insulating films 29 and 31 are removed simultaneously.

  Next, a thin conductive barrier film (first conductor film) 47a made of titanium nitride (TiN) or the like and having a thickness of about 5 to 50 nm is formed on the entire main surface of the substrate 1 using a sputtering method or the like. . For the conductive barrier film 47a, various materials described above in 26a can be applied in addition to titanium nitride. Subsequently, a main conductor film (second conductor film) 47b made of relatively thick copper having a thickness of, for example, about 800 to 1600 nm is formed on the conductive barrier film 47a. The main conductor film 47b can be formed using, for example, a CVD method, a sputtering method, a plating method, or the like. Thereafter, the main conductor film 47b is reflowed by performing a heat treatment on the substrate 1 in a non-oxidizing atmosphere (for example, a hydrogen atmosphere or a nitrogen atmosphere) of about 150 to 400 ° C. Embed without any gaps.

  Next, the main conductor film 47b and the conductive barrier film 47a are polished by the CMP method. As a result, as shown in FIG. 26, third layer wiring (wiring) 47 composed of a relatively thin conductive barrier film 47a and a relatively thick main conductor film 47b is formed in the wiring grooves 45 and 46. The third layer wiring 47 is electrically connected to the first layer wiring 15 and the second layer wiring 26 through the through hole 45.

  FIG. 27 is a plan view of an essential part of a region corresponding to FIG. 2 in the manufacturing process of the semiconductor device subsequent to FIG. In FIG. 27, the formation position 49 of the through hole connected to the third layer wiring 47, the second layer wiring and the upper layer is shown. As in the description of FIG. 7, in order to prevent misaligned through-holes (misalignment through-holes), the reservoir formation position is set so that the limited portion of the third-layer wiring is in the same state as the normal interlayer structure. 50 is set.

  28 is a cross-sectional view taken along the line AA of FIG. 27, following FIG. Also in FIG. 28, the illustration corresponding to the structure below the insulating film 17 in FIG. 3 is omitted. On the insulating film 37 and the third layer wiring 47, a barrier insulating film 48 is formed to a thickness of 20 to 50 nm. The insulating film 48 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 48 suppresses or prevents copper in the main conductor film 47b of the third layer wiring 47 from diffusing into the interlayer insulating film 53 to be formed later. As another material of the insulating film 48, for example, a single film of a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. The manufacturing method is the same as that described above with reference to FIG.

  Next, as described with reference to FIGS. 7 to 10, the reservoir 50 is formed around the third layer wiring 47. In FIG. 28, after the barrier insulating film 48 and the insulating films 37 and 36 are etched by the resist mask pattern, a new barrier insulating film 51 is formed on the upper and side walls of the insulating films 36 and 37, the barrier insulating film 48, and the third layer wiring 47. Is deposited in a thickness of 20 to 50 nm. The insulating film 51 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 48 suppresses or prevents copper in the main conductor film 47b of the third layer wiring 47 from diffusing into the interlayer insulating film 53 to be formed later. As another material of the insulating film 48, for example, a single film of a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. The manufacturing method is the same as that described above with reference to FIG.

  Next, as shown in FIG. 30, insulating films 53 and 54 are formed and planarized by the insulating film CMP. Also in the case of following the upper layer, the upper layer wiring after the fourth layer wiring can be formed by repeating the method shown in FIGS. Alternatively, the first layer wiring 15 may be a copper wiring formed in the same manner as the second layer wiring 26, and the second layer wiring 26 may be a copper wiring formed in the same manner as the third layer wiring 47.

  According to this embodiment, there is no CMP surface (surface polished by CMP) between the same-layer wirings. That is, most of the insulating films 21, 22, 36, and 37 polished in the CMP process for forming the second layer wiring 26 and the third layer wiring 47 are removed, and the second layer wiring 26 and the third layer are removed. Barrier insulating films 31 and 51 are formed so as to cover the wiring 47. For this reason, in the second layer wiring 26 and the third layer wiring 47, the upper surfaces of the same layer wirings are not connected to each other through the CMP surface except in the limited reservoir region. Thereby, the withstand voltage between wiring can improve and the TDDB life can also be improved. That is, the reliability of the semiconductor device can be improved.

  In addition, since the gaps (air gaps) 35 and 52 are formed between the closest wirings in the same-layer wiring that requires the most capacity reduction, the inter-wiring capacity can be efficiently reduced. Even if a material having a relatively high dielectric constant is used for the barrier insulating films 31 and 51 of the wiring, the capacitance between the wirings can be reduced. In the region where the distance between adjacent wirings of the same layer wiring is large, a low-K material is formed without forming an air gap between the wirings. For this reason, it becomes possible to maintain the whole mechanical strength.

  In the present embodiment, an insulating film region is formed by the reservoirs 28 and 50 around the through hole and its lower layer wiring. However, since the ratio is smaller than the nearest wiring pattern region, it is caused by the air gap. The capacity reduction effect can be sufficiently exhibited.

  Further, in the present embodiment, the air gap 35 or 52 may be formed between the wirings where the adjacent wiring interval is relatively small and the parasitic capacitance between them is desired to be reduced, not between the nearest wirings. The extent to which the air gap is formed can be controlled by adjusting the film formation conditions of the barrier insulating film 31 or 51, the film formation conditions of the insulating film 36 or 52, and the like. As a result, in a region where the wiring pattern density is high, an air gap is formed between adjacent wirings to reduce the capacitance between the wirings. In a region where the wiring pattern density is low, the spaces between the wirings are filled with a Low-K material, and the mechanical strength is increased. Can be maintained.

  The inventor investigated the capacitance reduction effect of the wiring structure of the present embodiment through experiments and simulations. As a comparative example, a copper wiring structure in which an insulating film and an interlayer insulating film for embedding the wiring are made of a Low-K material and is formed by a general damascene technique is used.

  As a result, the wiring structure of the present embodiment was able to reduce the inter-wiring capacitance by about 20 to 30% compared to the comparative example. In addition, the capacitance between the upper layer wiring and the lower layer wiring hardly changed, and only the capacitance between the wirings in the same layer decreased. For this reason, the influence of the crosstalk of wiring can be reduced. Further, the effective dielectric constant εr (εr is about 3.1 in the copper wiring structure of the comparative example) can be greatly reduced to about 2.3 to 2.7. Therefore, a low-capacity wiring structure of one generation or more can be realized by using the same generation Low-K material for the interlayer insulating film.

  FIG. 31 is a fragmentary cross-sectional view of the semiconductor device as another embodiment of the present invention during the manufacturing process thereof. The semiconductor device of the present embodiment includes a wiring layer in which an air gap is formed between adjacent wirings and the adjacent wirings are not connected on the CMP surface, like the second layer wiring 26 and the third layer wiring 47 of the first embodiment. It has a multilayer wiring structure in which a structure having a reservoir and a wiring layer formed using a general embedded wiring technique are combined. In FIG. 31, the process up to the formation of the insulating film 60 on the fourth layer wiring 55 is substantially the same as the manufacturing process of FIGS. 4 to 10 and FIGS. The description is omitted, and the subsequent manufacturing process will be described here.

  The fifth and subsequent wiring layers are formed using a general buried wiring technique, for example, a general dual damascene technique. First, after the insulating film 60 is planarized by CMP, a fifth layer wiring is formed. Then, using the dual damascene technique, the fifth layer wiring 61 embedded in the wiring trench formed in the insulating films 60, 59, 57, and 56 is formed. Then, an insulating film 62 made of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride film or the like is formed as a barrier insulating film on the insulating film 60 including the upper surface of the fifth layer wiring 61. Thereafter, insulating films 63 and 64 made of a Low-K material or the like are formed on the insulating film 62. Similarly, the sixth layer wiring 65 embedded in the wiring trench formed in the insulating films 62 to 64 is formed by using the dual damascene technique. Then, on the insulating film 64 including the upper surface of the sixth layer wiring 65, an insulating film 66 made of the same material as the insulating film 62, for example, silicon nitride is formed as a barrier insulating film.

As the insulating films 36, 53, 59 and 63, a film formed by a CVD method, for example, a silicon oxide film, an FSG (SiOF-based material) film, a SiOC film, or a porous silicon (Polus-Si) -based material film is used. You can also.
In a multilayer wiring structure, a wiring layer having a relatively small interval between adjacent wirings, that is, a wiring layer having a relatively small wiring pitch, tends to increase the inter-wiring capacity and reduce the TDDB life. According to the present embodiment, in such a wiring layer that increases the capacitance between wirings and easily reduces the TDDB life, the CMP surface is eliminated between the same-layer wirings other than the limited reservoir region, thereby improving the TDDB life. In addition, while maintaining a good contact of the vias that are misaligned using the reservoir structure, an air gap can be formed between the closest wirings of the same layer wiring to reduce the capacitance between the wirings.

  FIG. 32 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention subsequent to FIG. 3 during the manufacturing process. Also in FIG. 32, the illustration corresponding to the structure below the insulating film 17 in FIG. 3 is omitted.

  This embodiment shows an air gap wiring in the case where a wiring layer is formed by dry etching a conductive film typified by aluminum (Al) wiring. First, in the present embodiment, as shown in FIG. 32, a conductive film 70 is formed on the insulating film 17 in which the through holes 18 are buried by sputtering or CVD. The conductive film 70 here is not limited to aluminum and can be variously modified. For example, at least one of a single film such as aluminum (Al) or an aluminum alloy or upper and lower layers of these single films is nitride (Ti) or nitride. A laminated metal film in which a metal film such as titanium (TiN) is formed may be used, or a tungsten film or the like may be used.

  Next, as shown in FIG. 33, an antireflection film 71 and a photoresist film are sequentially formed on the conductive film 70, and the photoresist film is patterned by exposure to form a photoresist pattern 72. Then, the antireflection film 71 is selectively removed by a dry etching method using the photoresist pattern 72 as an etching mask. Thereafter, the conductive film 70 is selectively removed by a dry etching method using the photoresist pattern 72 as an etching mask, and a second wiring layer 73 is formed. Thereafter, as shown in FIG. 34, an insulating film 74 is formed on the second wiring layer and on the second wiring layer under a conformal condition, and a photoresist pattern for via reservoir is formed as in FIG. 75 is formed.

Next, as shown in FIG. 35, the reservoir insulating film pattern is formed by dry etching the insulating film 74 using the reservoir photoresist pattern 75 as a mask. Thus, a structure in which at least one insulating film layer or more is inserted between the photoresist pattern for the reservoir and the lower layer wiring is important.
Next, as shown in FIG. 36, an insulating film 77 is formed under non-conformal conditions, an air gap 76 is selectively formed in a portion where the space between adjacent wirings is narrow, and an interlayer insulating film CMP is performed for insulation. The upper part of the film 77 is planarized.

  Next, as shown in FIG. 37, a via 78 is formed in the insulating film 77. At this time, since the portion where the gap between adjacent wirings where the via portion is formed is formed earlier and there is a reservoir, even if misalignment occurs, no problem occurs and a good contact can be formed.

  38 to 41 show a method of creating the third wiring layer. First, as shown in FIG. 38, a conductive film 79 is formed, an antireflection film 80 and a photoresist film are sequentially formed on the conductive film 79, and the photoresist film is patterned by exposure to form a photoresist pattern 81. To do. Here, the conductive film 79 is not limited to aluminum and can be variously changed. For example, titanium (Ti) or nitridation is formed on at least one of a single film such as aluminum (Al) or an aluminum alloy or upper and lower layers of these single films. A laminated metal film in which a metal film such as titanium (TiN) is formed may be used, or a tungsten film or the like may be used.

  Then, as shown in FIG. 39, the antireflection film 80 and the conductive film 79 are selectively removed by a dry etching method using the photoresist pattern 81 as an etching mask, and a third wiring layer 82 is formed. Thereafter, the reservoir and the air gap creation method described in FIGS. 34 to 36 are similarly used. First, as shown in FIG. 40, an insulating film 83 is processed between the third-layer wirings 82 to form a reservoir as necessary. To do. Next, as shown in FIG. 41, an insulating film 85 is formed on the insulating film 83 to form an air gap 84. Finally, the upper portion of the insulating film 85 is planarized by the interlayer insulating film CMP. If necessary, the upper layer can be formed with the same air gap wiring by the processes repeated so far.

  FIG. 42 is a fragmentary sectional view in the manufacturing process of the semiconductor device according to another embodiment of the present invention. In the semiconductor device of this embodiment, a void is formed between adjacent wirings as in the second-layer wiring 73 and third-layer wiring 82 of the third embodiment, and the reservoir insulating film structure is connected to the adjacent wiring of each wiring layer. It has a multilayer wiring structure in which a structure between them and a wiring layer formed using a general dry etch wiring technique are combined. In FIG. 42, the process up to the step of forming the insulating film 85 is substantially the same as the manufacturing process up to FIG. 41 of the third embodiment, so the description thereof will be omitted, and the subsequent manufacturing process will be described here.

  In the present embodiment, a via 86 is formed in the insulating film 85, and a fourth layer wiring 87 is formed on the insulating film 85 and the via 86 in the same manner as the third layer wiring 82. Then, a reservoir is formed by the insulating film 88, and an insulating film 90 is formed thereon and planarized. In the fourth layer wiring 87 as well, as with the second layer wiring 73 and the third layer wiring 82, a void 89 is formed between the closest wirings.

  The fifth and subsequent wiring layers are formed using a general conductive film dry etching technique. First, after a via 91 is formed in the insulating film 90, a conductive film is formed. Then, a fifth layer wiring 92 is formed using a dry etching technique. Then, an insulating film 93 is formed on the side surface and the upper surface of the fifth layer wiring 93 to perform planarization. Thereafter, a via 94 is formed in the insulating film 93, and a conductive film is formed over the insulating film 93 and the conductive film 94. Thereafter, a sixth layer wiring 95 is formed by using a dry etching technique, an insulating film 96 is formed, and then planarization is performed.

  The insulating films 74, 77, 83, 85, 88, 90, 93, and 96 are films formed using a CVD method, such as a silicon oxide film, FSG (SiOF-based material) film, SiOC film, or porous silicon (Polus−). When an Si) -based material film, an FSG film, an SiOC film, or a porous silicon film is used, an insulating film having a two-layer structure capped with a silicon oxide film can be used.

  In a multilayer wiring structure, a wiring layer having a relatively small distance between adjacent wirings, that is, a wiring layer having a relatively small wiring pitch, increases the inter-wiring capacitance. According to the present embodiment, it is possible to reduce the inter-wiring capacity by forming the air gap while keeping the contact of the misaligned via well in the wiring layer in which the inter-wiring capacity tends to increase.

1 ... Semiconductor substrate
2. Element isolation region
3 ... p-type well
4 ... n-type well
5 ... Gate insulation film
6 ... Gate electrode
7 ... Sidewall
8 ... n-type semiconductor region (source / drain)
9 ... p-type semiconductor region (source / drain)
10 ... Co silicide film
11 ... Silicon nitride film
12 ... Silicon oxide film
13 ... Contact hole
14a ... Insulating film
14b ... Insulating film
15 ... 1st layer wiring
16 ... Insulating film
17 ... Insulating film
18 ... Through hole
19 ... Integrated circuit chip
19a ... Memory part (dense pattern part)
19b ... Peripheral circuit part (sparse pattern part)
20 ... Insulating film
21. Insulating film
22 ... Insulating film
23. Antireflection film
24 ... Photoresist pattern
25. Wiring groove
26 ... Second-layer wiring
26a ... Conductor barrier film
26b ... Main conductor film
26c ... first layer wiring formation position
27: Position of through hole formation
28 ... Reservoir formation position
29 ... Barrier insulating film
30 ... Photoresist pattern
31 ... Barrier insulating film
32. Insulating film
33 ... Photoresist pattern
34 ... Barrier insulating film
35 ... Air gap
36. Insulating film
37. Insulating film
38 ... Misalignment through hole (Through hole misaligned)
39. Insulating film
40: Antireflection film
41 ... Photoresist pattern
42 ... opening
43. Antireflection film
44 ... Photoresist pattern
45 ... Through hole opening
46: Wiring groove opening
47. Third layer wiring
47a ... Conductor barrier film
47b ... Main conductor film
48 ... Barrier insulating film
49 ... Through hole formation position
50: Reservoir formation position
51. Barrier insulating film
52 ... Air gap
53. Insulating film
54. Insulating film
55. Fourth layer wiring
55a ... Conductor barrier film
55b ... Main conductor film
56. Barrier insulating film
57. Barrier insulating film
58 ... Air gap
59. Insulating film
60. Insulating film
61. Fifth layer wiring
61a ... Conductor barrier film
61b ... Main conductor film
62 ... Barrier insulating film
63. Insulating film
64. Insulating film
65 ... 6th layer wiring
65a ... Conductor barrier film
65b ... Main conductor film
66. Barrier insulating film
70: Conductor film
71 ... Antireflection film 72 ... Photoresist pattern
73. Second layer wiring
74. Insulating film
75 ... Photoresist pattern
76 ... Air gap
77. Insulating film
78 ... Through hole
79 ... Conductor film
80 ... Antireflection film
81 ... Photoresist pattern
82. Third layer wiring
83. Insulating film
84 ... Air gap
85 ... Insulating film
86 ... Through hole
87. Fourth layer wiring
88. Insulating film
89 ... Air gap
90. Insulating film
91 ... Through hole
92 ... Fifth layer wiring
93. Insulating film
94 ... Through hole
95: Sixth layer wiring
96. Insulating film

Claims (2)

A method for manufacturing a semiconductor device comprising the following steps:
(A) forming a first conductor film on the semiconductor substrate;
(B) forming a plurality of first wirings by selectively removing the first conductor film by a dry etching method using a photoresist pattern as a mask;
(C) forming a first insulating film on the wiring and in a space region between the wiring;
(D) The first insulating film in the peripheral region of the through hole exposing the upper surface of the wiring with a narrow adjacent wiring interval formed in the subsequent step (f) is left, and the first insulating film other than the peripheral region is left. Removing the step,
(E) forming a second insulating film on the wiring while leaving a gap in the space region between the wirings from which the first insulating film has been removed;
(F) forming a through hole that penetrates the first insulating film and the second insulating film above the wiring having a narrow adjacent wiring interval and exposes an upper surface of the wiring having the narrow adjacent wiring interval;
(G) A step of forming a second conductor film inside the through hole.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductor film is an aluminum film or a tungsten film.

Images