KR20100073779A - Metal line of semiconductor device and fabricating method thereof - Google Patents

Metal line of semiconductor device and fabricating method thereof Download PDF

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Publication number
KR20100073779A
KR20100073779A KR1020080132539A KR20080132539A KR20100073779A KR 20100073779 A KR20100073779 A KR 20100073779A KR 1020080132539 A KR1020080132539 A KR 1020080132539A KR 20080132539 A KR20080132539 A KR 20080132539A KR 20100073779 A KR20100073779 A KR 20100073779A
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KR
South Korea
Prior art keywords
film
copper
forming
via hole
barrier
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KR1020080132539A
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Korean (ko)
Inventor
유동재
Original Assignee
주식회사 동부하이텍
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Priority to KR1020080132539A priority Critical patent/KR20100073779A/en
Publication of KR20100073779A publication Critical patent/KR20100073779A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment relates to metallization of a semiconductor device and a method of manufacturing the same. In the method of manufacturing a metallization of a semiconductor device according to an embodiment, forming an insulating film on a substrate, forming a via hole and a trench connected to the via hole in the insulating film, a first Ti on the entire surface of the substrate on which the via hole and the trench are formed Forming a film, forming a barrier film on the first Ti film, forming a copper film in the via hole and the trench where the barrier film is formed, forming a second Ti film on the copper film, and forming the second Ti film; Polishing the copper film to expose the top surface of the insulating film. The embodiment can prevent problems such as an adhesion problem or voids occurring at the interface of the copper wirings using a Ti film, and oxygen at the copper film interface is diffused along the copper grain boundary to be combined with Ta of the diffusion barrier. It can be minimized.

Description

Metal wiring of semiconductor device and manufacturing method thereof

The embodiment relates to metallization of a semiconductor device and a method of manufacturing the same.

In general, in semiconductor devices, electronic devices, and the like, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and a dry method. A technology of forming a wiring by patterning through a dry etching process has been established and widely used in this field. In particular, in recent years, a low resistivity metal such as copper (Cu) instead of aluminum (Al) or tungsten (W) as a part of reducing RC delay time centering on logic devices that require high speed among semiconductor devices. Has been studied to use a wire as a wiring.

However, in the wiring forming step using copper (Cu), a diffusion barrier film is formed between the insulating film and the copper wiring to prevent the copper particles from diffusing the insulating film.

In recent years, reliability problems have arisen in the interconnection structure using copper because the continuous flow of copper is interrupted by the diffusion barrier in the copper interconnect structure, and voids are formed in the diffusion barrier. .

In particular, problems such as poor adhesion and coverage of the diffusion barrier film occur at the interface between the lower copper wire and the upper copper wire, and TaO generation by combining Ta of the diffusion barrier film with oxygen on the surface of the copper film Problem occurs.

These problems can potentially cause problems such as electromigration (EM), stress induced voiding (SIV), stress migration (SM), etc., which not only degrades the performance of the overall device but can also cause reliability. .

The embodiment provides a metal wiring of a semiconductor device and a method of manufacturing the same, which can prevent voids and defects in copper wiring using a Ti film in a semiconductor device having a copper interconnection structure.

In the method of manufacturing a metallization of a semiconductor device according to an embodiment, forming an insulating film on a substrate, forming a via hole and a trench connected to the via hole in the insulating film, a first Ti on the entire surface of the substrate on which the via hole and the trench are formed Forming a film, forming a barrier film on the first Ti film, forming a copper film in the via hole and the trench where the barrier film is formed, forming a second Ti film on the copper film, and forming the second Ti film; Polishing the copper film to expose the top surface of the insulating film.

The metal wiring of the semiconductor device according to the embodiment may be formed on a substrate, and may include an insulating film having via holes and trenches connected to the via holes, a first Ti film formed along inner walls of the via holes and trenches, and a first stacked Ti layer on the first Ti film. And a copper wiring formed on the first barrier film, the second barrier film, and the second barrier film, and formed in the via hole and the trench.

The embodiment can prevent problems such as an adhesion problem or voids occurring at the interface of the copper wirings using a Ti film, and oxygen at the copper film interface is diffused along the copper grain boundary to be combined with Ta of the diffusion barrier. There is an effect that can be minimized.

The embodiment has the effect of improving the characteristics of the copper diffusion barrier of the copper metal wiring in the semiconductor device.

The embodiment has an effect of preventing the electron migration (EM) by adding a Ti film to the diffusion barrier formed on the copper metal wiring.

With reference to the accompanying drawings will be described in detail a metal wiring and a method of manufacturing the semiconductor device according to the embodiments. Hereinafter, when referred to as "first", "second", and the like, this is not intended to limit the members but to show that the members are divided and have at least two. Thus, when referred to as "first", "second", etc., it is apparent that a plurality of members are provided, and each member may be used selectively or interchangeably. In addition, the size (dimensions) of each component of the accompanying drawings are shown in an enlarged manner to help understanding of the invention, the ratio of the dimensions of each of the illustrated components may be different from the ratio of the actual dimensions. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted. In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on / above / over / upper" of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure being additionally formed therebetween. Therefore, the meaning should be determined by the technical spirit of the invention.

1 to 7 are cross-sectional views illustrating a method of forming metal wires in a semiconductor device according to an embodiment.

Here, the substrate 100 may be a semiconductor substrate on which wells and junctions are formed, an insulating film including a lower metal wiring 101 in a multilayer metal wiring structure, or a semiconductor including a conductive pattern used as an electrode of other semiconductor devices. It may be a substrate. The semiconductor substrate may include various transistors, and may include metal wires, via patterns, insulating layers, and various electronic devices.

The embodiment is a copper interconnection structure, and the lower metal interconnection 101 may also be formed of the copper metal interconnection according to the embodiment.

As shown in FIG. 1, a capping layer 115 is formed on the substrate 100.

The capping film 115 may be formed of a silicon nitride film.

The capping film 115 may be deposited to a thickness of 500 kW to 1000 kW.

The capping layer 115 may serve as an etch stop layer to protect the lower metal interconnection 101 from being exposed when etching the insulating layer formed later to form the via hole.

An interlayer insulating layer 120 is formed on the capping layer 115. The interlevel dielectric 120 may be deposited to a thickness of 5000 kPa to 10000 kPa.

The lower metal interconnection 101 may be formed on the substrate 100 in a multi-layered metal interconnection structure, and the lower metal interconnection 101 is connected to the lower metal interconnection 101 to be formed later through the interlayer insulating layer 120. It may be formed into a structure.

The interlayer insulating layer 120 is formed by depositing a material having a low dielectric constant such as fluorinated silicate glass (FSG) by plasma enhanced chemical vapor deposition (PECVD).

As illustrated in FIG. 2, via holes and trenches 121 may be formed in the interlayer insulating layer 120.

The via hole is formed through the interlayer insulating layer 120 to expose the lower metal wire 101.

The trench may be connected to the via hole in a width wider than that of the via hole and formed to a predetermined depth in the interlayer insulating layer 120.

The via hole and the trench 121 may be formed using a general dual damascene method, and the order thereof will not be described in detail.

In brief, a photoresist pattern is formed on the interlayer insulating layer 120, and a via hole is formed by etching the interlayer insulating layer 120 using the photoresist pattern as a mask. The via hole may expose a portion of the lower metal wire 101 to be electrically connected, for example. A protective layer made of novolac or bottom anti-reflective coating (BARC) is formed in the via hole. The interlayer insulating layer 120 is etched to form a trench on the via hole and to remove the protective layer. The interlayer insulating layer 120 having the via hole and the trench 121 exposes a portion of the capping layer 115. The via hole and the trench 121 may be formed by etching the interlayer insulating layer 120 by a plasma etching process. In the etching process, an F-based gas (eg, CF 4, etc.) may be used, or CO or oxygen may be used or a mixture thereof may be used. The photoresist pattern that may remain on the interlayer insulating layer 120 on which the via holes and the trench 121 are formed may be removed by an ashing process. The etching process is performed by plasma etching according to a set ashing rate.

Dual damascene made of a process as described above may be formed in various processes in addition to the above process, single damascene may also be included in the present invention. A portion of the exposed capping film 115 is etched to expose the lower metal wires.

As shown in FIG. 3, a barrier layer 130 is formed along the inner wall of the via hole and the trench 121 on the interlayer insulating layer 120 on which the via hole and the trench 121 are formed.

First, the first barrier metal film 131 is formed.

The first barrier metal film 131 may be formed of a Ti film.

The first barrier metal layer 131 may be formed to have a thickness of 8 to 12 nm.

A second barrier metal film 132 is formed on the first barrier metal film 131.

The second barrier metal film 132 may be formed of a TaN film.

The second barrier metal film 132 may be formed to a thickness of 10 ~ 20nm.

A third barrier metal film 133 is formed on the second barrier metal film 132.

The third barrier metal film 133 may be formed of a Ta film.

The third barrier metal film 133 may be formed to a thickness of 10 to 20nm.

The first barrier metal film 131 may be formed by a low temperature CVD method, and the second and third barrier metal films 132 and 133 may be formed by a PVD method.

The first barrier metal layer 131 may improve the step coverage characteristic in a subsequent process, and may improve the advice characteristic of the lower metal interconnection and the barrier metal layer.

Thereafter, a copper seed layer may be deposited on the entire surface of the substrate 100 on which the via holes and the trench 121 are formed to have a thickness of 200˜800 μs.

As shown in FIG. 4, the copper layer 140 is formed on the substrate 100 on which the copper seed layer is formed by using ECP (electro copper plating).

The copper layer 140 is gap-filled in the via hole and the trench 121, and is formed on the interlayer insulating layer 120 to have a predetermined thickness.

Thereafter, a first annealing is performed to stabilize the copper film 140.

In a typical annealing process, oxygen (O) diffuses downward through a copper grain boundary in CuOx formed on a copper surface and combines with Ta, which is a third barrier metal film formed below, to form TaOx. Since TaOx thus formed deteriorates the SIV characteristic, in this embodiment, the annealing process is limited to the following conditions.

In the first annealing process for stabilizing copper according to the embodiment, the annealing is performed at 160 to 240 ° C. for 16 to 24 minutes.

Subsequently, as shown in FIG. 5, a capping metal film 150 is formed on the copper film 140.

The capping metal film 150 may form a Ti film.

The capping metal layer 150 may be formed to have a thickness of 15 to 25 nm.

The capping metal layer 150 may be formed by PVD.

The capping metal film 150 may function as a gettering film for gettering oxygen in the copper film.

In addition, the capping metal film 150 is doped in the copper film 140 through annealing to capture oxygen of TaOx formed in the lower barrier metal film 130 and reduce it to Ta.

As illustrated in FIG. 6, the capping metal layer 150 may second anneal the substrate 100 formed on the copper layer 140.

In the second annealing process, annealing is performed at 350 to 450 ° C. for 20 to 40 minutes in a nitrogen atmosphere.

As illustrated in FIG. 7, a portion of the capping metal film 150 and the copper film 140 may be planarized using a chemical mechanical polishing process to expose the top surface of the interlayer insulating film 120.

As a result, first to third barrier metal layer patterns 131a, 132a, and 133a are formed in the via hole and the trench 121 formed in the interlayer insulating layer 120, and are formed on the third barrier metal layer pattern 133a. And a copper wiring 140a is formed in the trench 121.

Thereafter, the entire surface of the interlayer insulating layer 120 and the copper wiring 140a is cleaned using DHF to remove all remaining Ti.

The embodiment can prevent problems such as an adhesion problem or voids occurring at the interface of the copper wirings using a Ti film, and oxygen at the copper film interface is diffused along the copper grain boundary to be combined with Ta of the diffusion barrier. There is an effect that can be minimized.

The embodiment has the effect of improving the characteristics of the copper diffusion barrier of the copper metal wiring in the semiconductor device.

The embodiment has an effect of preventing the electron migration (EM) by adding a Ti film to the diffusion barrier formed on the copper metal wiring.

In addition, the embodiment has the effect of improving the performance and reliability of the overall device by solving the problems of electro migration (EM), stress induced voiding (SIV), stress migration (SM), etc. as a copper interconnect structure. have.

Although described above with reference to the embodiments, which are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not exemplified above without departing from the essential characteristics of the present invention. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 7 are cross-sectional views illustrating a method of forming metal wires in a semiconductor device according to an embodiment.

Claims (9)

Forming an insulating film on the substrate; Forming a via hole and a trench connected to the via hole in the insulating layer; Forming a first Ti film on an entire surface of the substrate on which the via hole and the trench are formed; Forming a barrier film on the first Ti film; Forming a copper film in the via hole and the trench in which the barrier film is formed; Forming a second Ti film on the copper film; And Polishing the second Ti film and the copper film to expose an upper surface of the insulating film. The method of claim 1, The first Ti film is formed to a thickness of 8 ~ 12nm metal manufacturing method of the semiconductor device. The method of claim 1, And said barrier film comprises a first barrier metal film formed on said first Ti film, and a second barrier metal film formed on said first barrier metal film. The method of claim 1, A first annealing process is performed after the step of forming the copper film. The method of claim 1, The second Ti film is formed to a thickness of 15 ~ 25nm method of manufacturing a metal wiring of the semiconductor device. The method of claim 1, The first Ti film is formed by a low temperature CVD method, and the second Ti film is formed by a PVD method. The method of claim 1, A second annealing process is performed after the step of forming the second Ti film, and the second annealing process is performed in a nitrogen atmosphere. An insulating film formed on the substrate and having a via hole and a trench connected to the via hole; A first Ti film formed along the inner wall of the via hole and the trench; A first barrier film and a second barrier film stacked on the first Ti film; And And a copper wiring formed on the second barrier film and formed in the via hole and the trench. The method of claim 8, And the first Ti film is in contact with a copper wiring formed on the substrate.
KR1020080132539A 2008-12-23 2008-12-23 Metal line of semiconductor device and fabricating method thereof KR20100073779A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013126458A1 (en) * 2012-02-24 2013-08-29 Skyworks Solutions, Inc. Improved structures, devices and methods releated to copper interconnects for compound semiconductors

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013126458A1 (en) * 2012-02-24 2013-08-29 Skyworks Solutions, Inc. Improved structures, devices and methods releated to copper interconnects for compound semiconductors
US8878362B2 (en) 2012-02-24 2014-11-04 Skyworks Solutions, Inc. Copper interconnects having a titanium—titanium nitride assembly between copper and compound semiconductor
US9443803B2 (en) 2012-02-24 2016-09-13 Skyworks Solutions, Inc. Devices and methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure
US9553049B2 (en) 2012-02-24 2017-01-24 Skyworks Solutions, Inc. Copper interconnects having a titanium-platinum-titanium assembly between copper and compound semiconductor
US9576906B2 (en) 2012-02-24 2017-02-21 Skyworks Solutions, Inc. Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure

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