CN109427649A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN109427649A CN109427649A CN201710734652.1A CN201710734652A CN109427649A CN 109427649 A CN109427649 A CN 109427649A CN 201710734652 A CN201710734652 A CN 201710734652A CN 109427649 A CN109427649 A CN 109427649A
- Authority
- CN
- China
- Prior art keywords
- interconnection
- layer
- mask
- opening
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes: offer substrate, has first medium layer in the substrate, has the first opening in the first medium layer；The first interconnection and the third opening in the first interconnection are formed in first opening；The second interconnection is formed in the third is open, the reproducibility of the second interconnection material is weaker than the reproducibility of the first interconnection material；Second dielectric layer is formed on the first medium layer and the second interconnection；Part second dielectric layer is removed, forms the second opening in second dielectric layer, second open bottom exposes the second interconnection.The method can be improved the controllability of the second opening pattern.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the development of semiconductor technology, semiconductor devices has had deep submicron structures, semiconductor integrated circuit IC
In include huge number of semiconductor element.In this large scale integrated circuit, single layer interconnection structure is not only protected, further includes
Multilayer interconnection structure.Wherein multilayer interconnection structure is stacked with, and is isolated by the dielectric layer between multilayer interconnection structure.It is special
Not, it when forming multilayer interconnection structure using dual damascene (dual-damascene) technique, needs to be formed in the dielectric layer in advance
For the groove and through-hole of interconnection, the groove and through-hole then are filled with conductive material such as copper.
The dual-damascene technics realizes that the difference of sequential manner can be divided into two classes according to technique: first trench process (Trench
) and first through-hole (Via First) technique First.First trench process includes: to etch groove on deposited dielectric layer first
Then figure etches via hole image again；First via process includes: to etch via hole image on dielectric layer first, then again
Etch groove figure.
However, the contact resistance for the semiconductor devices that the prior art is formed is larger.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of forming methods of semiconductor structure, to reduce semiconductor devices
Contact resistance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, comprising: provide
Substrate has first medium layer in the substrate, has the first opening in the first medium layer；Shape in being open described first
Third opening at the first interconnection and in the first interconnection；The second interconnection is formed in the third is open, it is described
The reproducibility of second interconnection material is weaker than the reproducibility of the first interconnection material；In the first medium layer and the second interconnection
Upper formation second dielectric layer；Part second dielectric layer is removed, forms the second opening, second open bottom in second dielectric layer
Portion exposes the second interconnection.
Optionally, the forming step of first interconnection, third opening and the second interconnection includes: to open described first
The first interconnection film is formed in mouthful and on first medium layer, is opened in the first medium layer on the first interconnection film with third
Mouthful；The second interconnection film is formed on the first interconnection film, part the second interconnection film is open full of the third；
The second interconnection film and the first interconnection film are planarized, until exposing the top surface of first medium layer.
Optionally, the formation process of the first interconnection film includes: galvanoplastic；It is formed before the first interconnection film, also
It include: to form the first seed layer in first opening and on first medium layer.
Optionally, the depth of the third opening are as follows: 50 nanometers~150 nanometers；The bottom of third opening is to first
Distance at the top of dielectric layer are as follows: 10 angstroms~100 angstroms.
Optionally, the material of first interconnection includes: copper.
Optionally, the material of second interconnection includes: gold, silver, platinum, platinum cobalt alloy, cobalt or tungsten.
Optionally, the thickness of second interconnection are as follows: 10 angstroms~100 angstroms.
Optionally, first opening includes: first through hole and first groove, and the first through hole and first groove connect
It is logical；It is formed before first opening, the forming method further include: the first mask layer is formed on the first medium layer,
There is the first mask open in first mask layer；Second is formed in first mask open and on the first mask layer to cover
Film layer, second mask layer is interior to have the second mask open, and second mask open is along the direction for being parallel to substrate surface
On size of the size less than the first mask open, and projection of second mask open in substrate and the first mask open
Projection in substrate is least partially overlapped.
Optionally, the forming step of the first through hole and first groove is included: and is carved using second mask layer as exposure mask
The part first medium layer is lost, forms the first initial access hole in the first medium layer；It is initial to form described first
After through-hole, the second mask layer is removed；After removing the second mask layer, using first mask layer as exposure mask, at the beginning of etching first
Beginning via top peripheral part first medium layer forms the first groove in the first medium layer, and etches at the beginning of first
The first medium layer of beginning via bottoms forms first through hole in the first medium layer.
Optionally, second opening includes: the second through-hole and second groove, and second through-hole and second groove connect
It is logical；It is formed before second opening, the forming method further include: third mask layer is formed in the second dielectric layer,
The third mask layer has third mask open；The 4th exposure mask is formed in the third mask open and on third mask layer
Layer, the 4th mask layer is interior to have the 4th mask open, and the 4th mask open edge is parallel on the direction of substrate surface
Size be less than the size of third mask open, and projection of the 4th mask open in substrate and third mask open exist
Projection in substrate is least partially overlapped.
Optionally, the forming step of second through-hole and second groove is included: and is carved using the 4th mask layer as exposure mask
The part second dielectric layer is lost, forms the second initial access hole in the second dielectric layer；It is initial to form described second
After through-hole, the 4th mask layer is removed；After removing the 4th mask layer, using the third mask layer as exposure mask, at the beginning of etching second
Beginning via top peripheral part second dielectric layer second groove in the second dielectric layer, and etch the second initial access hole bottom
Second dielectric layer, the second through-hole is formed in the second dielectric layer.
Optionally, using the third mask layer as exposure mask, the second initial access hole of etching top peripheral part second dielectric layer,
And second the technique of second dielectric layer of initial access hole bottom include: anisotropic dry etch process；The anisotropy
The parameter of dry etch process includes: that the etching gas includes carbon fluorine gas, hydrogen, oxygen and nitrogen.
Optionally, it is formed after second opening, the forming method further include: form the in second opening
Two interconnection structures.
The present invention also provides a kind of semiconductor structures characterized by comprising substrate has in the substrate first to be situated between
Matter layer, the first medium layer is interior to have the first opening；Positioned at first opening in the first interconnection and be located at the first interconnection
On third opening；The second interconnection in third opening；Second on first medium layer and the second interconnection is situated between
Matter layer, the second dielectric layer is interior to have the second opening, and second open bottom exposes the second interconnection.
Optionally, the material of first interconnection includes: copper.
Optionally, the material of second interconnection includes: gold, silver, platinum, platinum cobalt alloy, cobalt or tungsten.
Optionally, the depth of the third opening are as follows: 50 nanometers~150 nanometers；The bottom of third opening is to first
Distance at the top of dielectric layer are as follows: 10 angstroms~100 angstroms.
Optionally, the thickness of second interconnection are as follows: 10 angstroms~100 angstroms.
Optionally, the semiconductor structure further includes the second interconnection structure in the second opening.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method for the semiconductor structure that technical solution of the present invention provides, first is formed mutually in first opening
Portion, company and the third opening in the first interconnection, the third opening is for accommodating the second interconnection.It is subsequent mutual second
The second opening is formed in second dielectric layer in portion, company, due to the top surface of second the first interconnection of interconnection covering part,
Therefore, second interconnection protects the first interconnection of part top.Also, the reduction of the second interconnection material
Property be weaker than the reproducibility of the first interconnection material so that during forming the second opening, oxygen-containing gas and second interconnection
The binding ability in portion is weaker, reduces the loss of oxygen-containing gas, therefore, is conducive to improve the efficiency for forming the second opening, and improve
The controllability of second opening pattern.
Further, using the third mask layer as exposure mask, the technique of the second dielectric layer of the second initial access hole bottom of etching
It include: anisotropic dry etch process, etching gas includes oxygen in the anisotropic dry etch process.Due to second
The reproducibility of interconnection material is weaker, so that the second interconnection and the binding ability of oxygen are weaker, so that the content of oxygen is higher.
The etching gas further includes carbon fluorine gas, and during the anisotropic dry etch process, carbon fluorine gas is easily generated poly-
Object is closed, and oxygen can consume the polymer.When the content of oxygen is higher, the polymer for being formed in the second through-hole side wall disappears
Consumption faster, is then formed by the side wall of the second through-hole and the angle of bottom closer to right angle, is then formed by the bottom of the second through-hole
The difference of portion's size and top dimension is smaller, keeps the bottom size of second through-hole larger.Second through-hole is for subsequent
The second interconnection structure is accommodated, therefore, second interconnection structure and the contact area of the second interconnection are larger, advantageously reduce
The contact resistance of two interconnection structures and the second interconnection.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure；
Fig. 4 to Figure 13 is the structural schematic diagram of each step of the forming method of the semiconductor structure of one embodiment of the invention.
Specific embodiment
As described in background, the contact resistance of the semiconductor devices is larger.
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure.
Referring to FIG. 1, providing substrate 100, there is first medium layer 101 in the substrate 100；In the first medium layer
The first opening (not marking in figure) is formed in 101；The first interconnection structure 102 is formed in first opening；Described first
Stop-layer 103 is formed on dielectric layer 101 and the first interconnection structure 102；Second dielectric layer 104 is formed on the stop-layer 103,
There is the first mask layer 105 in the second dielectric layer 104, have the first mask open (in figure in first mask layer 105
It does not mark)；There is the second mask layer 140, second mask layer in first mask open and on the first mask layer 105
There is the second mask open 150, size of second mask open 150 on the direction for being parallel to 100 surface of substrate in 140
Less than the size of the first mask open, and projection of second mask open 150 in substrate 100 and the first mask open exist
Projection in substrate 100 is least partially overlapped.
Referring to FIG. 2, being exposure mask with second mask layer 140, the part second dielectric layer 104 is etched, described
Initial access hole 106 is formed in second dielectric layer 104；It is formed after the initial access hole 106, removes the second mask layer 140.
Referring to FIG. 3, being exposure mask with first mask layer 105 after the second mask layer 140 of removal, etch described first
Part second dielectric layer 104 around 106 top of beginning through-hole, forms groove 108, and etch in the second dielectric layer 104
The second dielectric layer 104 and stop-layer 103 of 106 bottom of initial access hole, until exposing the top table of the first interconnection structure 102
Face, forms through-hole 107 in the second dielectric layer 104 and stop-layer 103, and the through-hole 107 is connected to groove 108.
In the above method, the through-hole 107 and groove 108 are subsequently used for accommodating the second interconnection structure, second interconnection
Structure is used to be electrically connected with the realization of the first interconnection structure 102.The forming step of the through-hole 107 include: to be formed it is described initial logical
Hole 106；Remove the second dielectric layer 104 and stop-layer 103 of 106 bottom of initial access hole.
Wherein, removing the second dielectric layer 104 of 106 bottom of initial access hole and the technique of stop-layer 103 includes: anisotropy
Dry etch process, the parameter of the anisotropic dry etch process include: that etching gas includes carbon fluorine gas and oxygen.?
During the anisotropic dry etch process, the carbon fluorine gas easily reacts to form polymer, and oxygen can consume
The polymer.
However, the first interconnection structure of part 102 is exposed during the anisotropic dry etch process.By
In the material of first interconnection structure 102 include: copper.The reproducibility of copper is stronger, and therefore, copper is easily reacted with oxygen, so that oxygen
The content of gas reduces, so that the ability of oxygen consumption polymer reduces, so that the thickness of carbon fluorine gas precursor reactant polymer generated
It spends thicker.The polymer is covered in the side wall of through-hole 107, and the polymer can stop the second medium of 107 side wall of through-hole
Layer 104 is etched, so that the bottom size for being formed by through-hole 107 is less than top dimension, it may be assumed that the pattern of the through-hole 107 can
Control property is poor.It is subsequent that the second interconnection structure is formed in through-hole 107, since 107 bottom size of through-hole is smaller, so that being located at through-hole
The contact resistance of the second interconnection structure and the first interconnection structure 102 in 107 is larger, is unfavorable for improving the property of semiconductor devices
Energy.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: described first
There is the first opening in dielectric layer；The first interconnection is formed in first opening and the third in the first interconnection is opened
Mouthful；The second interconnection is formed in the third is open, the reproducibility of second interconnection is weaker than the reduction of the first interconnection
Property；The second opening is formed in the second dielectric layer in second interconnection, second open bottom exposes second mutually
Portion, company.The method can be improved the controllability of the second opening pattern.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 4 to Figure 13 is the structural schematic diagram of each step of the forming method of the semiconductor structure of one embodiment of the invention.
Referring to FIG. 4, providing substrate 200, there is first medium layer 201 in the substrate 200.
In the present embodiment, the substrate 200 is silicon substrate.In other embodiments, the substrate can also serve as a contrast for germanium
The semiconductor substrates such as bottom, silicon-Germanium substrate, silicon-on-insulator, germanium on insulator or sige-on-insulator.
In other embodiments, there is semiconductor devices, such as MOS transistor in the substrate.
In the present embodiment, the first medium layer 201 is single layer structure, and the material of the first medium layer 201 is low K
Dielectric material.The low-K dielectric material refers to dielectric material of the relative dielectric constant less than 3.9.The low-K dielectric material is
Porous material.
In the present embodiment, the material of the first medium layer 201 is the silica (FSG) of fluorine doped.
In other embodiments, the first medium layer is single layer structure, and the material of the first medium layer includes:
SiCOH, the silica (BSG) of boron-doping, the silica (PSG) of p-doped, boron-doping phosphorus silica (BPSG)；Alternatively, institute
State first medium layer be laminated construction, the first medium layer include: base top surface stop-layer and be located at stop-layer
On low K dielectric layer.
Subsequent that the first interconnection structure is formed in the first medium layer 201, the material of the first medium layer 201 is low
K dielectric material, the low-K dielectric material can reduce the capacitor between the first interconnection structure, can reduce in interconnection structure
The time constant of one interconnection structure reduces the delay of circuit signal.
It is formed before first interconnection structure, further includes: the first opening is formed in the first medium layer 201.
It in the present embodiment, is that presenting a demonstration property of dual damascene openings illustrates with first opening, double damascenes
Leather opening includes: through-hole and the groove on through-hole.Specifically please refer to Fig. 4.
Referring to FIG. 5, removal part first medium layer 201, forms the first opening 202 in the first medium layer 201.
In the present embodiment, first opening 202 is dual damascene openings.
In other embodiments, first opening includes: single Damascus opening.
In the present embodiment, first opening 202 includes: the first through hole (figure in the first medium layer 201
In do not mark) and first groove (not marked in figure) in the first through hole.
It is formed before first opening 202, further includes: the first mask layer (figure is formed on the first medium layer 201
In be not shown), there is in first mask layer the first mask open；It is formed in first mask open and on mask layer
Second mask layer (not shown), has the second mask open (not shown) in second mask layer, and described second
Mask open edge is parallel to size of the size on the direction on 200 surface of substrate less than the first mask open, and described second covers
The projection of film opening on a substrate 200 is least partially overlapped with the projection of the first mask open on a substrate 200.
The material of first mask layer includes: silica, silicon nitride, photoresist or metal material, wherein metal material
It include: TiN, TaN, WN.
First mask open is along the size being parallel in 200 surface direction of substrate for defining first be subsequently formed
The size of groove.
The material of second mask layer includes: silica, silicon nitride, photoresist or metal material, wherein metal material
It include: TiN, TaN, WN.
Second mask open is along the size being parallel in 200 surface direction of substrate for defining first be subsequently formed
The size of through-hole.
The forming step of first opening 202 includes: to etch the part first using second mask layer as exposure mask
Dielectric layer 201 forms the first initial access hole in the first medium layer 201；It is formed after first initial access hole, is removed
Second mask layer；After removing second mask layer, using first mask layer as exposure mask, the first initial access hole is etched
Top peripheral part first medium layer 201 forms first groove in the first medium layer 201, and it is initially logical to etch first
The first medium layer 201 of hole bottom forms the first through hole in the first medium layer 201.
Using second mask layer as exposure mask, the technique for etching the part first medium layer 201 includes: anisotropic dry
Method etching technics.
Using first mask layer as exposure mask, at the top of the first initial access hole of etching peripheral part first medium layer 201 and
The technique of the first medium layer 201 of first initial access hole bottom includes: anisotropic dry etch process.
It is formed after first opening 202, further includes: form the first interconnection structure, institute in first opening 202
The first interconnection structure is stated to include: the first interconnection on the first 202 side walls of opening and bottom surface and be located at part the
The second interconnection in one interconnection specifically please refers to Fig. 6 to 8.
Referring to FIG. 6, forming the first interconnection film in first opening, 202 (see Fig. 5) and on first medium layer 201
250, there is on the first interconnection film 250 third opening 230 in first medium layer 201.
In the present embodiment, formed before the first interconnection film 250, further includes: first opening 202 (see
Fig. 5) the first seed layer on interior and first medium layer 201.
Nucleus of first seed layer as the first interconnection film 250, and the is formed using electroplating technology as subsequent
The electrode of one interconnection film 250.
The material of the first interconnection film 250 is metal, in the present embodiment, the material of the first interconnection film 250
Material is copper.In other embodiments, the material of the first interconnection film includes: aluminium.
The formation process of the first interconnection film 250 includes: plating or electrochemical plating technique.
The side wall of first seed layer covering, first opening 202 and bottom, using electroplating technology, along first seed crystal
The crystal orientation direction of layer forms the first interconnection film 250.First interconnection film, 250 underfill first opening 202,
Third opening 230 is formed on the first interconnection film.
The depth of the third opening 230 are as follows: 50 nanometers~150 nanometers.Third opening 230 accommodates for subsequent
Two interconnection films.
The first interconnection film 250 is for being subsequently formed the first interconnection.
Referring to FIG. 7, the second interconnection film 260 is formed on the first interconnection film 250, part second interconnection
Portion's film 260 is weaker than the first interconnection film full of the third 230 (see Fig. 6) of opening, the reproducibility of the second interconnection film 260
250 reproducibility.
In the present embodiment, the material of the second interconnection film 260 is platinum cobalt alloy.In other embodiments, described
The material of second interconnection film includes: gold, silver, platinum, cobalt or tungsten.
The formation process of the second interconnection film 260 includes: plating or electrochemical plating technique.
The thickness of the second interconnection film 260 are as follows: 10 angstroms~100 angstroms.
The second interconnection film 260 is for being subsequently formed the second interconnection.The thickness of the second interconnection film 260 is determined
Surely the thickness for the second interconnection being subsequently formed.
Referring to FIG. 8, the second interconnection film 260 of planarization and the first interconnection film 250, until exposing first medium layer
203 top surface forms the first interconnection 203a in first opening, 202 (see Fig. 4) and is located at the interconnection of part first
The second interconnection 203b on portion 203a.
The technique for planarizing the second interconnection film 260 and the first interconnection film 250 includes: chemical mechanical milling tech.
First interconnection structure 203 include: the first interconnection 203a and on the first interconnection 203a of part second mutually
Company portion 203b.
Since first interconnection 250 is used to form the first interconnection 203a, the second interconnection film 260 is used for shape
At the second interconnection 203b, the reproducibility of the second interconnection film 260 is weaker than the reproducibility of the first interconnection film 250, therefore,
The reproducibility of the second interconnection 203b is weaker than the reproducibility of the first interconnection 203a.
The second through-hole, the second via bottoms exposure are formed in the subsequent second dielectric layer on the second interconnection 203b
Second interconnection 203b out.Since the second through-hole is smaller along the size being parallel in 200 surface direction of substrate, although institute
The second interconnection 203b only the first interconnection of covering part 203a is stated, the second interconnection 203b covers the second through-hole enough
First interconnection 203a of bottom.During forming the second through-hole, since the reproducibility of the second interconnection 203b is weaker, because
This, the binding ability of oxygen-containing gas and the second interconnection 203b is weaker, can reduce the loss of oxygen-containing gas, therefore, have
Conducive to the efficiency for improving the second through-hole of formation, and improve the controllability of the second through-hole pattern.
The thickness of the second interconnection 203b are as follows: 10 angstroms~100 angstroms, select the thickness of the second interconnection 203b
Meaning is: if the thickness of the second interconnection 203b less than 10 angstroms so that the second interconnection 203b is to the first interconnection
The protection of 203a is inadequate, and during being subsequently formed the second through-hole, the first interconnection 203a consumes to form the second through-hole
The amount of oxygen-containing gas in the process is more and without standard measure, so that being used to form the amount of the oxygen-containing gas of the second through-hole also without legal
Amount, so that the controllability for being formed by the second through-hole pattern is poor；If the thickness of the second interconnection 203b is greater than 100 angstroms,
So that for accommodates the second interconnection 203b third opening 230 depth it is larger so that formed third be open 230 difficulty compared with
Greatly.
Referring to FIG. 9, forming stop-layer 205 on the first medium layer 201 and the second interconnection 203b and being located at
Second dielectric layer 206 on stop-layer 205.
The stop-layer 205 is used for as the etching stop layer for being subsequently formed the second opening.
In the present embodiment, the material of the stop-layer 205 is silicon nitride.In other embodiments, the stop-layer
Material includes: AlN, SiCN or SiCO.
The material and forming method of the second dielectric layer 206 are identical as the material of first medium layer 201 and forming method,
This will not be repeated here.
It is formed after the second dielectric layer 206, further includes: the second opening is formed in the second dielectric layer 206.
It in the present embodiment, is that presenting a demonstration property of dual damascene openings illustrates with second opening, second opening
Include: the second through-hole and the second groove on the second through-hole, specifically please refers to Figure 10 to Figure 12.
Referring to FIG. 10, third mask layer 207 is formed in the second dielectric layer 206, in the third mask layer 207
It (is not marked in figure) with third mask open；The 4th is formed in the third mask open and on third mask layer 207 to cover
Film layer 270, the 4th mask layer 270 is interior to have the 4th mask open 280, and the 4th mask open 280 is in substrate 200
On projection and the projection of third mask open on a substrate 200 it is least partially overlapped.
The material of the third mask layer 207 includes: silica, silicon nitride, photoresist or metal material, wherein metal
Material includes: TiN, TaN, WN.
The third mask open is along the size being parallel in 200 surface direction of substrate for defining second be subsequently formed
The size of groove.
The material of 4th mask layer 270 includes: silica, silicon nitride, photoresist or metal material, wherein metal
Material includes: TiN, TaN, WN.
4th mask open 280 is used to define to be subsequently formed along the size being parallel in 200 surface direction of substrate
The size of second through-hole.
Figure 11 is please referred to, with the 4th mask layer 270 for exposure mask, the part second dielectric layer 206 is etched, described
The second initial access hole 204 is formed in second dielectric layer 206；It is formed after second initial access hole 204, removes the 4th mask layer
270, expose the top of third mask layer 207 and the side wall and bottom surface of third mask open.
The formation process of second initial access hole 204 includes: anisotropic dry etch process.
Second initial access hole 204 is for being subsequently formed the second through-hole.
The technique for removing the 4th mask layer includes: one of dry etch process and wet-etching technology or two kinds.
It please refers to Figure 12, is exposure mask with the third mask layer 207 after removing the 4th mask layer 280, etch described the
Two initial access holes, 204 top peripheral part second dielectric layer 206 forms second groove 209 in second dielectric layer 206, and carves
The second dielectric layer 206 and stop-layer 205 for losing 204 bottom of the second initial access hole, in second dielectric layer 206 and stop-layer 205
Form the second through-hole 208.
It is exposure mask with the third mask layer 207, etches 204 top peripheral part second medium of the second initial access hole
The technique of the second dielectric layer 206 and stop-layer 205 of layer 206 and 204 bottom of the second initial access hole includes: anisotropic dry
Method etching technics, the parameter of the anisotropic dry etch process include: that etching gas includes carbon fluorine gas, hydrogen, oxygen
And nitrogen.
During the anisotropic dry etch process, the reproducibility of the second interconnection 203b material is compared with first
The reproducibility of interconnection 203a material reduces the loss of oxygen so that the binding ability of the second interconnection 203b and oxygen is weaker,
Therefore, be conducive to improve the efficiency for forming the second through-hole 208, and improve the morphology controllable of second through-hole 208.
Also, during the anisotropic dry etch process, carbon fluorine gas is easy to react generation polymer, and oxygen
Gas can consume the polymer.When the content of oxygen is higher, it is formed in the thickness of the polymer of the second through-hole side wall
Consumption it is very fast, then be formed by the side wall of the second through-hole 208 and the angle of bottom closer to vertical.It is logical to be then formed by second
Hole bottom size and top dimension difference are smaller, keep the bottom size of second through-hole 208 larger.It is subsequent in the second through-hole
The second interconnection structure is formed, the contact resistance of second interconnection structure and the first interconnection structure 203 is smaller, is conducive to improve half
The performance of conductor device.
Figure 13 is please referred to, is formed after second through-hole 208 and second groove 209, third mask layer 207 is removed；It goes
After the third mask layer 207, formed in second through-hole 208 (see Figure 11) and second groove 209 (see Figure 11)
Second interconnection structure 210.
The forming step of second interconnection structure 210 includes: in the second dielectric layer 206,208 and of the second through-hole
Metal layer is formed in second groove 209；The metal layer is planarized, until the top surface of second dielectric layer 206 is exposed,
The second interconnection structure 210 is formed in the second groove 209 and the second through-hole 208.
The material of the metal layer is metal.In the present embodiment, the material of the metal layer is copper.Correspondingly, described
The material of second interconnection structure 210 is copper.In other embodiments, the material of the metal layer includes: aluminium, correspondingly, described
The material of second interconnection structure includes: aluminium.
The formation process of the metal layer includes: plating or electrochemical plating technique.
The technique for planarizing the metal layer includes: chemical mechanical milling tech.
The bottom size of second through-hole 208 is larger, so that being located at the second interconnection structure 210 in the second through-hole 208
It is smaller with the contact resistance of the first interconnection structure 203, be conducive to the performance for improving semiconductor devices.
Correspondingly, the present embodiment also provide it is a kind of semiconductor structure is formed by using the above method, please continue to refer to figure
12, comprising:
Substrate 200 has first medium layer 201 in the substrate 200, has first to open in the first medium layer 201
202 (see Fig. 5) of mouth；
The first interconnection 203a in the first opening 202 and the third opening 230 on the first interconnection 203a
(see Fig. 6)；
The second interconnection 203b in part third opening 230；
Second dielectric layer 206 on first medium layer 201 and the second interconnection 203b, the second dielectric layer 206
Inside there is the second opening, second open bottom exposes the top surface of the second interconnection 203b.
The material of the first interconnection 203a includes: copper.
The material of the second interconnection 203b includes: platinum cobalt alloy, cobalt or tungsten.
The depth of the third opening 230 are as follows: 50 nanometers~150 nanometers.
The thickness of the second interconnection 203b are as follows: 1000 angstroms~3000 angstroms.
The semiconductor structure further include: the second interconnection structure 210 in the second opening.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, there is first medium layer in the substrate, there is the first opening in the first medium layer；
The first interconnection and the third opening in the first interconnection are formed in first opening；
The second interconnection is formed in the third is open, the reproducibility of the second interconnection material is weaker than the first interconnection material
The reproducibility of material；
Second dielectric layer is formed on the first medium layer and the second interconnection；
Part second dielectric layer is removed, forms the second opening in second dielectric layer, second open bottom exposes second
Interconnection.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that first interconnection, third are opened
The forming step of mouth and the second interconnection includes: to form the first interconnection film in first opening and on first medium layer,
There is in first medium layer third opening on the first interconnection film；The second interconnection is formed on the first interconnection film
Film, part the second interconnection film are open full of the third；The second interconnection film and the first interconnection film are planarized,
Until exposing the top surface of first medium layer.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the formation process of the first interconnection film
It include: galvanoplastic；It is formed before the first interconnection film, further includes: shape in first opening and on first medium layer
At the first seed layer.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the depth of the third opening are as follows:
50 nanometers~150 nanometers；Distance at the top of the bottom to first medium layer of the third opening are as follows: 10 angstroms~100 angstroms.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material packet of first interconnection
It includes: copper.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material packet of second interconnection
It includes: gold, silver, platinum, platinum cobalt alloy, cobalt or tungsten.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of second interconnection
Are as follows: 10 angstroms~100 angstroms.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that first opening includes: first
Through-hole and first groove, the first through hole are connected to first groove；It is formed before first opening, the forming method is also
Include: to form the first mask layer on the first medium layer, there is the first mask open in first mask layer；Described
The second mask layer is formed in first mask open and on the first mask layer, and there is the second mask open in second mask layer,
Second mask open is along being parallel to size of the size on the direction of substrate surface less than the first mask open, and described the
Projection of two mask opens in substrate is least partially overlapped with projection of first mask open in substrate.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the first through hole and first groove
Forming step include: the first medium layer described in etched portions using second mask layer as exposure mask, in the first medium layer
The first initial access hole of interior formation；It is formed after first initial access hole, removes the second mask layer；Remove the second mask layer it
Afterwards, using first mask layer as exposure mask, peripheral part first medium layer at the top of the first initial access hole of etching is situated between described first
The first groove is formed in matter layer, and etches the first medium layer of the first initial access hole bottom, in the first medium layer
Form first through hole.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that second opening includes: second
Through-hole and second groove, second through-hole are connected to second groove；It is formed before second opening, the forming method is also
Include: the formation third mask layer in the second dielectric layer, there is third mask open in the third mask layer；Described
The 4th mask layer is formed in third mask open and on third mask layer, and there is the 4th mask open in the 4th mask layer,
4th mask open is less than the size of third mask open along the size being parallel on the direction of substrate surface, and described the
Projection of four mask opens in substrate and projection of the third mask open in substrate are least partially overlapped.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that second through-hole and the second ditch
The forming step of slot includes: the part second dielectric layer to be etched, described second using the 4th mask layer as exposure mask
The second initial access hole is formed in dielectric layer；It is formed after second initial access hole, removes the 4th mask layer；Remove the 4th exposure mask
After layer, using the third mask layer as exposure mask, peripheral part second dielectric layer at the top of the second initial access hole of etching, described the
Second groove is formed in second medium layer, and etches the second dielectric layer of the second initial access hole bottom, in the second dielectric layer
Form the second through-hole.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that with the third mask layer be cover
The second dielectric layer of film, the second initial access hole of etching top peripheral part second dielectric layer and the second initial access hole bottom
Technique includes: anisotropic dry etch process；The parameter of the anisotropic dry etch process includes: the etching gas
Including carbon fluorine gas, hydrogen, oxygen and nitrogen.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that it is formed after second opening,
The forming method further include: form the second interconnection structure in second opening.
14. a kind of semiconductor structure characterized by comprising
Substrate has first medium layer in the substrate, has the first opening in the first medium layer；
The first interconnection in the first opening and the third opening in the first interconnection；
The second interconnection in third opening；
Second dielectric layer on first medium layer and the second interconnection, the second dielectric layer is interior to have the second opening, institute
It states the second open bottom and exposes the second interconnection.
15. semiconductor structure as claimed in claim 14, which is characterized in that the material of first interconnection includes: copper.
16. semiconductor structure as claimed in claim 14, which is characterized in that the material of second interconnection include: gold,
Silver, platinum, platinum cobalt alloy, cobalt or tungsten.
17. semiconductor structure as claimed in claim 14, which is characterized in that the depth of the third opening are as follows: 50 nanometers~
150 nanometers；Distance at the top of the bottom to first medium layer of the third opening are as follows: 10 angstroms~100 angstroms.
18. semiconductor structure as claimed in claim 14, which is characterized in that the thickness of second interconnection are as follows: 10 angstroms~
100 angstroms.
19. semiconductor structure as claimed in claim 14, which is characterized in that the semiconductor structure further includes being located at second to open
The second interconnection structure in mouthful.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710734652.1A CN109427649B (en) | 2017-08-24 | 2017-08-24 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710734652.1A CN109427649B (en) | 2017-08-24 | 2017-08-24 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109427649A true CN109427649A (en) | 2019-03-05 |
| CN109427649B CN109427649B (en) | 2020-09-08 |
Family
ID=65501385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710734652.1A Active CN109427649B (en) | 2017-08-24 | 2017-08-24 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109427649B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112097A (en) * | 2019-05-21 | 2019-08-09 | 德淮半导体有限公司 | The production method of wafer bonding structure and wafer bonding structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1516264A (en) * | 2002-12-27 | 2004-07-28 | ����ʿ�뵼������˾ | Method for forming metal wire in semiconductor device |
| KR20080001905A (en) * | 2006-06-30 | 2008-01-04 | 주식회사 하이닉스반도체 | Method of forming a metal wire in a semiconductor device |
| CN101777491A (en) * | 2009-01-09 | 2010-07-14 | 中芯国际集成电路制造(上海)有限公司 | Method for opening contact hole |
| CN102446815A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming interconnecting groove and through hole and method for forming interconnecting structure |
-
2017
- 2017-08-24 CN CN201710734652.1A patent/CN109427649B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1516264A (en) * | 2002-12-27 | 2004-07-28 | ����ʿ�뵼������˾ | Method for forming metal wire in semiconductor device |
| KR20080001905A (en) * | 2006-06-30 | 2008-01-04 | 주식회사 하이닉스반도체 | Method of forming a metal wire in a semiconductor device |
| CN101777491A (en) * | 2009-01-09 | 2010-07-14 | 中芯国际集成电路制造(上海)有限公司 | Method for opening contact hole |
| CN102446815A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming interconnecting groove and through hole and method for forming interconnecting structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112097A (en) * | 2019-05-21 | 2019-08-09 | 德淮半导体有限公司 | The production method of wafer bonding structure and wafer bonding structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109427649B (en) | 2020-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101600217B1 (en) | Self-enclosed asymmetric interconnect structures | |
| US9741608B2 (en) | Methods of fabricating semiconductor devices including supporting patterns in gap regions between conductive patterns | |
| TWI549245B (en) | Methods for forming interconnect layers having tight pitch interconnect structures | |
| TWI610365B (en) | Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches and a structure thereof | |
| TWI552268B (en) | Techniques for forming interconnects in porous dielectric materials | |
| TW503473B (en) | Semiconductor wafer device having separated conductive patterns in peripheral area and its manufacture method | |
| KR101111025B1 (en) | Integrated low-k hard mask | |
| TW201521202A (en) | Method and structure to contact tight pitch conductive layers with guided vias | |
| CN104979203B (en) | The forming method of MOS transistor and conductive plunger | |
| JP2003324102A (en) | Manufacturing method of semiconductor device | |
| TWI288430B (en) | Structure with via hole and trench and the fabrication method thereof | |
| TWI512893B (en) | Avd hardmask for damascene patterning | |
| CN109755245B (en) | Memory device and method of manufacturing the same | |
| CN109427649A (en) | Semiconductor structure and forming method thereof | |
| CN109427650B (en) | Semiconductor structure and forming method thereof | |
| JP2003249572A (en) | Method of manufacturing semiconductor device, and the semiconductor device | |
| CN104022071B (en) | Forming method of interconnection structure | |
| TWI660464B (en) | Memory device and method for manufacturing the same | |
| CN110233132A (en) | Semiconductor structure and forming method thereof | |
| TW432627B (en) | Method of manufacturing semiconductor device having interconnection composed of doped polysilicon layer | |
| KR100779343B1 (en) | Semiconductor device having mim capacitor and method of fabricating the same | |
| CN108573913A (en) | Semiconductor structure and forming method thereof | |
| US20050153539A1 (en) | Method of forming interconnection lines in a semiconductor device | |
| KR20000011641A (en) | Semiconductor device and manufacturing method thereof | |
| KR20050054116A (en) | The copper metal layer in semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |