TWI660464B - Memory device and method for manufacturing the same - Google Patents

Abstract

A memory device and a method of manufacturing the same are provided. The memory device includes two first gate structures and a multilayer insulation structure. The multilayer insulation structure includes a first insulation layer, a second insulation layer, a third insulation layer, and a fourth insulation layer in order from bottom to top. The width of the second insulating layer is the same as that of the third insulating layer, and is smaller than the width of the first insulating layer. The width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer. The memory device also includes a capacitive contact plug formed between the first gate structures. The capacitive contact plug includes a first contact member, a buffer layer, and a second contact member. The top surface of the second contact member is wider than the bottom surface thereof.

Description

Memory device and manufacturing method thereof

The invention relates to a memory device, and more particularly, to a memory device with a self-aligned contact structure and a manufacturing method thereof.

With the increasing popularity of portable electronic products, the demand for memory devices is also increasing. All portable electronic products (for example, digital cameras, notebook computers, mobile phones, etc.) require lightweight and reliable memory devices to facilitate data storage and transmission.

Dynamic random access memory (DRAM) has the advantages of small size, large memory capacity, fast read / write speed, and long product life. Therefore, it is widely used in various electronic products.

With the trend of miniaturization of electronic products, there is also a demand for miniaturization of memory devices. However, with the miniaturization of memory devices, it has become more difficult to improve the yield of products. Therefore, there is still a need for a memory device and a manufacturing method thereof with a high yield.

An embodiment of the present invention discloses a memory device including: a substrate, wherein the substrate includes an array region and a peripheral region; two first gate structures formed in the array region; and a multilayer insulation structure formed in the first gate Structurally, the multilayer insulation structure includes: a first insulation layer formed on the first gate structure, And covers the first gate structure; the second insulating layer is formed on the first insulating layer, wherein the width of the second insulating layer is smaller than the width of the first insulating layer; the third insulating layer is formed on the second insulating layer, wherein The width of the third insulating layer is the same as the width of the second insulating layer; and the fourth insulating layer is formed on the third insulating layer, wherein the width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer; And a capacitive contact plug formed between the first gate structures, wherein the capacitive contact plug includes: a first contact member formed on the substrate; a second contact member formed on the first contact member, wherein the second contact The width of the top surface of the component is greater than the width of the bottom surface of the second contact component; and a buffer layer is formed between the first contact component and the second contact component.

Another embodiment of the present invention discloses a method for manufacturing a memory device, including: providing a substrate, wherein the substrate includes an array region and a peripheral region; forming two first gate structures in the array region; and forming a multi-layer insulation structure in the first region. On a gate structure, the multilayer insulation structure includes: a first insulation layer formed on the first gate structure and covering the first gate structure; a second insulation layer formed on the first insulation layer, wherein the first The width of the two insulating layers is smaller than the width of the first insulating layer; the third insulating layer is formed on the second insulating layer, wherein the width of the third insulating layer is the same as the width of the second insulating layer; and the fourth insulating layer is formed on On the third insulation layer, a width of a bottom surface of the fourth insulation layer is greater than a width of a top surface of the third insulation layer; and a capacitor contact plug is formed between the first gate structures, wherein the capacitor contact plug includes: A contact member is formed on the substrate; a second contact member is formed on the first contact member, wherein a width of a top surface of the second contact member is greater than a width of a bottom surface of the second contact member; ; And a buffer layer formed between the first contact member and the second contact member.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are exemplified below and described in detail as follows:

10‧‧‧Array area

20‧‧‧Peripheral area

100‧‧‧Memory device

102‧‧‧ substrate

104‧‧‧Polycrystalline silicon gate

106‧‧‧ metal gate

108‧‧‧The first insulation layer

110‧‧‧ protective layer

112‧‧‧Second insulation layer

114‧‧‧third insulating layer

111, 115, 123, 127, 129, 131‧‧‧ opening

116‧‧‧The first curtain layer

118‧‧‧ second curtain layer

120‧‧‧Photoresistive layer

121‧‧‧Second conductive material

122, 222, 322, 422‧‧‧ Fourth insulation layer

122S, 222S, 322S, 422S‧‧‧ sidewall

122B, 222B, 322B, 422B ‧‧‧ bottom surface

122T, 222T, 322T, 422T‧‧‧Top surface

124‧‧‧Fifth insulation layer

125‧‧‧ self-aligned contact hole

130‧‧‧ buffer layer

133‧‧‧Source / drain contact hole

135‧‧‧Gate contact hole

140‧‧‧Second contact part

142‧‧‧Gate contact plug

144‧‧‧Source / Drain Contact Plug

145‧‧‧hole

150‧‧‧First contact part

160‧‧‧Capacitor structure

T1‧‧‧Maximum thickness

W1, W2, W3, W4, W5, W6, W7, W8‧‧‧Width

θ‧‧‧ angle

FIG. 1A to FIG. 1L are schematic cross-sectional views of a manufacturing process of a memory device according to some embodiments of the present invention.

FIG. 2 is a schematic enlarged sectional view of a region R in FIG. 1K.

FIG. 3 is a schematic cross-sectional view of a fourth insulating layer according to some embodiments of the present invention.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are exemplified below and described in detail with the accompanying drawings. However, in order to make the description clearer, the relative size ratio or number of various characteristic structures can be arbitrarily increased or decreased. Furthermore, repeated reference signs and / or words may be used in different examples of this disclosure. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the appearance structure.

Some embodiments of the present invention provide a memory device and a method for manufacturing the same. FIG. 1A to FIG. 1L are schematic cross-sectional views illustrating a manufacturing process of the memory device 100 according to some embodiments of the present invention.

Referring to FIG. 1A, the memory device 100 includes a substrate 102, and the substrate 102 includes an array region 10 and a peripheral region 20. A plurality of first gate structures are formed on the substrate 102 of the array region 10. The first gate structure includes a polycrystalline silicon gate 104 and a metal gate 106 stacked on the polycrystalline silicon gate 104. Furthermore, a plurality of second gate structures are formed on the substrate 102 in the peripheral region 20, and the second gate structures include The polysilicon gate 104 and the metal gate 106 stacked on the polysilicon gate 104.

The material of the substrate 102 may include silicon, a silicon-containing semiconductor, silicon on insulator (SOI), other suitable materials, or a combination of the foregoing materials. The material of the metal gate 106 may be, for example, tungsten, aluminum, copper, gold, silver, tantalum, hafnium, zirconium, the alloy described above, or other suitable metal materials.

After forming the first and second gate structures, a first insulating layer 108 is formed on the first and second gate structures, and the first insulating layer 108 covers the first and second gate structures. Two gate structure. Next, the first insulating layer 108 is patterned to form openings 115 between the first gate structure and the second gate structure, respectively, as shown in FIG. 1A. The first insulating layer 108 may be formed and patterned by any conventional technique, which is not described in detail here.

Next, in the array region 10, a first conductive material is deposited in the openings 115 between the first gate structures to form a first contact member 150. The first conductive material may be a non-metallic conductive material, for example, including, but not limited to, doped or undoped single crystal silicon, polycrystalline silicon, or amorphous silicon. The first conductive material may be deposited by any conventional technique, which is not described in detail here.

Before forming the first contact member 150, a protective layer 110 may be formed in the peripheral region 20, which covers the first insulating layer 108 and the second gate structure and fills the opening 115 between the first gate structure to avoid the first A conductive material is deposited on the peripheral region 20. After the first contact member 150 is formed, a part of the protective layer 110 on the peripheral region 20 may be removed by a planarization process or an etching process to expose the first insulating layer 108. In this way, the structure shown in FIG. 1A can be obtained.

Referring to FIG. 1B, a second insulating layer 112 is formed on the first insulating layer 108, and the second insulating layer 112 is filled in the opening in the array region. Then, visual A planarization process is required. The second insulating layer 112 has a top surface having substantially the same height in the array region 10 and the peripheral region 20. In other words, the second insulating layer 112 has a substantially flat top surface. Thereafter, a third insulating layer 114 is formed on the second insulating layer 112, and the third insulating layer 114 has a top surface having substantially the same height in the array region 10 and the peripheral region 20. In other words, the third insulating layer 114 has substantially the same thickness in the array region 10 and the peripheral region 20.

Referring to FIG. 1C, a first cover curtain layer 116, a second cover curtain layer 118, and a photoresist layer 120 are formed on the third insulating layer 114. In this embodiment, the first mask layer 116 and the second mask layer 118 are used as a mask in the etching process. However, it is not limited to this, and a single layer or a plurality of mask layers may be used as required. The first cover layer 116 and the second cover layer 118 may each independently include carbides, nitrides, carbonitrides, oxynitrides, or other suitable materials.

Next, the photoresist layer 120 is patterned to form a plurality of openings 111 in the array region 10 and a plurality of openings 123 in the peripheral region 20. As shown in FIG. 1C, the opening 111 is located on the opening 115, and its position corresponds to the position of the opening 115. The width of the opening 111 is wider than the width of the opening 115. In addition, the positions of the openings 123 correspond to both sides of the second gate structure.

Referring to FIG. 1C and FIG. 1D, a first etching process is performed, and each layer under the opening 111 and the opening 123 is etched to pattern the third insulating layer 114. In order to effectively remove the third insulating layer 114, the etching rate of the third insulating layer 114 by the first etching process is preferably higher. The first etching process may be dry etching, wet etching, or a combination thereof.

Next, a second etching process is performed using the patterned third insulating layer 114 as a mask to remove part of the second insulating layer 112 and the first insulating layer. 108, and a self-aligned contact hole 125 is formed between the first gate structure, and openings 127 are formed on both sides of the second gate structure.

In order to use the third insulating layer 114 as an etching mask, the second etching process has a high etching selectivity for the second insulating layer 112 and the third insulating layer 114. In other words, the etching rate R1 of the second etching process for the second insulating layer 112 is greater than the etching rate R2 of the third insulating layer 114. In addition, in order to form the self-aligned contact hole 125 as shown in FIG. 1D, the second etching process has a high etching selectivity for the second insulating layer 112 and the first insulating layer 108. In other words, the etching rate R1 of the second etching process for the second insulating layer 112 is greater than the etching rate R3 of the first insulating layer 108.

The second etching process may be dry etching, wet etching, or a combination thereof. During the second etching process, since the second etching process has high etching selectivity for the second insulating layer 112 and the third insulating layer 114, substantially vertical sidewalls can be formed on the upper portion of the self-aligned contact hole 125. . When the etching depth reaches the top surface of the first insulating layer 108, only a small part of the first insulating layer 108 is removed because the second etching process has a high etching selectivity for the second insulating layer 112 and the first insulating layer 108. . In other words, the second etching process can completely remove the second insulating layer 112 located under the self-aligned contact hole 125 while maintaining the shape of the first insulating layer 108.

In some embodiments, during the second etching process, the ratio R1 / R2 of the etching rate R1 of the second insulating layer 112 to the etching rate R2 of the third insulating layer 114 is 5-40. In some embodiments, R1 / R2 is 10-40. In other embodiments, R1 / R2 is 20-30. In some embodiments, during the second etching process, the first insulating layer 108 is etched by the etching rate R1 of the second insulating layer 112. The ratio R1 / R3 of the rate R3 is 10-50. In some embodiments, R1 / R3 is 10-40. In other embodiments, R1 / R3 is 20-30.

Each of the first insulating layer 108, the second insulating layer 112, and the third insulating layer 114 may be an oxide, a nitride, an oxynitride, a metal oxide, a combination of the foregoing, or other suitable insulating materials. By selecting appropriate materials to form the first insulating layer 108, the second insulating layer 112, and the third insulating layer 114, the etching rate of each insulating layer in the second etching process can be adjusted to a desired range.

In some embodiments, the first insulating layer 108 and the third insulating layer 114 may be nitride (for example, silicon nitride), and the second insulating layer 112 may be an oxide (for example, silicon oxide). In other embodiments, the first insulating layer 108 and the third insulating layer 114 may be different materials, as long as R1 / R2 and R1 / R3 are 5-40 and 5-50, respectively.

In order to make R1 / R2 and R1 / R3 be 5-40 and 5-50, respectively, an appropriate etching process and / or etching parameters may be selected. In some embodiments, the second etching process is dry etching, and parameters that can be used to adjust the etching selectivity include, but are not limited to, for example, the composition of the etching gas, the flow rate of the etching gas, the etching temperature, or the etching power.

After the second etching process, the width of the third insulating layer 114 is substantially the same as the width of the second insulating layer 112, and the width of the third insulating layer 114 is smaller than the width of the first insulating layer 108 below it, as in the first 1D As shown. In other words, the cross-sectional profile of the formed self-aligned contact hole 125 has a wider upper portion and a narrower lower portion. Such self-aligned contact holes 125 can help improve the balance between the yield and the critical size of the memory device, which will be discussed in detail later.

Referring to FIG. 1E, a first region is formed in the array region 10 and the peripheral region 20. A cover layer 116, a second cover layer 118, and a photoresist layer 120. Next, the photoresist layer 120 in the peripheral region 20 is patterned to form a plurality of openings 129 and 131 in the peripheral region 20. The opening 131 is located on the opening 127, and its position corresponds to the position of the opening 127. The width of the opening 131 is wider than the width of the opening 127. In addition, the opening 129 is located on the second gate structure, and its position corresponds to the position of the second gate structure.

Referring to FIG. 1E and FIG. 1F, a third etching process is performed, and each layer below the opening 129 and the opening 131 is etched to form a gate contact hole 135 on the second gate structure and form a source / drain The contact holes 133 are on both sides of the second gate structure. In addition, after the third etching process, the self-aligned contact holes 125 in the array region 10 are exposed. The third etching process may be the same as or similar to the first etching process and / or the second etching process, and details are not described herein again.

Referring to FIG. 1G, a metal silicidation reaction is performed to form a buffer layer 130 at the bottom of the self-aligned contact hole 125, the gate contact hole 135, and the source / drain contact hole 133. The buffer layer 130 may be formed using any suitable process. For example, a metal (eg, cobalt or tungsten) can be deposited on the surface of silicon, and then annealed at a specific high temperature to react the metal with silicon to form a metal silicide. The metal silicide is a material constituting the buffer layer 130.

Referring to FIG. 1H, a second conductive material 121 is deposited in the self-aligned contact hole 125, the gate contact hole 135, and the source / drain contact hole 133. The second conductive material 121 may include a metal, for example, tungsten, aluminum, copper, gold, silver, the alloy described above, or other suitable metal materials.

The first conductive material is a non-metallic conductive material, and the second conductive material 121 is a metallic material. The adhesion between the two is not good, and the conductivity of the two is also significantly different. By forming the buffer layer 130, the first conductive material and the The adhesive force between the second conductive materials 121 can avoid a sudden change in the resistance value.

Referring to FIG. 1I, a planarization process is performed, and a part of the second conductive material 121 is removed to form a second contact member 140 in the self-aligned contact hole 125, and a gate contact plug 142 and a source / The drain contact plug 144 is in the gate contact hole 135 and the source / drain contact hole 133.

As shown in FIG. 11, the bottom surface of the second contact member 140 is higher than the top surface of the first gate structure. Both the second contact member 140 and the metal gate 106 include a metal material with good conductivity. Therefore, if the distance between the second contact member 140 and the first gate structure is too close, electrical interference is likely to occur during operation of the two.

Referring to FIG. 1J, a fourth insulating layer 122 is formed in the array region 10 and the peripheral region 20. In some embodiments, the fourth insulating layer 122 may use the same material as the third insulating layer 114. In this embodiment, the fourth insulating layer 122 is a nitride (for example, silicon nitride).

Referring to FIG. 1K, a fifth insulating layer 124 is formed on the fourth insulating layer 122. In some embodiments, the fifth insulating layer 124 may use the same material as the second insulating layer 112. In this embodiment, the fifth insulating layer 124 is an oxide (for example, silicon oxide).

Next, a patterned mask layer (not shown in the figure) is formed on the fifth insulating layer 124 of the array region 10, and a fourth etching process is performed to remove part of the fifth insulating layer 124 and part of the fourth insulating layer 124. The insulating layer 122 and a plurality of holes 145 are formed in the fifth insulating layer 124 on the top surface of the second contact member 140. Each hole 145 is located on a second contact member 140, and each hole 145 exposes a part of the top surface of a second contact member 140, and the fourth insulating layer 122 has a gradually narrowing cross-sectional profile as shown in the first section. 1K picture.

Before the fourth etching process is performed, a protective layer (not shown in the figure) may be formed on the peripheral region 20 to avoid damage to the fifth insulating layer 124 of the peripheral region 20 by the fourth etching process. After the fourth etching process is performed, the protective layer on the peripheral region 20 may be removed to expose the fifth insulating layer 124. In this way, the structure shown in FIG. 1K can be obtained.

The fourth etching process may be dry etching, wet etching, or a combination thereof. The fourth etching process may have a suitable etching selectivity for the fifth insulating layer 124 and the fourth insulating layer 122, so a portion of the fourth insulating layer 122 may be retained in the hole 145. In other words, the fourth insulating layer 122 located at the bottom of the hole 145 may be provided with a protruding portion extending toward the inside of the hole 145.

In some embodiments, during the fourth etching process, the ratio R4 / R5 of the etching rate R4 of the fifth insulating layer 124 to the etching rate R5 of the fourth insulating layer 122 is 2-30. In some embodiments, R4 / R5 is 5-20. In other embodiments, R4 / R5 is 10-15.

In some embodiments, the fourth etching process is a wet etching process, and the fourth insulating layer 122 has a cross-sectional profile that gradually narrows upward, as shown in FIG. 1K. Such a fourth insulating layer 122 can help to greatly improve the yield of the memory device, which will be discussed in detail later.

Referring to FIG. 1L, a capacitor structure 160 is formed in the hole 145, wherein the bottom surface of the capacitor structure 160 directly contacts the top surface of the second contact member 140, so that the capacitor structure 160 and the second contact member 140 are electrically connected. The capacitor structure 160 may be formed by a conventional method, which is not described in detail here.

FIG. 2 is a schematic enlarged sectional view of a region R in FIG. 1K. Please refer to FIG. 1K and FIG. 2 at the same time. The second contact member 140 may include a first part, a first Part two and part three. The first portion (ie, the upper portion) extends downward from the bottom surface 122B of the fourth insulating layer 122. The second part (ie, the lower part) extends upward from the top surface of the buffer layer 130. The third section (ie, the middle section) is located between the first section and the second section and is adjacent to the first section and the second section, wherein the third section gradually narrows toward the second section.

A second portion of the second contact member 140 is located between the two first gate structures. If the width of the second portion is too wide, the distance between the second contact member 140 and the first gate structure is too close, which may easily lead to an operation error. In order to avoid such an operation error, the first insulating layer 108 between the lower portion of the second contact member 140 and the metal gate 106 may be thickened. However, as the first insulating layer 108 becomes thicker, the distance between the two first gate structures becomes larger. In other words, if the width of the second portion is too wide, the distance between the first gate structures cannot be reduced. As a result, the critical size cannot be reduced, which is not conducive to miniaturization of the memory device.

On the other hand, in the fourth etching process for forming the holes 145, the second contact member 140 can serve as an etching stop layer, and the second insulating layer 112 and the third insulating layer 114 are protected from being removed by the fourth etching process. However, since the width of the hole 145 is similar to the width of the second contact member 140. If the position of the second contact member 140 and the position of the hole 145 are not aligned during the fourth etching process, the fourth etching process may remove the second insulation layer 112 and the third insulation located on both sides of the second contact member 140. Layer 114. Then, when the conductive material used to form the capacitor structure is filled into the hole 145, these conductive materials are filled into the second insulating layer 112 and the third insulating layer 114. As a result, the operation of the memory device will be wrong, and the yield of the final product will be reduced. Such a problem is more serious when the critical size is reduced. In addition, to align the position of the second contact member 140 very accurately The location of the hole 145 is very difficult to manufacture and may consume extra time and cost.

In response to the foregoing problems, the second contact member 140 of the present invention has a second portion having a relatively narrow width. Therefore, the second contact member 140 can reduce the critical size and the miniaturization of the memory device. On the other hand, since the second contact member 140 has a wider first portion, the alignment of the second contact member 140 and the hole 145 can be easier (that is, the process window is larger), and further, Improve the yield of the final product. Therefore, it is possible to help improve the balance between the yield and the critical size of the memory device.

Please refer to FIG. 1C and FIG. 2 at the same time. After the first etching process, the width of the third insulating layer 114 is W3. After the second etching process, the width W2 of the second insulation layer 112 is substantially equal to the width W3 of the third insulation layer 114. On the other hand, since the second etching process hardly reduces the width of the first insulating layer 108, the width W1 of the first insulating layer 108 is greater than the width W2 of the second insulating layer 112. As such, for the self-aligned contact hole 125 formed in the second etching process, the width W6 of the lower portion is smaller than the width W7 of the upper portion.

The shape of the second contact member 140 is corresponding to and the same as the shape of the self-aligned contact hole 125. Therefore, by controlling parameter conditions of the second etching process, the shape of the self-aligned contact hole 125 (or the second contact member 140) can be easily adjusted. In this way, the use of the photomask and the number of lithographic processes can be reduced, thereby simplifying the process and reducing production costs.

In other words, as shown in FIG. 2, the width W7 of the top surface of the second contact member 140 has a ratio W7 / W6 to the width W6 of the bottom surface of the second contact member 140, and W7 / W6 can be adjusted to a specific value. Range while improving memory The balance between the yield of the device and the critical size. In some embodiments, W7 / W6 is 1.1-1.5. In some embodiments, W7 / W6 is 1.2-1.4. In other embodiments, W7 / W6 is 1.3.

In some embodiments, the fourth etching process is a wet etching process, and the etching solution may pass through the interface between the second contact member 140 and the third insulating layer 114 to reach the second insulating layer 112. Therefore, a part of the second insulating layer 112 will be removed, and voids will be generated in the second insulating layer 112. When the capacitor structure 160 is formed, a conductive material may fill the cavity, thereby reducing the insulation of the second insulating layer 112. As a result, operation errors of the memory device are caused, and the yield of the final product is reduced.

Referring to FIG. 2, the width W4 of the bottom surface of the fourth insulating layer 122 is greater than the width W3 of the top surface of the third insulating layer 114. In other words, the fourth insulating layer 122 covers the interface between the second contact member 140 and the third insulating layer 114. Furthermore, the bottom surface of the fourth insulating layer 122 is flush with the top surface of the second contact member 140 and is in direct contact, as shown in FIG. 2. Because the fourth etching process has a slower etching rate for the fourth insulating layer 122, the fourth insulating layer 122 having this specific shape can reduce or even completely prevent the etching solution from reaching the second insulating layer 112 through the interface. In this way, the problem of incorrect operation of the memory device can be greatly improved.

Furthermore, the fourth insulating layer 122 has a cross-sectional profile that gradually narrows upward, as shown in FIG. 2. Since the shape of the bottom of the hole 145 corresponds to the shape of the fourth insulating layer 122, the bottom of the hole 145 has a cross-sectional profile that gradually narrows downward. In other words, the width of the bottom of the hole 145 is smaller than the width of the upper portion.

If the holes 145 have a uniform width from the top to the bottom, it is difficult to balance the yield and the critical size of the memory device. More specifically, if When the width of the hole 145 is too large, the alignment of the second contact member 140 and the hole 145 becomes very difficult, and the critical size cannot be reduced, which is not conducive to miniaturization of the memory device. On the other hand, if the width of the hole 145 is too small, the depth-to-width ratio of the hole 145 is too high, and it is difficult to fill the hole structure 145 with the material forming the capacitor structure 160 well, which leads to a decrease in the yield of the final product.

Since the hole 145 has a lower portion with a narrower width, the alignment of the second contact member 140 and the hole 145, the reduction in the critical size, and the miniaturization of the memory device can be facilitated. On the other hand, since the hole 145 has a wide upper portion, the formation of the capacitor structure 160 (ie, the filling of the hole 145) can be easier, and the yield of the final product can be improved. Therefore, it is possible to help improve the balance between the yield and the critical size of the memory device.

The ratio of the width W4 of the bottom surface 122B of the fourth insulating layer 122 to the width W5 of the top surface 122T of the fourth insulating layer 122 is W4 / W5, as shown in FIG. 2. In other words, by adjusting W4 / W5 to a specific range, the balance between the yield of the memory device and the critical size can be further improved. In some embodiments, W4 / W5 is 1.1-3.0. In some embodiments, W4 / W5 is 1.3-2.5. In other embodiments, W4 / W5 is 1.5-2.0.

In the structure shown in FIG. 2, the thickness and cross-sectional profile of the fourth insulating layer 122 are also important parameters that affect the yield of the memory device 100.

Referring to FIG. 2, the fourth insulating layer 122 has a maximum thickness T1. If T1 is too small, the protruding portion of the fourth insulating layer 122 at the bottom of the hole 145 will be too thin to effectively block the etching solution and protect the second insulating layer 112. Conversely, if T1 is too large, it is difficult to remove enough fourth insulating layer 122 through the fourth etching process to form an opening exposing the second contact member 140. So to improve The yield rate can control the maximum thickness T1 of the fourth insulating layer 122 within a specific range. In some embodiments, the maximum thickness T1 of the fourth insulating layer is 10-60 nm. In some embodiments, T1 is 20-50 nm. In other embodiments, T1 is 30-40 nm.

Referring to FIG. 2, the sidewall 122S of the fourth insulating layer 122 and the bottom surface 122B of the fourth insulating layer 122 have an included angle θ, and the included angle θ can be used to describe the cross-sectional profile of the fourth insulating layer 122.

If the included angle θ is too small, it means that the fourth insulating layer 122 is gradually narrowed. Therefore, the protruding portion of the fourth insulating layer 122 is relatively thin, which cannot effectively block the etching solution and protect the second insulating layer 112. In addition, under the condition that the maximum thickness T1 of the fourth insulating layer 122 is the same, a smaller included angle θ indicates that the area of the second contact member 140 exposed by the hole 145 is smaller (that is, the width W8 is smaller). Therefore, The resistance value between the capacitor structure 160 and the second contact member 140 is increased accordingly, which is not beneficial to the operation of the memory device 100. Conversely, if the included angle θ is too large, it means that the fourth insulating layer 122 is sharply narrowed. Therefore, under the condition that the maximum thickness T1 of the fourth insulating layer 122 is the same, a larger included angle θ indicates that the protruding portion of the fourth insulating layer 122 is shorter (or narrower), which cannot effectively block the etching solution and protect the second The insulating layer 112 and the third insulating layer 114. Furthermore, a larger included angle θ indicates that the area of the second contact member 140 exposed by the hole 145 is larger (that is, the width W8 is larger), and the alignment of the second contact member 140 and the hole 145 becomes difficult, which is not favorable. Improve the yield of the final product. Therefore, in order to improve the yield, the included angle θ can be controlled within a specific range. In some embodiments, the included angle θ is 20-60 degrees. In other embodiments, θ is 30-50 degrees.

In addition, in some embodiments, the second etching process is performed first. After the opening 127 having a smaller width is formed, the width of the upper portion of the opening 127 is increased by a third etching process to form a source / drain contact hole 133. Since the width of the lower portion of the source / drain contact hole 133 is small, the available area of the substrate 102 can be reduced, which is beneficial to miniaturization of the memory device. On the other hand, the width of the upper portion of the source / drain contact hole 133 is large, which makes it easier to fill the second conductive material 121, and reduces the formation of holes in the source / drain contact plug 144 . It is beneficial to reduce the resistance value of the source / drain contact plug 144. In this case, by the second etching process and the third etching process, the source / drain contact plug 144 having the above-mentioned cross-sectional profile can be simply formed. Compared with the conventional technology, it can simplify the process steps and reduce the production cost.

Some embodiments of the present invention provide a memory device. Referring to FIG. 1L, the memory device 100 of the present invention may include a substrate 102 having an array region 10 and a peripheral region 20. In the array region 10, a plurality of first gate structures are formed on the substrate 102, and a multilayer insulation structure is formed on the first gate structures. The multilayer insulation structure includes a first insulation layer 108, a second insulation layer 112, a third insulation layer 114, and a fourth insulation layer 122 in this order from bottom to top. The first insulating layer 108 is formed on the first gate structure and covers the first gate structure.

Referring to FIG. 2, the width W2 of the second insulating layer 112 is smaller than the width W1 of the first insulating layer 108. The width W3 of the third insulating layer 114 is the same as the width W2 of the second insulating layer 112. A width W4 of a bottom surface of the fourth insulating layer 122 is larger than a width W3 of a top surface of the third insulating layer 112. The width of the bottom surface W4 of the fourth insulating layer 122 is greater than the width W5 of the top surface of the fourth insulating layer 122. The first insulating layer 108, the second insulating layer 112, the third insulating layer 114, and the fourth insulating layer 122 can be adjusted by selecting appropriate materials and controlling the parameter conditions of the second etching process. Relative thickness.

There are a plurality of capacitive contact plugs in the array region 10, and each capacitive contact plug is formed between two adjacent first gate structures. The capacitive contact plug includes a first contact member 150, a buffer layer 130, and a second contact member 140 in this order from bottom to top. The second contact member 140 includes a first portion extending downward from a bottom surface of the fourth insulating layer, a second portion extending upward from a top surface of the buffer layer 130, and a third portion formed between the first portion and the second portion. section. The third portion is adjacent to the first portion and the second portion, and gradually narrows toward the second portion. The width W7 of the top surface of the second contact member 140 is larger than the width W6 of the bottom surface of the second contact member 140, as shown in FIG. 2.

Referring to FIG. 1L, a fifth insulating layer 124 is formed in the array region 10, and a plurality of capacitor structures 160 are formed between the fifth insulating layers 124. Each capacitor structure 160 is formed on a capacitor contact plug, and its position corresponds to the position of the capacitor contact plug. Referring to FIG. 2, the width of the fifth insulating layer 124 is equal to the width W5 of the top surface of the fourth insulating layer 122. The width W8 of the bottom of the capacitor structure 160 is smaller than the width W7 of the top surface of the second contact member 140.

Still referring to FIG. 1L, a plurality of second gate structures are formed in the peripheral region 20. The gate contact plug 142 is formed on the second gate structure, and its position corresponds to the position of the second gate structure. Two source / drain contact plugs 144 are formed on both sides of the second gate structure, respectively. The source / drain contact plug 144 includes an upper portion and a lower portion, and a width of a bottom surface of the upper portion is greater than a width of a top surface of the lower portion.

As described above, in some embodiments, by controlling the cross-sectional profiles of the second contact member 140 and the fourth insulating layer 122, the memory device can be greatly improved. The yield of the device is balanced with the critical size.

Referring to FIG. 2, in some embodiments, the fourth insulating layer 122 has a top surface 122T, a bottom surface 122B, and a sidewall 122S. The sidewall 122S is linear, and the sidewall 122S and the bottom surface 122B have an included angle θ. However, the cross-sectional profile of the fourth insulating layer 122 is not limited thereto.

FIG. 3 is a schematic cross-sectional view of a fourth insulating layer according to some embodiments of the present invention. The fourth insulating layer 222 in FIG. 3 has a top surface 222T, a bottom surface 222B, and a side wall 222S, and the side wall 222S and the bottom surface 222B have an included angle θ. Please refer to FIG. 2 and FIG. 3 at the same time. The fourth insulating layer 222 of FIG. 3 is similar to the fourth insulating layer 122 of FIG. 2 except that the sidewall 222S of FIG. In addition, the sidewall 322S of the fourth insulating layer 322 in FIG. 3 is convexly curved. In addition, the side wall 422S of the fourth insulating layer 422 in FIG. 3 has an irregular zigzag shape. The cross-sectional profile of the fourth insulating layer shown in FIG. 2 and FIG. 3 is for illustration only, and is not intended to limit the present invention. Therefore, the cross-sectional profile of the sidewall of the fourth insulating layer may be linear, curved, sawtoothed, irregular, or a combination thereof.

In summary, some embodiments of the present invention provide a memory device with improved yield and critical size. Furthermore, some embodiments of the present invention provide a low-cost and high-efficiency manufacturing method that can be used to form a memory device with improved yield and critical size.

Specifically, the advantages of the memory device and the manufacturing method thereof provided by the embodiments of the present invention include at least:

(1) The second contact member includes a lower portion with a smaller width, which can reduce the critical size and is beneficial to miniaturization of the memory device.

(2) The second contact member includes an upper portion having a larger width, which enables the second contact portion The alignment of the component and the capacitor structure is relatively easy (increasing the operating window), thereby improving the yield of the final product.

(3) The capacitor structure includes a lower portion that gradually narrows downward, which can further increase the operating window, thereby improving the yield of the final product.

(4) The fourth insulating layer covers the interface between the third insulating layer and the second contact member, and the width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer, which can effectively block the etching solution and the Protect the second insulation layer and further improve the yield of the final product.

(5) The fourth insulating layer has a gradually narrowing upward profile, which can effectively block the etching solution and protect the second insulating layer 112, and can make the alignment of the second contact member and the capacitor structure easier, which can greatly improve the final Product yield.

(6) The relative relationship between the thicknesses of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be adjusted by selecting appropriate materials and controlling the parameter conditions of the second etching process. Therefore, no complicated process steps are needed to form insulating layers with different widths. In this way, the time and cost of production can be reduced.

(7) The manufacturing method of the memory device provided by the embodiment of the present invention can be easily integrated into the existing memory device manufacturing process without additional replacement or modification of production equipment. Under the premise of reducing process complexity and production cost, the yield and critical size of the memory device can be effectively improved.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, therefore, the scope of protection of the present invention shall be defined as quasi.

Claims (18)

A memory device includes: a substrate, wherein the substrate includes an array region and a peripheral region; two first gate structures are formed in the array region; and a multi-layer insulation structure is formed on the first gates. Structurally, the multilayer insulating structure includes: a first insulating layer formed on the first gate structures and covering the first gate structures; a second insulating layer formed on the first insulating layer The width of the second insulation layer is smaller than the width of the first insulation layer; a third insulation layer is formed on the second insulation layer; and the width of the third insulation layer is the same as that of the second insulation layer. A width; and a fourth insulating layer formed on the third insulating layer, wherein a width of a bottom surface of the fourth insulating layer is greater than a width of a top surface of the third insulating layer; and a capacitor contact plug, Formed between the first gate structures, wherein the capacitive contact plug includes: a first contact member formed on the substrate; a second contact member formed on the first contact member, wherein the first Two contact parts It is greater than the width of the top surface of the second contact member is a bottom surface; and a buffer layer formed between the first contact member and the second contact member. The memory device according to item 1 of the scope of patent application, wherein the bottom surface of the fourth insulation layer is flush with and directly contacts the top surface of the second contact member. The memory device according to item 1 of the application, wherein the fourth insulating layer has a cross-sectional profile that gradually narrows upward. The memory device according to item 1 of the application, wherein the ratio of the width of the bottom surface of the fourth insulating layer to the width of the top surface of the fourth insulating layer is 1.1-3.0. The memory device according to item 1 of the scope of the patent application, wherein an angle between a sidewall of the fourth insulation layer and the bottom surface of the fourth insulation layer is 20-60 degrees. The memory device according to item 5 of the scope of patent application, wherein the sidewall of the fourth insulating layer is linear, curved, jagged, or irregular. The memory device according to item 1 of the scope of patent application, wherein the maximum thickness of the fourth insulating layer is 10-60 nm. The memory device according to item 1 of the patent application scope, wherein the second contact member includes: a first portion extending downward from the bottom surface of the fourth insulating layer; and a second portion extending from the buffer layer. A top surface extends upward; and a third portion is formed between the first portion and the second portion and is adjacent to the first portion and the second portion, wherein the third portion gradually narrows toward the second portion. . The memory device according to item 5 of the application, wherein a ratio of a width of the top surface of the second contact member to a width of the bottom surface of the second contact member is 1.1 to 1.5. According to the memory device of claim 1, wherein the bottom surface of the second contact member is higher than a top surface of the first gate structure. The memory device according to item 1 of the application, wherein the material of the second insulating layer is different from the material of the first insulating layer, and the material of the second insulating layer is different from the material of the third insulating layer. The memory device according to item 11 of the scope of patent application, wherein the first insulating layer is a nitride, the second insulating layer is an oxide, the third insulating layer is a nitride, and the fourth insulating layer is nitrogen Compound. The memory device according to item 1 of the scope of patent application, further comprising: a fifth insulating layer formed on the fourth insulating layer, wherein a material of the fifth insulating layer is different from a material of the fourth insulating layer; And a capacitor structure formed on the capacitor contact plug. The memory device according to item 1 of the patent application scope further includes: a second gate structure formed in the peripheral region; a gate contact plug formed on the second gate structure; a source A pole / drain contact plug is formed on the substrate, wherein the source / drain contact plug includes an upper portion and a lower portion, and a bottom surface of the upper portion is wider than a top surface of the lower portion. The width. A method for manufacturing a memory device includes: providing a substrate, wherein the substrate includes an array region and a peripheral region; forming two first gate structures in the array region; and forming a multi-layer insulation structure on the first regions On the gate structure, the multilayer insulation structure includes: a first insulating layer formed on the first gate structures and covering the first gate structures; a second insulating layer formed on the first On the insulating layer, the width of the second insulating layer is smaller than the width of the first insulating layer; a third insulating layer is formed on the second insulating layer, and the third insulating layer has the same width as the second insulating layer A width of the layer; and a fourth insulating layer formed on the third insulating layer, wherein a width of a bottom surface of the fourth insulating layer is greater than a width of a top surface of the third insulating layer; and forming a capacitive contact A plug is between the first gate structures, wherein the capacitive contact plug includes: a first contact member formed on the substrate; a second contact member formed on the first contact member, wherein the Second pick Width of a top surface of the second member is larger than a bottom surface of the contact member; and a buffer layer formed between the first contact member and the second contact member. The method for manufacturing a memory device according to item 15 of the scope of patent application, wherein forming the multilayer insulation structure includes: forming the second insulation layer in the array region to cover the first gate structures and the first An insulating layer, wherein the second insulating layer has a flat top surface; forming the third insulating layer on the second insulating layer, wherein the third insulating layer has a uniform thickness in the array region; performing a first An etching process is used to pattern the third insulating layer, wherein the width of the patterned third insulating layer is smaller than the width of the first insulating layer below it; the patterned third insulating layer is used as a mask Performing a second etching process to remove a portion of the second insulating layer and form an opening between the first gate structures; and filling a conductive material into the opening to form the second contact A component; forming the fourth insulating layer on the third insulating layer and the second contact member; and performing a third etching process to remove a portion of the fourth insulating layer and exposing a portion of the second contact The top surface of the component The method for manufacturing a memory device according to item 16 of the scope of the patent application, wherein in the second etching process, a ratio of an etching rate of the second insulating layer to an etching rate of the first insulating layer is 5-50. According to the method for manufacturing a memory device described in item 16 of the scope of patent application, after forming the fourth insulating layer, the method further includes: forming a fifth insulating layer on the fourth insulating layer; and performing the third etching process, Removing a portion of the fourth insulating layer and the fifth insulating layer, and forming a hole in the fifth insulating layer on the top surface of the second contact member; and forming a capacitor structure in the hole, wherein The bottom surface of the capacitor structure directly contacts the top surface of the second contact member.