CN110610922B - Contact structure and forming method thereof - Google Patents
Contact structure and forming method thereof Download PDFInfo
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- CN110610922B CN110610922B CN201810613178.1A CN201810613178A CN110610922B CN 110610922 B CN110610922 B CN 110610922B CN 201810613178 A CN201810613178 A CN 201810613178A CN 110610922 B CN110610922 B CN 110610922B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The invention discloses a contact structure and a forming method thereof. The contact structure includes an insulating layer formed on a substrate. The contact structure includes a conductive member formed on the substrate and in the insulating layer. The contact structure includes a first liner layer formed in the insulating layer and on sidewalls of an upper portion of the conductive feature. The contact structure includes a second liner layer formed on a sidewall of the conductive feature. The second liner and the conductive feature form a conductive contact plug. At an upper portion of the conductive feature, a second liner is interposed between the conductive feature and the first liner. At a lower portion of the conductive feature, a second liner layer is interposed between the conductive feature and the insulating layer.
Description
Technical Field
The present invention relates to a memory device, and more particularly, to a contact structure and a method for forming the same.
Background
As portable electronic products become more popular, the demand for memory devices is increasing. All portable electronic products (e.g., digital cameras, notebook computers, mobile phones, etc.) require a small and reliable memory device to facilitate data storage and transmission.
With the trend of increasingly miniaturized electronic products, there is an increasing demand for miniaturization of memory devices. However, as memory devices are miniaturized, it becomes more difficult to improve the performance, durability, yield, and reliability of the products. Therefore, there is still a need for a memory device and a method for forming the same that has high performance, high endurance, high yield and high reliability.
Disclosure of Invention
An embodiment of the present invention discloses a contact structure, including: an insulating layer formed on the substrate; a conductive member formed on the substrate and located in the insulating layer; a first liner layer formed in the insulating layer and on sidewalls of an upper portion of the conductive feature; and a second liner layer formed on a sidewall of the conductive feature, wherein the second liner layer and the conductive feature form a conductive contact plug, and wherein at an upper portion of the conductive feature, the second liner layer is between the conductive feature and the first liner layer, and at a lower portion of the conductive feature, the second liner layer is between the conductive feature and the insulating layer.
Another embodiment of the present invention discloses a method for forming a contact structure, comprising: forming an insulating layer on the substrate; performing a first etching process to form a contact opening in the insulating layer; conformally forming a first liner material on the side wall and the bottom of the contact opening; performing a second etching process to remove the first liner material on the bottom of the contact opening and increase the depth of the contact opening, wherein the first liner material remained on the sidewall of the contact opening forms a first liner; forming a second liner layer on the sidewall and the bottom of the contact opening; and filling a conductive material in the contact opening to form a conductive part on the substrate and in the insulating layer, wherein the second liner layer and the conductive part form a conductive contact plug, and wherein at an upper portion of the conductive part, the second liner layer is between the conductive part and the first liner layer, and at a lower portion of the conductive part, the second liner layer is between the conductive part and the insulating layer.
Another embodiment of the present invention discloses a memory device, including: an insulating layer formed on a substrate, wherein the substrate includes a plurality of groups of regions and a peripheral region; and at least one contact structure as described above disposed in the peripheral region.
In order to make the aforementioned and other objects, features, and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
Fig. 1A-1H are schematic cross-sectional views of a memory device at various stages of processing according to some embodiments of the invention.
Fig. 2 is a cross-sectional view of a memory device at a stage in processing according to other embodiments of the present invention.
Fig. 3 is a cross-sectional view of a memory device at a stage in processing according to other embodiments of the present invention.
100-memory device
102 to substrate
106-grid structure
106a polysilicon gate
106 b-metal gate
108 spacer layer
110 to the first insulating layer
110 a-first sublayer
110 b-second sublayer
112 to second insulating layer
115-contact opening
115 a-upper part
115 b-lower part
120-first underlayer
120' to the first liner layer material
120a to lower part
120 b-upper part
140-conductive contact plug
140a to second liner layer
140 a' second liner material
140 b-conductive member
140 b' conductive material
150-conductive circuit
300-memory device
315 contact opening
315 a-upper part
315 b-lower part
500-memory device
515 contact opening
515a to first part
515b to second part
515c to third part
H1-first height
H2-second height
W1 first width
W2 second Width
W3-third Width
Detailed Description
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the relative dimensional proportions or numbers of the various features may be arbitrarily increased or decreased for clarity of illustration. Moreover, repeated reference characters and/or words may be used in various examples of the embodiments. These repeated symbols or words are used for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structure.
As used herein, the term "about" generally means within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The amounts given herein are approximate, meaning that the meaning of "about" or "approximately" may still be implied without particular recitation.
Some embodiments of the present invention provide a memory device and a method of forming the same. More particularly, embodiments of the present invention provide a contact structure included in a memory device and a method of forming the same. Fig. 1A-1H are cross-sectional views of a memory device 100 at various stages of fabrication according to some embodiments of the invention.
Referring to fig. 1A, the memory device 100 includes a substrate 102, and the substrate 102 includes a plurality of regions and a peripheral region. For simplicity, fig. 1A to 1H only show the peripheral region of the memory device 100, and the array region is omitted. However, such omission is for the sake of explanation and is not intended to be limiting. In the present embodiment, the contact structure described below is formed in the peripheral region. In some embodiments, the contact structures may be formed in the array region. In other embodiments, the contact structures may be formed in the array region and the peripheral region.
Referring to fig. 1A, a gate structure 106 is formed on the substrate 102 in the peripheral region. In the present embodiment, the gate structure 106 includes a polysilicon gate 106a and a metal gate 106b stacked on the polysilicon gate 106 a. It should be understood that fig. 1A is simplified. Fig. 1A may include other features not shown, such as shallow trench isolation structures, gate dielectric layers, or other features included in a memory device.
The material of the substrate 102 may include silicon, a silicon-containing semiconductor, a silicon-on-insulator (SOI), other suitable materials, or a combination thereof. The material of the metal gate 106b may include, for example, tungsten, aluminum, copper, gold, silver, tantalum, hafnium, zirconium, alloys thereof, or other suitable metal materials. The gate structure 106 may be formed by a suitable process. For example, the polysilicon layer and the metal layer may be patterned after sequentially depositing the polysilicon layer and the metal layer. Thus, the gate structure 106 is formed.
Next, a spacer layer 108 is formed on the substrate 102, and the spacer layer 108 conformally covers the sidewalls and the top portion of the gate structure 106. The material of the spacer layer may include, for example, a nitride, an oxide, an oxynitride, other suitable insulating material, or a combination thereof. In the present embodiment, the spacer layer 108 has a single-layer structure, and the spacer layer 108 is a nitride layer. In other embodiments, the spacer layer 108 is a bilayer structure or a multilayer structure.
Next, a first insulating layer 110 is formed on the substrate 102 to completely cover the substrate 102 and the spacer layer 108. Thereafter, a planarization process is performed to expose the top surface of the spacer layer 108. The material of the first insulating layer 110 may include an oxide, an oxynitride, other suitable insulating materials, or a combination thereof. It should be noted that the material of the first insulating layer 110 is different from the material of the spacer layer 108 in order to facilitate the subsequent processes. In the present embodiment, the spacer layer 108 is a nitride (e.g., silicon nitride), and the first insulating layer 110 is an oxide (e.g., silicon oxide).
Still referring to fig. 1A, a second insulating layer 112 may be deposited on the substrate 102 as needed. The material of the second insulating layer 112 may be the same as or different from the material of the first insulating layer 110. The second insulating layer 112 may protect the spacer layer 108 (not shown) of the array region from damage during subsequent processes. In other embodiments, an additional protection layer (not shown) may be formed on the array region during subsequent processes, and the second insulating layer 112 formed in the peripheral region may be omitted.
Referring to fig. 1B, a first etching process is performed to form a contact opening 115 in the first insulating layer 110 and the second insulating layer 112. The first etching process may include a dry etching process, a wet etching process or a combination thereof.
Referring to fig. 1C, a first liner material 120' is conformally formed on the second insulating layer 112 and in the contact opening 115. More specifically, the first liner material 120' is formed on the bottom and sidewalls of the contact opening 115. The process of forming the first liner material 120' may include a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or combinations thereof. The first liner material 120' may comprise nitride, oxynitride, carbide, polysilicon, other suitable insulating materials, or combinations thereof. In the present embodiment, the first liner material 120' is silicon nitride.
Referring to fig. 1D, a second etch process is then performed to remove the first liner material 120' located on the bottom of the contact opening 115 and to increase the depth of the contact opening 115. The second etching process may be anisotropic etching. More specifically, the second etching process may be a two-step etching process. In the first step of the second etch process, the first liner material 120 'on the bottom of the contact opening 115 is removed and the first liner material 120' on the sidewalls of the contact opening 115 remains. In the second step of the second etching process, the first insulating layer 110 under the contact opening 115 is removed to increase the depth of the contact opening 115.
Referring to fig. 1D, after the second etching process, the first liner material 120' remaining on the sidewalls of the contact opening 115 forms a first liner 120. After the second etching process, the contact opening 115 may be divided into a lower portion 115b and an upper portion 115 a. The upper portion 115a has a substantially uniform width from top to bottom, and the lower portion 115b has a tapered width from top to bottom.
Then, at least one wet process is performed. The wet process may include a wet cleaning process and a wet etching process. The conductive contact plug to be subsequently formed functions to provide an electrical connection. If an insulating material exists at the interface between the conductive contact plug and the substrate 102 (or the metal silicide layer), the resistance between the conductive contact plug and the substrate 102 (or the conductive contact plug and the metal silicide layer) may be greatly increased, and the operating voltage may be increased. This results in increased power consumption of the memory device and reduced performance and durability of the memory device. In order to prevent the insulating material from remaining on the surface of the substrate 102 (or the metal silicide layer), at least one wet cleaning process may be performed to remove the insulating material during the subsequent processes. In addition, the width of the lower portion 115b of the contact opening 115 is gradually narrowed from the top to the bottom due to the high aspect ratio. Therefore, the interface area between the conductive contact plug and the substrate 102 is too small, and the resistance value is too high. In order to increase the interface area, a wet etching process may be optionally performed before the formation of the metal silicide.
After the wet process, the width of the lower portion 115b of the contact opening 115 is increased, and the lower portion 115b of the contact opening 115 has a substantially uniform width from the top to the bottom, as shown in fig. 1E.
Referring to fig. 1F, a metal material is deposited on the bottom of the contact opening 115, and a metal silicidation process is performed. In the silicidation process, the metal material and the silicon of the substrate 102 are silicidated at a high temperature to form a metal silicide layer 122 at the bottom of the contact opening 115. The metallic material may include cobalt, nickel, tungsten, other suitable metallic materials, or combinations thereof.
Next, a second liner material 140 a' is conformally formed on the second insulating layer 112 and in the contact opening 115. As shown in fig. 1F, a second liner material 140 a' is formed on the sidewalls and bottom of the contact opening 115. The second liner material 140 a' may comprise a metal, an alloy, a metal nitride, other conductive material, or combinations thereof. In some embodiments, the second liner material 140 a' comprises titanium, tantalum, titanium nitride, or tantalum nitride. The process of forming the second liner material 140 a' may include a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or a combination thereof.
Still referring to fig. 1F, a conductive material 140 b' is formed on the second insulating layer 112 and filled in the contact opening 115. The conductive material 140 b' may include a metal, such as tungsten, aluminum, copper, gold, silver, other suitable metallic materials, or combinations thereof. The process of forming the conductive material 140 b' may include a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or a combination thereof.
The adhesion between the conductive material 140 b' and the insulating layers (e.g., the first insulating layer 110, the second insulating layer 112, and the first liner layer 120) is poor. By forming the second liner layer 140a, the adhesion between the conductive material 140b 'and the insulating layer can be improved, and delamination of the conductive material 140 b' can be prevented. In this way, the yield of the memory device 100 can be improved.
Referring to fig. 1G, a planarization process is then performed to remove a portion of the second insulating layer 112, a portion of the first liner layer 120, a portion of the second liner layer material 140a ', and a portion of the conductive material 140 b', and form the second liner layer 140a and the conductive feature 140b in the contact opening 115. In the present embodiment, the conductive contact plug 140 is formed of a second liner layer 140a and a conductive member 140 b. Therefore, the second liner layer 140a and the conductive member 140b are collectively referred to as a conductive contact plug 140 in this specification. After the planarization process, the top surface of the second insulating layer 112, the top surface of the first liner layer 120, and the top surface of the conductive contact plug 140 are coplanar.
Referring to fig. 1G, a first liner layer 120 is formed on the sidewalls of the upper portion of the conductive feature 140 b. In some embodiments, the first liner 120 surrounds an upper portion of the conductive member 140 b. Further, at an upper portion of the conductive member 140b, the second liner 140a is interposed between the conductive member 140b and the first liner 120. In addition, at a lower portion of the conductive member 140b, a second liner layer 140a is interposed between the conductive member 140b and the first insulating layer 110. In other words, there are two liners above the conductive feature 140b and only one liner below the conductive feature 140 b.
Referring to fig. 1H, a conductive line 150 is formed on the second insulating layer 112. The conductive traces 150 may electrically connect the conductive contact plugs 140 to other components of the memory device 100 or to external circuitry. For example, the conductive lines 150 may be formed by depositing a conductive material on the substrate 102 and patterning the conductive material. The conductive material used to form the conductive lines 150 may include a metal, such as aluminum, copper, gold, silver, tungsten, other suitable metal materials, or a combination thereof. The deposition process for forming the conductive line 150 may include a physical vapor deposition process, an atomic layer deposition process, a sputtering process, other suitable deposition processes, or a combination thereof. In some embodiments, the conductive material 140 b' comprises copper.
Generally, when forming an opening with a high aspect ratio (e.g., an aspect ratio greater than 4), the width of the opening gradually narrows from the top to the bottom. As described above, if the interface area between the contact opening 115 and the substrate 102 (or the metal silicide layer 122) is too small, the above-mentioned problem due to the excessively high resistance value may occur. The smaller the size of the memory device, the higher the aspect ratio of the opening. Therefore, the above-mentioned problem caused by the excessively high resistance value becomes more serious as the memory device is miniaturized.
To avoid the above problem, the wet etching process may be performed to increase the width of the bottom of the contact opening 115. However, in this case, the width of the top of the contact opening 115 is also increased. When forming the conductive contact plug 140 in such a contact opening 115 (i.e., a contact opening having an enlarged top width), the distance (distance in the horizontal direction) between the top of the conductive contact plug 140 and the adjacent conductive line 150 (e.g., the conductive line 150 located at the very middle of fig. 1H) becomes shorter. Therefore, the conductive contact plug 140 and the adjacent conductive line 150 may be short-circuited, and the operation of the memory device 100 may be erroneous. As a result, the yield and reliability of the memory device 100 are greatly reduced.
Furthermore, if the conductive lines 150 are patterned with a shift or deviation, the distance between the conductive contact plug 140 and the adjacent conductive line 150 may be further shortened, and the above-mentioned problem due to short circuit may become more serious.
On the other hand, in order to ensure that the insulating material does not remain on the surface of the substrate 102 (or the metal silicide layer 122), at least one of the above-mentioned wet cleaning processes may be performed. These wet cleaning processes all have the ability to remove insulating material (e.g., the first insulating layer 110 or the second insulating layer 112). In other words, the wet cleaning processes can also increase the width of the contact opening 115. Therefore, the above-described problem due to the short circuit may occur even without performing an additional wet etching process. The smaller the size of the memory device, the shorter the distance between the conductive contact plug 140 and the adjacent conductive line 150. Therefore, the above-mentioned problem due to the short circuit becomes more serious as the memory device is miniaturized.
In order to simultaneously improve or avoid the problems caused by the over-high resistance value and the short circuit, some embodiments of the invention provide a method for forming a contact structure.
Referring to fig. 1D, a first liner layer 120 is formed on the sidewalls of the contact opening 115, and then a second etching process is performed. The contact opening 115 thus obtained has a lower portion 115b and an upper portion 115 a. The first liner 120 is located on the sidewalls of the upper portion 115a, but is not located on the sidewalls of the lower portion 115 b. The first liner 120 may protect the upper portion 115a from being widened during a subsequent wet process (e.g., a wet cleaning process and/or a wet etching process). Thus, the problems caused by short circuit can be improved or avoided. On the other hand, no first liner layer 120 is present on the sidewalls of the lower portion 115 b. Therefore, the width of the lower portion 115b is enlarged in the subsequent wet process, as shown in fig. 1E. Therefore, the problem caused by overhigh resistance value can be improved or avoided.
In addition, the performance, durability, yield and reliability of the formed memory device 100 can be greatly improved at the same time due to the inclusion of the contact structure described above.
In order to avoid the increase of the width of the upper portion 115a, the selectivity of the first insulating layer 110 (and/or the second insulating layer 112) to the first liner layer 120 in the above-mentioned wet processes may be increased. In at least one of the wet processes, the removal rate (etching rate) of the first insulating layer 110 (and/or the second insulating layer 112) is R1, the removal rate (etching rate) of the first liner layer 120 is R2, and the ratio of the removal rate (etching rate) of the first insulating layer 110 (and/or the second insulating layer 112) to the removal rate (etching rate) of the first liner layer 120 is R1/R2. In some embodiments, in at least one of the wet processes, R1/R2 is 10-100. In other embodiments, R1/R2 is 20-80 in at least one of the wet processes. In still other embodiments, R1/R2 is 30-60 during at least one of the wet processes. After the wet process, the top surface of the first liner layer 120 is higher than the top surface of the second insulating layer 112, as shown in fig. 1E.
Referring to fig. 1G, the top surface of the conductive contact plug 140 has a second width W2, and the top surface of the first liner layer 120 has a third width W3. If the ratio of the second width W2 to the third width W3 is too small, the width of the opening 115 becomes too small, and the aspect ratio of the opening 115 becomes too high. Therefore, it becomes difficult to fill the conductive material 140 b' into the contact opening 115. As a result, holes are easily formed in the conductive contact plugs 140, thereby reducing the yield and reliability of the memory device 100. A similar problem occurs if the third width W3 is too large (i.e., the thickness of the first liner 120 is too thick). On the contrary, if the ratio of the second width W2 to the third width W3 is too large, the thickness of the first liner layer 120 is too thin to prevent the width of the upper portion 115a from being enlarged in the wet process. In this way, the above-described problem due to the short circuit may occur. Furthermore, if the ratio of the second width W2 to the third width W3 is too large, the distance between the conductive contact plug 140 and the adjacent conductive trace 150 may be too close. In this way, the above-described problem due to the short circuit may also occur.
Accordingly, the width of the top surface of the first liner layer 120 may be controlled to a specific range. As shown in fig. 1G, the top surface of the first liner layer 120 has a third width W3. In some embodiments, the third width W3 is 3-10 nm. In other embodiments, the third width W3 is 4-9 nm. In still other embodiments, the third width W3 is 5-8 nm. Further, the ratio of the second width W2 to the third width W3 may be controlled to be in a specific range. In some embodiments, the ratio W2/W3 of the second width W2 to the third width W3 is 5-40. In other embodiments, the ratio W2/W3 of the second width W2 to the third width W3 is 10-30. In still other embodiments, the ratio W2/W3 of the second width W2 to the third width W3 is 15-20.
Referring to fig. 1G, the bottom surface of the conductive contact plug 140 has a first width W1, and the top surface of the conductive contact plug 140 has a second width W2. In the present embodiment, the first width W1 is greater than the second width W2. In addition, if the ratio of the first width W1 to the second width W2 is too small, the first width W1 may not be large enough. Therefore, the contact area between the conductive contact plug 140 and the substrate 102 (or the metal silicide layer 122) cannot be increased greatly. Thus, the problem caused by the over-high resistance value cannot be greatly improved. Conversely, if the ratio of the first width W1 to the second width W2 is too large, the difference between the first width W1 and the second width W2 is too large. Therefore, it becomes difficult to fill the contact opening 115 with the second liner material 140a 'and the conductive material 140 b'. As a result, holes are easily formed in the conductive contact plugs 140, thereby reducing the yield of the memory device 100. Further, if the ratio of the first width W1 to the second width W2 is too large, the first width W1 may become too large. Thus, it takes up too much substrate real estate. This is not favorable for miniaturization of the memory device.
Therefore, the ratio of the first width W1 to the second width W2 may be controlled to be within a specific range. In some embodiments, the ratio W1/W2 of the first width W1 to the second width W2 is 1.1-1.4. In other embodiments, the ratio W1/W2 of the first width W1 to the second width W2 is 1.1-1.3. In still other embodiments, the ratio W1/W2 of the first width W1 to the second width W2 is 1.1-1.2.
Referring to fig. 1G, the first liner layer 120 has a first height H1, and the conductive contact plug 140 has a second height H2. If the ratio of the first height H1 to the second height H2 is too small, the depth of the upper portion 115b of the contact opening 115 having a smaller width is too shallow. Therefore, the distance between the lower portion of the conductive contact plug 140 and the adjacent conductive line 150 may be formed too close. As a result, the above-described problem due to the short circuit may occur. Conversely, if the ratio of the first height H1 to the second height H2 is too large, less conductive material is filled into the contact opening 115. As a result, it is not favorable to reduce the resistance between the conductive contact plug 140 and the substrate 102. Furthermore, if the insulating first liner layer 120 extends to the surface of the substrate 102, the contact area between the conductive contact plug 140 and the substrate 102 is reduced. This is not favorable for reducing the resistance between the conductive contact plug 140 and the substrate 102.
Accordingly, the ratio of the first height H1 to the second height H2 may be controlled to be within a specific range. In some embodiments, the ratio of the first height H1 to the second height H2, H1/H2, is 0.1-0.8. In other embodiments, the ratio of the first height H1 to the second height H2, H1/H2, is 0.3-0.7. In still other embodiments, the ratio of the first height H1 to the second height H2, H1/H2, is 0.4-0.6.
In addition, referring to fig. 1E, the cross-sectional profile of the first liner 120 includes a lower portion 120a and an upper portion 120 b. The upper portion 120b of the first liner layer 120 extends downward from the top surface of the first liner layer 120, and the upper portion 120b is substantially perpendicular to the top surface of the second insulating layer 112. The lower portion 120a of the first liner layer 120 is adjacent to the upper portion 120b and extends along an oblique direction to the sidewalls of the first insulating layer 110. In other words, in the present embodiment, the lower portion 120a of the first liner 120 is tapered downward. Such a cross-sectional profile of the first liner 120 may facilitate the formation of the second liner 140a on the inner sidewalls of the contact opening 115. Furthermore, if the sidewalls of the lower portion 120a of the first liner 120 are perpendicular to the sidewalls of the upper portion 120b, the second liner 140a may have discontinuous portions at the interface between the lower portion 120a and the upper portion 120 b. Without the second liner layer 140a, delamination of the conductive features may occur therein, thereby reducing the yield of the memory device 100.
In contrast, in the present embodiment, the lower portion 120a of the first liner 120 is gradually narrowed in the inclined direction. Thus, the second liner layer 140a can be formed as a continuous film layer without discontinuous portions. Thus, the yield of the memory device 100 can be further improved.
Some embodiments of the present invention provide a memory device. Referring to fig. 1H, the memory device 100 of the present invention may include a substrate 102 having a plurality of sets of regions and a peripheral region. The memory device 100 also includes a gate structure 106 and a spacer layer 108 formed on the substrate 102. The spacer layer 108 conformally covers the sidewalls and top portion of the gate structure 106. Memory device 100 also includes contact structures located in the periphery region. The contact structure includes a first insulating layer 110 and a second insulating layer 112 formed on the substrate 102. The contact structure also includes a conductive contact plug 140 formed on the substrate and located in the first insulating layer 110 and the second insulating layer 112. The conductive contact plug 140 is formed of a conductive second liner 140a and a conductive member 140 b. The contact structure also includes an insulating first liner 120 disposed in the first insulating layer 110 and the second insulating layer 112. The first liner layer 120 surrounds and directly contacts an upper portion of the conductive contact plug 140. More specifically, the first liner 120 surrounds an upper portion of the conductive member 140 b. Further, at an upper portion of the conductive member 140b, the second liner 140a is interposed between the conductive member 140b and the first liner 120. In addition, at a lower portion of the conductive member 140b, a second liner layer 140a is interposed between the conductive member 140b and the first insulating layer 110. In other words, there are two liners above the conductive feature 140b and only one liner below the conductive feature 140 b.
Fig. 2 is a cross-sectional view of a memory device 300 at a stage in processing according to other embodiments of the present invention. Fig. 2 is similar to fig. 1E, except that contact opening 315 in fig. 2 has a substantially uniform width from top to bottom. Components in fig. 2 that are the same as those in fig. 1E are denoted by the same reference numerals. For simplicity, the elements and the steps of the process for forming the same as those in fig. 1E will not be described again. Further, after the structure shown in FIG. 2 is formed, the processes of FIGS. 1F-1H may be continued. For simplicity, the processes of fig. 1F to 1H are not described herein again.
Referring to fig. 2, in the present embodiment, by forming the first liner layer 120 on the sidewall of the upper portion 315a of the contact opening 315, the upper portion 315a and the lower portion 315b of the contact opening 315 may have a substantially uniform width. Accordingly, the first width W1 of the bottom surface of the conductive contact plug 140 can be formed to be equal to the second width W2 of the top surface of the conductive contact plug 140. As such, the performance, durability, yield, and reliability of the memory device 300 can be greatly improved. Further, in the present embodiment, the first width W1 does not become too large. Therefore, the memory device does not occupy too much of the available substrate area, thereby facilitating the miniaturization of the memory device.
Fig. 3 is a cross-sectional view of a memory device 500 at a stage in processing according to other embodiments of the present invention. Fig. 3 is similar to fig. 1E, with the difference that the first insulating layer 110 includes two sub-layers. Components in fig. 3 that are the same as those in fig. 1E are denoted by the same reference numerals. For simplicity, the elements and the steps of the process for forming the same as those in fig. 1E will not be described again. Further, after the structure shown in FIG. 3 is formed, the processes of FIGS. 1F-1H may be continued. For simplicity, the processes of fig. 1F to 1H are not described herein again.
Referring to fig. 3, prior to filling the second liner material 140a 'and the conductive material 140 b', the cross-sectional profile of the contact opening 515 may include a first portion 515a, a second portion 515b, and a third portion 515 c. The first portion 515a extends downward from the top portion of the contact opening 515. The second portion 515b extends upward from the bottom portion of the contact opening 515. The third portion 515c is formed between the first portion 515a and the second portion 515b, and is adjacent to the first portion 515a and the second portion 515 b. The third portion 515c is tapered toward the first portion 515 a. The cross-sectional profile of the subsequently formed conductive contact plug 140 is the same as the cross-sectional profile of the contact opening 515. More specifically, in the present embodiment, the cross-sectional profile of the conductive contact plug 140 includes a first portion, a second portion and a third portion. The first portion extends downward from the top surface of the conductive contact plug 140. The second portion extends upward from the bottom surface of the conductive contact plug 140. The third portion is formed between and adjacent to the first portion and the second portion, wherein the third portion tapers toward the first portion.
Referring to fig. 3, the first insulating layer 110 includes a first sub-layer 110a and a second sub-layer 110b formed on the first sub-layer 110 a. The boundary between the first sub-layer 110a and the second sub-layer 110b is substantially equal to the boundary between the second portion 515b and the third portion 515 c. In the present embodiment, the material of the first sub-layer 110a is different from the material of the second sub-layer 110 b. Therefore, in at least one of the wet processes, the etching rate of the first sub-layer 110a is different from the etching rate of the second sub-layer 110 b. Thus, the cross-sectional profiles of the contact openings 515 corresponding to the first sub-layer 110a and the second sub-layer 110b are different. More specifically, referring to fig. 3, after the wet process, the first sub-layer 110a has a substantially uniform width, and the second sub-layer 110b has a width gradually narrowing downward. The cross-sectional profile of the contact opening 515 is determined by the cross-sectional profile of the first insulating layer 110, and the cross-sectional profile of the contact opening 515 and the cross-sectional profile of the first insulating layer 110 are complementary to each other. Thus, the third portion 515c of the contact opening 515 has an upwardly tapering cross-sectional profile. In other words, the cross-sectional profile of the contact opening 515 may be adjusted to a desired shape as desired by selecting appropriate materials for forming the first sub-layer 110a and the second sub-layer 110 b. Therefore, the flexibility of the manufacturing process can be improved. The first sub-layer 110a and the second sub-layer 110b may independently include an oxide, oxynitride, or other suitable insulating material, and the material of the first sub-layer 110a is different from the material of the second sub-layer 110 b. In some embodiments, the first sub-layer 110a and the second sub-layer 110b may include a first oxide and a second oxide, respectively, and the first oxide and the second oxide are formed by different processes. In other embodiments, the first sub-layer 110a may comprise spin-on oxide (SPIN-ON oxide) and the second sub-layer 110b may comprise high density plasma oxide (HDP oxide). The number of sub-layers of the first insulating layer 110 shown in fig. 3 is for illustration only and is not intended to limit the invention. In other embodiments, the first insulating layer 110 may include three or more sub-layers.
The cross-sectional profile of the sidewall of the third portion 515c includes a rounded curved portion, thereby facilitating filling of the second liner material 140a 'and the conductive material 140 b' into the contact opening 515. Further, the amount of conductive material filled into the contact opening 515 increases. As a result, the resistance of the conductive plug 140 can be further reduced, and the performance and durability of the memory device 500 can be further improved.
The cross-sectional profiles of the contact openings shown in fig. 2 and 3 are for illustration purposes only and are not intended to be limiting. In some embodiments, the cross-sectional profile of the lower portion of the contact opening may be linear, curvilinear, serrated, irregular, or a combination thereof.
In summary, embodiments of the present invention provide a contact structure and a method for forming the same. Furthermore, some embodiments of the present invention provide a memory device including the contact structure, and the performance, durability, yield and reliability of the memory device can be significantly improved.
Although the present invention has been described with reference to a few preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A memory device, said memory device comprising:
a gate structure formed on a substrate; and
two contact structures formed on the substrate and located at two sides of the gate structure, wherein a bottom surface of the contact structures is flush with a bottom surface of the gate structure, and each contact structure comprises:
an insulating layer formed on the substrate;
a conductive member formed on the substrate and in the insulating layer;
a first liner formed in the insulating layer and on sidewalls of an upper portion of the conductive feature; and
a second liner layer formed on sidewalls of the conductive feature, wherein the second liner layer and the conductive feature form a conductive contact plug, and wherein at the upper portion of the conductive feature, the second liner layer is between the conductive feature and the first liner layer, and at a lower portion of the conductive feature, the second liner layer is between the conductive feature and the insulating layer;
the cross-sectional profile of the conductive contact plug includes:
a first portion extending downwardly from a top surface of the conductive contact plug;
a second portion extending upwardly from a bottom surface of the conductive contact plug; and
a third portion formed between and adjacent to the first portion and the second portion, wherein the third portion tapers toward the first portion.
2. The memory device of claim 1, wherein a bottom surface of the conductive contact plug has a first width W1, a top surface of the conductive contact plug has a second width W2, and wherein the first width W1 is greater than or equal to the second width W2.
3. The memory device of claim 2, wherein a ratio W1/W2 of the first width W1 to the second width W2 is 1.1-1.4.
4. The memory device of claim 1, wherein the cross-sectional profile of the first liner comprises:
an upper portion extending downwardly from a top surface of the first liner layer; and
a lower portion adjacent to the upper portion of the first liner, wherein the lower portion of the first liner tapers downwardly.
5. The memory device of claim 1, wherein a top surface of the first liner layer has a third width W3, and wherein the third width W3 is 3-10 nm.
6. The memory device of claim 2, wherein a top surface of the first liner layer has a third width W3, and wherein a ratio W2/W3 of the second width W2 to the third width W3 is 5-40.
7. The memory device of claim 1, wherein the first liner layer has a first height H1, the conductive contact plug has a second height H2, and wherein a ratio H1/H2 of the first height H1 to the second height H2 is 0.1-0.8.
8. A method of forming a contact structure, the method comprising:
forming an insulating layer on a substrate;
performing a first etching process to form a contact opening in the insulating layer;
conformally forming a first liner material on the side wall and the bottom of the contact opening;
performing a second etching process to remove the first liner material on the bottom of the contact opening and increase the depth of the contact opening, wherein the first liner material remaining on the sidewall of the contact opening forms a first liner layer, wherein the first liner layer does not cover a top surface of the insulating layer;
forming a second liner layer on the sidewall and the bottom of the contact opening; and
filling a conductive material in the contact opening to form a conductive feature on the substrate and in the insulating layer, wherein the second liner and the conductive feature form a conductive contact plug, and wherein at an upper portion of the conductive feature, the second liner is between the conductive feature and the first liner, and at a lower portion of the conductive feature, the second liner is between the conductive feature and the insulating layer, and wherein a cross-sectional profile of the conductive contact plug comprises:
a first portion extending downward from a top surface of the conductive contact plug;
a second portion extending upwardly from a bottom surface of the conductive contact plug; and
a third portion formed between and adjacent to the first portion and the second portion, wherein the third portion tapers toward the first portion.
9. The method of claim 8, wherein at least one wet process is performed after forming the first liner layer and before filling the conductive material.
10. The method of claim 9, wherein a ratio of an etch rate of the insulating layer to an etch rate of the first liner layer in the at least one wet process is in a range of 10-100.
11. The method of claim 8, wherein a bottom surface of the conductive contact plug has a first width W1, a top surface of the conductive contact plug has a second width W2, and wherein the first width W1 is greater than or equal to the second width W2.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083226A (en) * | 2006-05-30 | 2007-12-05 | 三星电子株式会社 | Semiconductor device having a contact structure with a contact spacer and method of fabricating the same |
| US20080182406A1 (en) * | 2007-01-31 | 2008-07-31 | Axel Preusse | Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime |
| US20090047781A1 (en) * | 2007-08-16 | 2009-02-19 | Dave Pratt | Methods of Forming Through Substrate Interconnects |
| US20100015797A1 (en) * | 2005-08-26 | 2010-01-21 | Toshio Saito | Manufacturing method of semiconductor device |
| US20110183512A1 (en) * | 2010-01-22 | 2011-07-28 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device having contact plug |
| US20150061134A1 (en) * | 2013-08-30 | 2015-03-05 | Eun-Ok Lee | Semiconductor devices including air gap spacers and methods of manufacturing the same |
| US20180019187A1 (en) * | 2016-07-14 | 2018-01-18 | Nxp Usa, Inc. | Method of integrating a copper plating process in a through-substrate-via (tsv) on cmos wafer |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6569778B2 (en) * | 2001-06-28 | 2003-05-27 | Hynix Semiconductor Inc. | Method for forming fine pattern in semiconductor device |
| TWI225686B (en) * | 2003-12-08 | 2004-12-21 | Nanya Technology Corp | Method of forming bit line contact |
| KR20090097426A (en) * | 2008-03-11 | 2009-09-16 | 주식회사 하이닉스반도체 | Method for forming contact of semiconductor device |
| KR101669470B1 (en) * | 2009-10-14 | 2016-10-26 | 삼성전자주식회사 | Semiconductor device including metal silicide layer |
| CN107910328B (en) * | 2017-12-12 | 2023-09-22 | 长鑫存储技术有限公司 | Method for manufacturing storage node contact in semiconductor device and semiconductor device |
-
2018
- 2018-06-14 CN CN201810613178.1A patent/CN110610922B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100015797A1 (en) * | 2005-08-26 | 2010-01-21 | Toshio Saito | Manufacturing method of semiconductor device |
| CN101083226A (en) * | 2006-05-30 | 2007-12-05 | 三星电子株式会社 | Semiconductor device having a contact structure with a contact spacer and method of fabricating the same |
| US20080182406A1 (en) * | 2007-01-31 | 2008-07-31 | Axel Preusse | Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime |
| US20090047781A1 (en) * | 2007-08-16 | 2009-02-19 | Dave Pratt | Methods of Forming Through Substrate Interconnects |
| US20110183512A1 (en) * | 2010-01-22 | 2011-07-28 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device having contact plug |
| US20150061134A1 (en) * | 2013-08-30 | 2015-03-05 | Eun-Ok Lee | Semiconductor devices including air gap spacers and methods of manufacturing the same |
| US20180019187A1 (en) * | 2016-07-14 | 2018-01-18 | Nxp Usa, Inc. | Method of integrating a copper plating process in a through-substrate-via (tsv) on cmos wafer |
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