TWI225686B - Method of forming bit line contact - Google Patents

Abstract

The present invention disclose a method of forming bit line contact, comprising providing a substrate having a plurality of transistors with a gate electrode and a doping area consisted of source and drain. A first dielectric layer is formed on the substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer and a portion of the first dielectric layer are removed on the bit line contact area. A protecting layer is formed on the second dielectric layer and a portion of the gate electrode and first dielectric layer. The second dielectric layer and the protecting layer on the gate electrode are ion doping, and the un-doped protecting layer is then removed. The first dielectric layer on the doping area surface of the bit line contact is removed to form a bit line contact. A conductive layer is finally filled into the bit line contact to form a bit line contact plug.

Description

1225686 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for a bit line contact window, and in particular to a method for manufacturing a bit line contact window with self-alignment (SAC). [Previous technology] In recent years, with the increase of the integration degree of integrated circuits, the design of semiconductor processes has also developed toward reducing the size of semiconductor components to increase the density. Taking currently widely used dynamic random access memory (DRAM) as an example, The 64M DRAM process has been switched from 0.35 micron to below 0.3 micron (/ zm), while 128M DRAM or 256M DRAM is moving towards 0.2 micron. When manufacturing high-density integrated circuit components such as dynamic random access memory (DRAM), the so-called self-aligned contact window (SAC) process is often used to improve the precision of the wires. However, as line widths continue to shrink, process difficulty continues to increase. Taking the filling process of the bit line contact window as an example, for some cutting-edge wafer manufacturers, when the line width is reduced to about 0. 11 microns, the width of the drain region exposed by the bit line contact window may be Only about 0.05 to 0.06 microns (50 to 60 nanometers). Therefore, when a conductive layer is formed in the bit line contact window as a bit line contact (CB), a bit line contact (CB ope η) or a word line bit line is prone to occur. A short circuit (word line-bi1: line short) defect occurs. As long as the above-mentioned defects of the bit line contact open circuit or the word line-bit line short circuit occur, it will cause the manufactured semiconductor device to fail, which will adversely affect the yield and cost of the semiconductor process. To further investigate the problem, the manufacturing process of the conventional technology is explained below. Please refer to Figures 1A to 1F for a series of cross-sectional views showing a

Page 6 0548-A50014TWf (Nl); 92103, 92126; yyhsu.ptd 1225686 V. Description of the invention (2) How to make a self-aligned bit line contact window is how to make the above bit line contact open or Word line—The defect of a bit line short. : First, provide a substrate 10, please refer to _. The substrate 10 has a structure of an electric sun, and has the drain regions 12 and the source regions 14 staggered at an interval on the active surface of the substrate 10. ; Between the drain region 12 and the source region 14, a gate 20 having a wide projection on the surface of the substrate 10, and the gate 20 has a multilayer structure according to various requirements, such as the gate 2 in FIG. 1A. In the order, a gate dielectric layer 21, a conductive layer 22, a gold silicide layer 23, and a hard mask layer 24 are sequentially arranged from the surface of the substrate 10 upward, and a gate electrode layer is formed on the side wall of the gate electrode 20. Silicon spacer wall 25. Since there is a gap wall 25 on the side wall of the gate electrode 20, the design of the semiconductor device (desi gn rule) reduces the line width to about 0.1 μm as described above, and the adjacent idler electrode 20 The width of the exposed drain region 12 between the spacers 25 is only about 0.05 μm to about 0.06 μm. Referring to FIG. 1B, a dielectric layer and a patterned resist layer 60 are sequentially formed on the substrate 10. The patterned resist layer 60 has an opening 60a, and the exposed portion of the opening 60a is formed subsequently. Position of the bit line contact window. The next step is to remove the dielectric layer 30 exposed at the opening 60a to the drain surface to form a dielectric window as a bit line contact window, and blow out the drain region 12, and A conductive layer is filled in the above interlayer window, and :: is a bit line contact plug. The steps in Figs. 1C to 1D show how to cause the above-mentioned defect of the bit line to open in the y step, and the steps in Figs. 1E to 1F show how to cause the above-mentioned character line in the above steps. -Defects in bit line shorts. Please refer to FIG. 1C. In an ideal case, the patterned resist layer 60 is

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The engraved mask performs anisotropic etching of the dielectric layer 30 to form a dielectric window 31 and expose the drain region 12. This completes the process of the bit line contact window: ^, as described above When the line width is about 0 · 丨 丨 microns, the thickness of the interlayer window 3 丨 (and the width of the pole region 12 is only about 0.05 ~ 0.06 microns, and the interlayer ", window 31 The system has a relatively high depth. Therefore, in the actual situation, in the $ electrical layer 30 at the bottom of the dielectric window L, the dielectric layer 30 closer to the drain region 12 is more difficult to be etched. When the engraving reaction is terminated, a small amount of residual dielectric 30a 'is left on the bottom 4 of the interlayer window 31 without being etched or incompletely etched, and the surface of the electrode region 12 is not exposed. There is a part of the residual dielectric layer 30a on the bottom of the 31 so that the surface of the electrode region 12 cannot be exposed. Please refer to FIG. 1d. Even after a barrier layer 40 is formed in the dielectric window 31, And filled with a conductive layer 50 as a bit line contact. In the case where the remaining dielectric layer 3 0 is not a conductor, the conductive layer 50 and the drain region 2 cannot be generated. The electrical connection causes the above-mentioned defect of the bit line contact open circuit. In order to avoid the defect of the bit line contact open circuit, a known practice is to use a self-aligned contact window etching process parameter with a lower selection ratio Etching of the contact window. However, in the process design of forming the bit line contact window, in order to avoid a short circuit between the gate electrode 20 serving as the bit line and the subsequent bit line contact, the conduction in the gate electrode 20 The polycrystalline silicon layer 22 and the metal silicide layer 23 are protected by a hard cover curtain layer 24 and a spacer 25, and are etched with a parameter having a high etching selection ratio to avoid the conductive layer in the gate electrode 20. The polycrystalline silicon layer 22 and the metal silicide layer 23 are exposed and a short circuit occurs with the bit line contact formed later. However, it is difficult

1225686 V. Description of the invention (4) Please refer to the first section, in addition to editing and selecting this method, in addition to the dielectric layer 30 remaining on the bottom of the dielectric substrate, 30 etch away, and the gap between 25 辟 and Λ will expand. 'A part of the hard cover curtain layer 24 and the chemical layer 23 are exposed to form a partition wall 25a, so that the silicon metal comes. Do n’t layer 23 blaze out, even the compound dream heart may also be exposed. After the metal dream layer 23 of the electrical layer, and fill in: as a step of forming a barrier layer 40 in the interlayer window 31a, as a step of conducting the conductive layer 50 in line contact, the conductive layer 50 is formed. It is electrically connected to the metallization of the conductive layer of the interrogation pole at 2 °, that is, the square that caused the short-circuit of the word line to the bit line, = ▲. In practice, it will also use a surname engraved (over (etchi ng) "I have caused bit line open contact defects, but because of the process of forming the bit window, the nitrided dream is generally used as the hard cover curtain. 24 fish gates 9R ::, so the dielectric layer 30 pairs Hard mask: The etching selection ratio of 24 to 25 and 25 is about 10. However, such a low = engraving selection ratio will also make it harder than Qveretching, that is, 24 and the spacer 25 are eroded and the metal silicide layer 22 is exposed, resulting in the word line bit described above. Yuan line short circuit. Therefore, it is highly desirable to add process steps to protect the semiconductor surface from causing the above problems. If so, the problems of production cost and production schedule caused by increasing the number of process steps are inevitable. [Summary of the Invention] 0548-A50014TWf (Nl); 92103, 92126 > yyhsu.ptd Page 9 1225686 V. Description of the invention (5) Miscellaneous # In view of this, the purpose of the present invention is to provide a kind of bit line connection = Surface method to avoid the problem that the gap between the gate electrodes is getting smaller and smaller, so as to avoid the bit line contacting open circuits (contact defects). Another purpose of this month is to provide a way to form bit lines. / Of the contact window can avoid the problem of short circuit between the sub-line and the bit line. In order to achieve the above purpose, the present invention proposes a doped protective layer for depositing a contact window to be deposited on the dielectric layer. Li Xing's characteristics of the selection ratio of 1 to 2 η etching were performed in two stages from the Feng Lifan line contact window to form a bit line contact window. It is provided for a substrate with a plurality of transistors. A gate and a doped region constituting a drain and a source. Forming a 乂 乂 layer = the surface of the above substrate and filling the plurality of MOS transistor dielectrics; a dielectric layer is formed on the first dielectric layer to form -Layer ^ A in m ^ = on the second dielectric layer and define the A desired doped region between the gates and a portion of the gate surface adjacent to the doped region, the sub-layers are removed to form a bit line contact window region:] a layer. A protective layer is formed on the second dielectric layer and; = And electrode, first; I electrical layer. Ion-doped second dielectric layer and protective layer on gate: Sub-remove the protective layer that is not ion-doped. Remove the contact window between the gates to form a bit 70 line. The first dielectric layer on the surface of the doped region forms a bit contact window. Finally, a conductive layer is filled in the bit line contact bit line contact plug. Μ [Embodiment]

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Please refer to FIGS. 2A to 2F, which are a series of cross-sectional views, showing the method of forming a bit line contact window in the preferred embodiment of the present invention. Please refer to FIG. 2A. First, a substrate 100, such as a substrate of single crystal silicon, is provided. The substrate 100 has a transistor structure, and the active surface of the substrate 100 has a dopant and a source dopant. Miscellaneous regions 丨 丨 〇; gates protruding from the surface of the substrate 100 between the doped regions 1 i 〇 2 〇a ~ i2〇b, the gate system is a _ bit line, and usually has a multilayer structure according to various needs For example, in the gates 120a to 120b of FIG. 28, a gate dielectric layer 1 2 1 is arranged in order from the surface of the substrate 100 upward, such as an oxide layer and a polycrystalline spar layer 1 as a conductive layer. 2 2. A metal silicide layer as a conductive layer 丨 2 3 is, for example, a silicide crane layer to reduce the contact resistance between the metal layer and each pole of the M 0 S element, and a hard mask layer 1 2 4 is, for example, nitride ; Ε evening layer. The structure composed of the above-mentioned polycrystalline stone layer and metallic stone material layer is also called polycide metal. On the side walls of the gates 120a to 120b, there are gate spacers 125 formed of, for example, silicon nitride. The above-mentioned gate structure is only one example of a conventional gate structure, which is not related to the features of the present invention, and is not a basis for limiting the scope of the present invention. Afterwards, a first dielectric layer 126, such as boro-phosphosilicate glass (BPSG), is deposited by plasma enhanced chemical vapor deposition (PECVD) to a thickness of about 5000-800 angstroms. ) To form a layer of oxidized stone (hereinafter referred to as BPSG) to fill the plurality of MOS transistors, and ^ deposit a thickness of about 3,000 to 9500 by electropolymerization enhanced chemical vapor deposition (PECVD). 〇 Second dielectric layer 127, such as tetraethoxy stone Xiyuan, (tetracthoxysilane; TE0S) silicon oxide layer (hereinafter referred to as TE〇s)

1225686 V. Description of the invention (7) --------------------------- Two ------ ------------------ -------- On the first dielectric layer 126. This stack is used as the inner layer of the integrated circuit = electrical layer (ILD), covering the transistor. Among them, the above-mentioned BPSG has excellent hole filling ability due to its relatively low glass transition temperature (both 1 ass and rans 丨 ti ○ ^ temperature), even when the line width is reduced to about 0.11 , Still widely used by the industry. After the BPSG deposition is completed, in order to increase the flatness, the wafer with BpSG deposited is generally placed in a furnace tube at about 8500 ~ 950 ° C for a period of time to reflow, and then chemical mechanical polishing (CMp) to achieve the desired flatness. Next, as shown in FIG. 2B, a mask layer 28 is formed. For example, a photoresist layer is formed on the second dielectric layer 127 and the doping between the gates to form a bit line contact window is defined. Region and a portion of the gate surface region adjacent to the doped region, and thereafter. The second dielectric layer 127 and a portion of the first dielectric layer 126 are etched by an anisotropic etching method to form an opening 129 to expose the doped region, and the first dielectric layer 126. During the etching process, a part of the gate silicon layer 1 24 and the spacer wall 12 25 were damaged, but the polysilicon was protected from exposure. During the etching process, the silicon nitride layer 24 serves as a hard mask. The second dielectric layer 127 and the first dielectric layer 126 have an etching ratio of about 1 to 20. This completes the first stage of the bit line contact window etching process. After,, the photoresist layer 128 is removed as shown in FIG. 2C. A PECVD method is used to deposit a layer with a thickness of about ¾ = protective layer 13G. For example, an amorphous stone layer is filled with Kaichuan 9 and an ion implantation method 131 is used to implant a layer. For example, βι? 2+ doped with a concentration of 1.0E14 ~ 5.0E14 for planting concentration / 15 ~ 3〇] (67 planting energy

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The parameters are supplemented by the titration of the ion beam, such as 30 °: the angle to the protective layer 13. Due to this tilt angle j

The glycocalyx layer is not doped with BF2 +, and the rest of the protection is mixed. The purpose is to make the doped protective layer 132 have a slower etch rate for the subsequent (NH40H). The K etching solution will be removed, because: the silicon is etched to cut the amorphous to have a high quality, please see the 2D picture, using the isotropic wet etching method to ammonia the first dielectric layer on the surface of 26 The un-doped protective layer 13 ^ leaves the BF-doped protective layer 132. The theoretical basis of this process is that for etching different semiconductor materials with ammonia, the etch rate is the fastest, polycrystalline silicon is the second, amorphous silicon is the slowest, and doped: is slower. Therefore, using this effect, a part of the protective layer (amorphous silicon layer j is doped with a slower etch rate. In contrast, the un-doped protective layer has an etch rate of water on the stomach and is etched first, exposing the bits to be formed. The line contacts the surface of the H-dielectric layer 126. Subsequently, as shown in FIG. 2E, the second-stage bit line is connected to the window and engraved. The same etching method as in the first stage is used to protect it from doping. 3 2 and the nitrided stone layer 1 2 4 are masks. The doped protective layer 1 3 / has a higher etching selection ratio (higher than 1 to 25, and the best value can reach 1 to θ 3〇). — The dielectric layer is completely etched and removed to expose the surface of the doped region of the silicon substrate. So far, the second stage of the bit line contact window etching process is completed, and the bit line contact window is jealous. / Finally ' As shown in FIG. 2F, a conductive layer 1 3 3 is formed by a low-pressure chemical vapor deposition method, such as a tungsten metal layer to fill the bit line contact window, thereby forming a bit line contact window plug.

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The present invention is quite novel. By implementing the present invention, a two-stage bit and a doped protective layer can be used to thicken the spacer and the word line-bit line. Second, because the doped protective layer has a first dielectric layer in the second step of the bit line contact window etching step to form a bit line-bit 1 ine ope, although the present invention has been The preferred embodiments limit the present invention. Anyone skilled in the art and the scope can make some changes and scopes. When viewing the attached patent scope, the width of the hard cover curtain layer of the contact window can be improved. In the moment, the problems such as the contact window and η) are exposed as above. Without retouching, the definition of the character is the side of the shoulder, which makes the word defects more effective than the bits. And 'Ran Qi is here to stay. : Its ^, step, supplemented by metaline-bit to avoid. The advantage is the division of the D line-bit solution. Not for the spirit of the Ming

1225686 Brief description of the drawings In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the attached drawings, detailed descriptions are as follows: Section 1 A ~ 1 F The figure is a series of cross-sectional views, which show how a conventional method for manufacturing a bit line contact window can cause the above-mentioned defects such as an open bit line contact or a word line-bit line short circuit. Figures 2A to 2F are cross-sectional views of 歹 | J, showing detailed steps of a method for forming a bit line contact window in a preferred embodiment of the present invention. [Symbol description] Conventional technology ·· 10 ~ substrate; 12 ~ drain region; 14 ~ source region; 20 ~ gate; 2 1 ~ gate dielectric layer; 2 ~ compound silicon layer ; 2 3 ~ metal fragmentation layer; 2 4 ~ hard cover curtain layer; 2 5 ~ interlayer spacer; 30 ~ dielectric layer; 31, 31a ~ dielectric window; 50 ~ conductive layer; 60 ~ photoresist layer (Cover layer);

0548-A50014TWf (Nl); 92103, 92126; yyhsu.ptd Page 15 1225686 Simple illustration of the diagram 6 0 a ~ patterned resist layer opening technology of the present invention is good: 100 110 120a 121 ~ 122 123 124 125 126 127 128 129 130 131 132 133 substrate; doped region (non-electrode region) 1 2Ob ~ gate; gate dielectric layer; polycrystalline silicon layer; metal silicide layer; hard cover curtain layer; gate dielectric first dielectric Layer, second dielectric layer, photoresist layer (mask layer), opening of the dielectric window, protective layer, ion implantation, conductive layer of doped protective layer.

0548-A50014TWf (Nl); 92103, 92126; yyhsu.ptd page 16

Claims (1)

A method for forming a bit line contact window, including 12 sub-months; ^ said Φ ~ dfe ~ 4 ^ Li Fanchu provides a semiconductor substrate including a plurality of adjacent steps: and the transistor includes a gate And forming the drain and source transistors to form a first dielectric layer on the upper surface of the substrate; the dielectric layer is filled between the plurality of MOS transistors; The second dielectric layer exposes the doped region through an opening of the first etch and the second dielectric layer. The electrical layer is formed on the first dielectric layer; the first dielectric layer f above forms an amorphous silicon layer on the first dielectric layer. The second dielectric layer invites the first dielectric layer; /, the second dielectric layer is doped with inclined ion beam ions in the 4 openings; the amorphous silicon on the = removes the non-doped impurities A first dielectric layer on the spar layer; the doped region is based on the doped amorphous silicon layer, and the doped 1 electrical layer is formed to form a one-bit line contact window; and Filler line contact plugs in the bit line contact window. Β is a bit that forms the bit line contact window as described in item 1 of the 7L dagger range. In the method, the gate electrode includes a gate dielectric layer, a polycrystalline silicon gate electrode, a titanium silicide layer, and a nitride layer in this order from the substrate surface. A method for forming a bit line contact window, wherein the first dielectric layer is a borophosphosilicate glass (BpsG) layer. 0548-A50014TWFl (4.4); 92103; 92126; Jessica.ptc 1225686 Amendment 4. The method of the scope of the patent application, such as the second dielectric layer 5. The method of the scope of the patent application, the amorphous silicon layer (PECVD) is formed. 'The bit line contact window described in item 1 is a tetraethoxysilane (TEOS) layer. Plasma-reinforced chemical vapor deposition method for forming a bit line contact window as described in item 1. Method. = The thickness of the amorphous stone layer in the eighth bit line contact window formed in item 5 of the patent scope is controlled to 1 000 ~ 2 00 Angstrom & The above-mentioned formation of the bit line contact window> Q is that the ion doping impurity is formed by a BF2 ion (BF2 +) implantation method. • The method for forming a bit line contact window as described in item 7 of the M patent scope, wherein the angle of the ion beam called ion implantation is inclined by 30 to Γ0 degrees. 9) The method for forming a bit line contact window as described in item i of Shengu's patent scope, wherein the #etch removal of the non-ion-doped amorphous stone layer is performed by an isotropic wet-etch method. 1) A method for forming a bit line contact window, including the following steps: providing a substrate including a plurality of adjacent MOS transistors, and the transistor including a gate and a drain and a source; A doped region; forming a first; an electrical layer on the surface of the substrate and filling the interstitial crystal; a second dielectric layer is formed on the first dielectric layer; an opening is etched to expose the doped region A first dielectric layer; compliantly forming a protective layer on the second dielectric layer and the first dielectric layer in the opening; 0548-A50014TWFl (4.4); 92103; 92126; Jessica.ptc page 18 1225686 _Case No. 92134532_Year Month__ VI. Application for patent scope 1 8. The method for forming a bit line contact window as described in item 10 of the scope of patent application, wherein the ion doping is based on BF2 ions (BF2 +) Implant formation. 19. The method for forming a bit line contact window as described in item 18 of the scope of the patent application, wherein the ion beam angle of the BF2 ion implantation is inclined by 30 to 40 degrees. 20. The method for forming a bit line contact window as described in item 10 of the scope of the patent application, wherein the removal of the non-ion-doped protective layer is performed by an isotropic wet lasting method. 0548-A50014TWFl (4.4); 92103; 92126; Jessica.ptc page 20