KR100955263B1 - Fabricating method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device in which the storage node electrode of the capacitor and the metal wiring contact plug are simultaneously formed without the addition of a mask step, thereby reducing the difficulty of etching the metal wiring contact hole and the gapfill process due to the height of the capacitor. According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a cell region and a peripheral circuit region, wherein a bit line and a first interlayer insulating layer covering the bit line and a storage node contact plug penetrating the interlayer insulating layer are formed on a substrate. Making; Forming a capacitor oxide film on the first interlayer insulating film; Etching the capacitor oxide layer using a mask to simultaneously form a capacitor hole exposing the storage node contact plug formed in a cell region and a metal contact hole exposing the bit line formed in a peripheral circuit region; Depositing a barrier metal and tungsten on the entire structure to simultaneously form a storage node filling the capacitor hole and a metal contact plug filling the metal contact hole; Planarizing the surface until the tungsten mask is exposed; And forming an oxide film and a cell open mask on the entire structure.

Storage Node, Metal Contact Plug, Aspect Ratio, Gap Fill

Description

Manufacturing Method of Semiconductor Device {FABRICATING METHOD OF SEMICONDUCTOR DEVICE}             

1A to 1F are cross-sectional views illustrating a prior art of manufacturing a storage node electrode and a metal contact plug of a capacitor;

2A through 2F are cross-sectional views illustrating a process of manufacturing a storage node electrode and a metal contact plug of a capacitor according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

30: substrate

31: bit line

32: hard mask

34: first interlayer insulating film

35: plug poly (storage node contact plug)

36: etch stop nitride film

37: PSG membrane

38: PE-TEOS membrane                 

39: Tungsten Hard Mask

40: photosensitive film

41: tungsten

42: oxide film

43: Cell Open Mask

The present invention relates to a method of fabricating a semiconductor device which reduces the difficulty of etching the metallization contact hole and gap fill process by increasing the height of the capacitor by simultaneously forming the storage node electrode of the capacitor and the metal (metallization) contact plug without adding a mask step. will be.

Among the semiconductor devices, in particular, as the degree of integration increases, the area of memory cells for storing one bit, which is a basic unit of memory information, is gradually reduced.

This is because with the development of the semiconductor industry, the size of the pattern applied to the production of products continues to decrease in order to increase the number of chips that can be produced per wafer.

In the case of DRAM devices, such a trend is most obvious, and the charge capacity required per cell is unchanged, but a higher required capacitance is required for the purpose of attenuating transistor characteristics deterioration due to a reduction in pattern size.

However, the area of the capacitor cannot be continuously reduced in proportion to the shrinking of the memory cells, because a certain charging capacity per unit cell is required to prevent soft errors and maintain stable operation.

Therefore, research is required to maintain the capacity of the capacitor in a limited cell area above an appropriate value, which has been generally divided into three methods.

That is, reduction in the thickness of the dielectric, increase in the effective area of the capacitor, use of a material having a high dielectric constant, and the like have been considered.

The method of increasing the effective area of the capacitor is as follows. The capacitance of the capacitor can be increased by widening the area between the two electrodes. As mentioned earlier, the planar area of the chip is inevitably reduced to reduce the chip size, so that the height in the vertical direction is inevitably increased. Is increased.

However, an increase in device height causes an increase in the metal contact height formed in the peripheral circuit region. As the height of the metal contact is increased in this way, the aspect ratio of the contact hole is increased, which leads to the difficulty of the open process of the contact hole and the gap fill process of filling the deep contact hole.

Hereinafter, a semiconductor device manufacturing method according to the related art will be described with reference to FIGS. 1A to 1F.

First, as illustrated in FIG. 1A, a bit line 11 and a bit line hard mask 12 are stacked and patterned on a semiconductor substrate 10 having a cell region and a peripheral circuit region. 1A shows a bit line 11 formed in a cell region and a peripheral circuit region.

Here, the semiconductor substrate 10 is a substrate on which a word line, a landing plug contact, and other series of elements are formed.

Subsequently, a first interlayer insulating layer 13 is formed on the semiconductor substrate 10 including the bit line 11, and then a plug polysilicon 14 penetrating the first interlayer insulating layer 13 is formed. .

The plug polysilicon 14 is also referred to as a storage node contact plug, hereinafter referred to as plug polysilicon. At this time, the substrate connecting with the plug polysilicon 14 is typically a landing plug contact.

Next, as illustrated in FIG. 1B, a nitride film 15 is deposited on the first interlayer insulating film 13 including the plug polysilicon 14. In this case, the nitride layer 15 is used as an etch stop layer during subsequent capacitor oxide layer etching and an attack prevention layer during wet etching.

Next, a capacitor oxide film is formed on the nitride film 15. Phospho Silicate Glass (PSG) film, Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS) film, Undoped Silicated Glass (USG) film, Boro Phospho Silicate Glass (BPSG) film, etc. may be used as the capacitor oxide film. It is also possible to use a structure in which oxide films are stacked.

Referring to FIG. 1B, it can be seen that a structure in which the first oxide film 16 and the second oxide film 17 are stacked is used as the capacitor oxide film.

Next, a storage node mask 18 for patterning the capacitor oxide films 16 and 17 and the nitride film 15 is formed on the capacitor oxide film. As the storage node mask 18, polysilicon is typically used.

Thereafter, the capacitor oxide layers 16 and 17 and the nitride layer 15 of the cell region are etched using the storage node mask 18 to form a capacitor hole exposing the plug polysilicon 14.

In this case, it can be seen that the storage node mask 18 is only patterned in the cell region. After the formation of the capacitor hole, the storage node mask 18 is removed.

Next, as shown in FIG. 1C, the electrode hole to be used as the storage node 19 is coated on the entire structure including the capacitor hole to fill the capacitor hole. Here, as the storage node, polysilicon or tungsten is generally used.

Next, as shown in FIG. 1D, the surface shown in FIG. 1D is completed by applying a chemical mechanical polishing (CMP) process or an etch back process to planarize the surface. .

 Next, as shown in FIG. 1E, a cell open mask 20 for opening only a cell region is formed, and the first oxide layer 17, the second oxide layer 16, and the nitride layer 15 formed in the cell region are formed using the cell open mask 20. Proceed to the etching process to remove

As a result, the storage node 19 is exposed in the cell region, and in the subsequent process, the dielectric 21 and the upper electrode 22 contacting the storage node are formed to form a capacitor.

In this case, as the height of the storage node electrode 19 increases, the effective area of contact with the dielectric 21 increases, so that the capacitance can be increased as described above.

Next, as shown in FIG. 1F, after forming the second interlayer insulating film 23 covering all of the capacitor structures, a metal contact forming process for electrically connecting the metal wiring and the bit line of the peripheral circuit region is performed.

That is, as shown in FIG. 1F, the second interlayer insulating layer 23 is partially etched to form a metal contact hole exposing the bit line hard mask 12 formed in the peripheral circuit region, and then the bit line hard mask. (12) is also etched to expose the bit lines 11 formed in the peripheral circuit area.

Subsequently, the metal contact plug 24 filling the metal contact hole is formed, and then the metal wiring 25 is formed.

In this case, the higher the height of the storage node, the greater the depth of the metal contact hole. Therefore, there is a problem that the etching process of forming such a deep metal contact hole is difficult, and also the process of filling the metal contact hole having a high aspect ratio with a conductive material is insufficient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a method of manufacturing a semiconductor device that is stable and easy to fabricate by simultaneously forming a storage node electrode and a metal contact plug without increasing a mask step.

In accordance with an aspect of the present invention, there is provided a semiconductor device including a cell region and a peripheral circuit region. Forming a storage node contact plug; Forming a capacitor oxide film on the first interlayer insulating film; Etching the capacitor oxide layer using a mask to simultaneously form a capacitor hole exposing the storage node contact plug formed in a cell region and a metal contact hole exposing the bit line formed in a peripheral circuit region; Depositing a barrier metal and tungsten on the entire structure to simultaneously form a storage node filling the capacitor hole and a metal contact plug filling the metal contact hole; Planarizing the surface until the tungsten mask is exposed; And forming an oxide film and a cell open mask on the entire structure.

The present invention facilitates the subsequent process by simultaneously forming the storage node electrode and the metal contact plug without increasing the mask step.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.                     

2A through 2F illustrate a semiconductor device manufacturing process according to an exemplary embodiment of the present invention, with reference to the drawings. FIG.

First, the process of forming a nitride film, which is a word line, a landing plug contact, a bit line, a plug polysilicon, a capacitor oxide film, and an etch stop film, on a semiconductor substrate is the same as in the prior art. same.

First, as shown in FIG. 2A, the bit line 31 and the bit line hard mask 32 are stacked and formed on the semiconductor substrate 30. 2A shows bit lines formed in the cell region and the peripheral circuit region.

The semiconductor substrate 30 is a substrate on which word lines, landing plug contacts, and other series of devices are formed.

Subsequently, the first interlayer insulating layer 34 is formed on the semiconductor substrate 30 including the bit lines 31, and then the plug polysilicon 35 penetrating the first interlayer insulating layer 34 is formed in the cell region. To form. At this time, the plug polysilicon 35 is typically connected with the landing plug contact.

Next, a nitride film 36 is deposited on the first interlayer insulating film 34 including the plug polysilicon 35. In this case, the nitride layer 36 is used as an etch stop layer during subsequent capacitor oxide layer etching and an attack prevention layer during wet etching.

Next, a capacitor oxide film is formed on the nitride film 36. Phospho Silicate Glass (PSG) film, Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS) film, Undoped Silicated Glass (USG) film, Boro Phospho Silicate Glass (BPSG) film, etc. may be used as the capacitor oxide film, or as described above. It is also possible to use a structure in which oxide films are stacked.

Referring to FIG. 2A, it can be seen that a structure in which the PSG film 37 and the PE-TEOS film 38 are stacked is used as a capacitor oxide film.

Next, a storage node mask 39 for patterning the capacitor oxide films 37 and 38 and the nitride film 36 is formed on the capacitor oxide film.

Tungsten was used as the storage node mask 39 used in the embodiment of the present invention. In the prior art, polysilicon was mainly used as a storage node mask, but in one embodiment of the present invention, tungsten was used as the storage node mask 39.

This is to form the storage node electrode of the cell region and the metal contact plug of the peripheral circuit region at the same time, and also to more stably adjust the CD (Critical Dimension) and profile of the capacitor hole, which is more robust than conventional polysilicon. Is used as the storage node mask.

Subsequently, after the photoresist layer 40 is formed on the tungsten storage node mask 39, the photoresist layer 40 is patterned through an exposure / etch process.

In this case, the photoresist layer 40 is patterned to form a storage node electrode in a cell region and a metal contact plug in a peripheral circuit region.

Next, as illustrated in FIG. 2B, the tungsten storage node mask 39 is patterned by using a photoresist film (not shown) as an etching mask.

Comparing the storage node mask according to an embodiment of the present invention and the storage node mask according to the prior art is as follows.

First, it can be seen that the storage node mask 39 according to an embodiment of the present invention uses tungsten and is patterned in the peripheral circuit region as well as the cell region to form the metal contact plug.

In contrast, polysilicon was used as the storage node mask 18 according to the related art, and was patterned only in the cell region to form the storage node.

In the present invention, by using tungsten as the storage node electrode, since the work function difference is larger than that of the conventional polysilicon storage node electrode in relation to the dielectric, the effective thickness can be lowered and high capacitance can be obtained. There is an advantage.

As such, after the tungsten storage node mask 39 is patterned, a process of etching the PSG film 37, the PE-TEOS film 38, and the nitride film 36 formed in the cell region and the peripheral circuit region using the same is performed. do.

Through the etching process, a capacitor hole through which the plug polysilicon 35 is exposed is formed in the cell region, and in the peripheral circuit region, the PSG film 37, the PE-TEOS film 38, the nitride film 36, and the bit line hard mask are formed. The 32 is etched to form a metal contact hole through which the bit line 31 is exposed. This is shown in Figure 2c.

Next, as shown in FIG. 2D, a barrier metal (not shown) and tungsten 41 are deposited on the entire structure to fill the storage node contact hole in the cell region and the metal contact hole in the peripheral circuit region.                     

That is, in one embodiment of the present invention, the storage node electrode is formed in the cell region and the metal contact plug is simultaneously formed in the peripheral circuit region. Therefore, since the metal contact plugs formed in the subsequent metal contact forming process are used as they are, it is possible to manufacture a stable device by minimizing the difficulty of forming a contact hole and the burden of a gapfill process due to the vertical height increase of the device.

After depositing the barrier metal and tungsten on the whole structure in this manner, the surface is planarized by applying chemical mechanical polishing or etchbeck process, and then an oxide film 42 is formed on the whole structure as shown in FIG. 2E.

Next, as shown in FIG. 2F, a cell open mask 43 for opening only the cell region is formed, and the PE-TEOS film 38, the PSG film 37, and the nitride film 36 formed in the cell region are formed using the cell open mask 43. Is removed to expose the tungsten storage node 41.

After that, the dielectric and the upper electrode are formed to complete the capacitor structure. Next, a metal contact forming process for connecting the bit line and the metal wiring of the peripheral circuit area is performed. In an embodiment of the present invention, since the metal contact plug is formed in advance, the margin of the subsequent gap fill process may be improved. As described above.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

Application of the present invention, in spite of an increase in the topology of the device, which is an inevitable result of the refinement of design rules, enables stable metal contact formation, thereby increasing the stability and reliability of device fabrication.

Claims (2)

In the method of manufacturing a semiconductor device comprising a cell region and a peripheral circuit region, Forming a bit line, a first interlayer insulating layer covering the bit line, and a storage node contact plug passing through the interlayer insulating layer on a substrate; Forming a capacitor oxide film on the first interlayer insulating film; Etching the capacitor oxide layer using a mask to simultaneously form a capacitor hole exposing the storage node contact plug formed in a cell region and a metal contact hole exposing the bit line formed in a peripheral circuit region; Depositing a barrier metal and tungsten on the entire structure to simultaneously form a storage node filling the capacitor hole and a metal contact plug filling the metal contact hole; Planarizing the surface until the tungsten mask is exposed; And Forming an oxide film and a cell open mask on the entire structure Method of manufacturing a semiconductor device comprising a. The method of claim 1, The mask is a manufacturing method of a semiconductor device, characterized in that the tungsten.

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