JP3482272B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a high-performance and highly reliable wiring layer.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, high integration and fine processing have been promoted, and accordingly, the wiring structure has become fine, and an excellent wiring structure has been demanded.

In recent years, an ASIC which is a semiconductor integrated circuit device corresponding to each function or circuit required by a user.
In (Application Specific Integrated Circuit), a variety of products are available in small quantities in response to various demands of users, and therefore, there is a demand for easy design and flexible manufacturing process.

Therefore, in order to simplify the design of the ASIC and to make the manufacturing process flexible, there is provided a structure in which an annular input / output main line that surrounds the chip of the semiconductor integrated circuit device is arranged and an input / output cell is provided in the outer sphere. Conceivable.

The ASIC having the wiring of the above structure is
The input / output terminal of the internal logic circuit cell in the chip of the semiconductor integrated circuit device is connected to an annular input / output trunk line that circulates around the chip, and the input / output cell is electrically connected to the input / output trunk line to meet the user's request. The input / output terminals of various internal logic circuit cells cannot be directly connected to the input / output cells, but can be electrically connected as much as possible by using the input / output trunk line.

As a document describing the wiring structure in a semiconductor integrated circuit device having a logic block, there is, for example, the one described in Japanese Patent Application Laid-Open No. 54-20680.

[0007]

However, the present inventor has found that the above-described semiconductor integrated circuit device has various problems as described below.

That is, the input / output wiring of the input / output cell and the internal logic circuit cell in the semiconductor integrated circuit device such as an ASIC uses the upper wiring layer as the in-chip wiring, so that the lowermost one layer of the wiring layer is formed. Since only the wiring layer is used, if the layout of the I / O terminals in the I / O cells and the I / O terminals in the internal logic circuit cells conflicts, one of the I / O terminals and the ring-shaped I / O trunk line You have to sacrifice the connection.

Therefore, even if the ring-shaped input / output trunk line is used, the input / output terminal of the internal logic circuit cell cannot be completely electrically connected to the input / output terminal of the input / output cell. Above, various problems occur.

Specifically, an abnormal power supply state occurs at the input / output terminal of the internal logic circuit cell, which causes electromigration and a reduction in noise margin. Therefore, high speed operation cannot be performed. There is a problem that the performance and reliability of the wiring layer are reduced.

An object of the present invention is to provide a semiconductor integrated circuit device having a wiring layer of high performance and high reliability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

The typical ones of the inventions disclosed in the present invention will be outlined below.

In the semiconductor integrated circuit device of the present invention, a circuit cell region in which a plurality of circuit cells are arranged in the central portion of the chip, and an input / output trunk line made up of an input trunk line and an output trunk line are provided around the circuit cell region. The input / output main line area and the input / output cell area in which a plurality of input / output cells are arranged outside the input / output main line, and the input / output which is electrically connected to the input / output terminal in the circuit cell by the wiring layer. The input / output terminals of the input / output cells are electrically connected to the area different from the area of the main line by the wiring layer , and the input / output main line is the second layer.
It is provided in the wiring layer, and the input / output trunk line and the circuit
The wiring layer to which the input / output terminals of the module are electrically connected is 1
It is provided in the wiring layer of the second layer, and the input / output trunk line and the
Input / output terminals of input / output cells are electrically connected.
Line layer Ru der those provided in the first layer or the third wiring layer.

[0015]

According to the above-described semiconductor integrated circuit device of the present invention, the input / output terminals of the input / output cells are arranged in the first and third layers.
Prepare in the wiring layer and input / output terminals in the input / output cell
The electrical connection between the input and output mains on the first or third layer
Select one of the layers so that it can be electrically connected.
By providing a reason, I / O trunk lines and internal logic circuits
The first layer layout that electrically connects the input / output terminals of the cell
Select a wiring layer that does not conflict with the line layer and input / output to the input / output trunk line
Since the input / output terminals in the cell can be electrically connected, input / output
The first wiring layer from the main line to the input / output terminals of the circuit cell
In order to make a reliable electrical connection using
Efficiently input / output power from a power cell to internal logic circuit cells
It can be supplied via the main line.

Further , in another semiconductor integrated circuit device of the present invention,
According to this, the input / output terminals in the input / output cell are the first layer and the third layer.
Prepare in the eye wiring layer and input / output in the input / output cell
Make the electrical connection between the terminal and the input / output trunk line on the first layer or the third layer.
Select to be able to make electrical connection by selecting either of the wiring layers
I / O cell chips, even with the freedom of
The placement area in is compared with the placement area of the internal logic circuit cell
And regular, the two wiring layers of the first and third layers
Even if an I / O terminal is provided on the
There is almost no effect, facilitating design and manufacturing process
Flexible and high performance wiring structure with high reliability
You can

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

FIG. 1 is a schematic plan view showing a chip 1 of a semiconductor integrated circuit device which is an embodiment of the present invention. Figure 2
[Fig. 2] is a schematic plan view showing a partial region 1a in Fig. 1 in an enlarged manner. FIG. 3 is a schematic plan view showing the first wiring layer in the region 1a shown in FIG. FIG. 4 is a schematic plan view showing the second wiring layer in the region 1a shown in FIG. FIG. 5 is a schematic plan view showing the third wiring layer in the region 1a shown in FIG. In addition, in FIGS. 1 to 5, the lines showing the respective regions are shown as solid lines when viewed from the top for simplification of the drawings.

The semiconductor integrated circuit device of the present invention will be described in detail with reference to FIGS.

First, as shown in FIG. 1, the semiconductor integrated circuit device of this embodiment is, for example, a gate array.
ASIC, etc., and a CMOS in the center of the chip 1.
It has an internal logic circuit cell region 2 in which a large number of internal logic circuit cells made of semiconductor elements having a (Complementary Metal Oxide Semiconductor) structure are provided.

Further, the semiconductor integrated circuit device of this embodiment is
An annular input / output main line 3 is provided around the internal logic circuit cell region 2 in which a large number of internal logic circuit cells are provided, and the input / output main line 3 is, for example, 5V power supply voltage (VDD).
For example, and an output main line 3b for a reference voltage (Vss) which is, for example, 0V (ground potential).

The semiconductor integrated circuit device of this embodiment is
An input / output cell region 4 having a large number of input / output cells is provided in a region outside the input / output main line 3.

As shown in FIGS. 2 to 5, each internal logic circuit cell in the internal logic circuit cell region 2 is arranged as a plurality of columns arranged in an orderly manner, for example, internal logic circuit cells 5 to 10. The input / output terminals in the adjacent internal logic circuit cells in the same column are electrically connected using the wiring layer. The wiring layer of each internal logic circuit cell in the internal logic circuit cell region 2 is formed by using the first wiring layer as the internal logic circuit cells 5 to 10, for example. The second or more wiring layers in the internal logic circuit cell area 2 can be used for electrical connection of signal wiring layers or mutual wiring layers.

More specifically, the internal logic circuit cell 6
The through hole 6c corresponding to the input terminal for the power supply voltage (VDD), which is, for example, 5V, is the through hole 9a corresponding to the input terminal of the adjacent internal logic circuit cell 9 in the same column.
Is electrically connected to the first wiring layer 6e. Further, the through hole 6d corresponding to the output terminal for the reference voltage (Vss) which is, for example, 0 V in the internal logic circuit cell 6
Are electrically connected to the through holes 9b corresponding to the input terminals of the adjacent internal logic circuit cells 9 in the same column by the first wiring layer 6f.

Further, the through hole 7c corresponding to the input terminal for the power supply voltage (VDD) of 5V in the internal logic circuit cell 7 has the adjacent internal logic circuit cell 1 in the same column.
The through hole 10a corresponding to the 0 input terminal is electrically connected to the first wiring layer 7e. In addition, the reference voltage (Vss) which is 0 V, for example, in the internal logic circuit cell 7
The through hole 7d corresponding to the output terminal for is electrically connected to the through hole 10b corresponding to the input terminal of the adjacent internal logic circuit cell 10 in the same column by the first wiring layer 7f.

On the other hand, the internal logic circuit cells arranged at the ends of the internal logic circuit cells of each column in the internal logic circuit cell region 2 are arranged in the second wiring layer like the internal logic circuit cell 6, for example. It is electrically connected to the input / output main line 3. The wiring layer of each internal logic circuit cell in the internal logic circuit cell region 2 is formed by using the wiring layer of the first layer like the internal logic circuit cells 5 to 10, and the wiring of the second layer. It is electrically connected to the input / output trunk line 3 which is a layer through a through hole provided in the interlayer insulating film between the first wiring layer and the second wiring layer.

More specifically, the internal logic circuit cell 6
The through hole 6a corresponding to the input terminal for the power supply voltage (VDD), which is, for example, 5V, is the through hole 3c corresponding to the input terminal of the input main line 3a in the input / output main line 3 of the second layer and the wiring layer of the first layer. It is electrically connected by 6g. Further, the through hole 6b corresponding to the output terminal for the reference voltage (Vss) which is 0V, for example, in the internal logic circuit cell 6 is the output trunk line 3b in the input / output trunk line 3 of the second layer.
Are electrically connected to the through hole 3d corresponding to the output terminal of the first wiring layer 6h.

The through hole 7a corresponding to the input terminal for the power supply voltage (VDD), which is 5V, for example, in the internal logic circuit cell 7 corresponds to the input terminal of the input trunk line 3a in the input / output trunk line 3 of the second layer. The through holes 3e are electrically connected to the first wiring layer 7g. Further, the reference voltage (V
The through hole 7b corresponding to the output terminal for ss) is electrically connected to the through hole 3f corresponding to the output terminal of the output main line 3b in the input / output main line 3 of the second layer by the wiring layer 7h of the first layer.

On the other hand, a plurality of input / output cells in the input / output cell region 4 are arranged in order in the region outside the input / output main line 3 in the peripheral portion of the chip 1 like the input / output cells 11 and 12, for example. The input / output terminals of each input / output cell are electrically connected to the input / output main line 3. The input / output terminals of each input / output cell in the input / output cell region 4 are provided in the regions of the first wiring layer and the third wiring layer, such as the input / output cells 11 and 12, for example. In the input / output trunk line 3 which is the second wiring layer, the interlayer insulating film between the first wiring layer and the second wiring layer or the second wiring layer and the third wiring layer. The layers are electrically connected to each other through through holes provided in the interlayer insulating film.

FIG. 6 is a schematic perspective view showing the structure of the wiring layer provided on the input / output cell 11. The input / output terminals of the input / output cell 11 are provided in the regions of the first wiring layer 13 and the third wiring layer 14, and the wiring layout specifications are changed as necessary to change the wiring layout specifications of the first layer. Wiring layer 13
Alternatively, one of the third wiring layers 14 can be selected and electrically connected to the input / output trunk line 3 which is the second wiring layer. In FIG. 6, reference numeral 15 is an insulating film such as an interlayer insulating film, and 16 is a wire bonding pad electrode electrically connected to the input / output cell 11.

That is, the input / output terminal in each input / output cell is provided in the region of the first wiring layer and the third wiring layer, and the first wiring layer or the third wiring layer is formed. It has a structure that can be freely selected as needed. More specifically, the input terminal of each input / output cell has a structure that can be electrically connected to the input main line 3a of the second input / output main line 3 by using the first wiring layer or the third wiring layer. There is. The output terminal of each input / output cell has a structure that can be electrically connected to the output trunk line 3b of the second-layer input / output trunk line 3 by using the first wiring layer or the third wiring layer.

More specifically, the through hole 11a corresponding to the input terminal for the power supply voltage (VDD), which is, for example, 5V, in the input / output cell 11 is the input / output trunk line 3 of the second layer.
Are electrically connected to the through hole 3g corresponding to the input terminal of the input main line 3a in the first wiring layer 11c. Further, the through hole 1 corresponding to the output terminal for the reference voltage (Vss) which is 0V in the input / output cell 11 is used.
1b is electrically connected to the through hole 3h corresponding to the output terminal of the output main line 3b in the input / output main line 3 of the second layer and the wiring layer 11d of the third layer.

In this case, the through hole 11a corresponding to the input terminal in the input / output cell 11 and the through hole 3g corresponding to the input terminal of the input trunk line 3a in the input / output trunk line 3 in the second layer are provided in the first wiring layer 11c. The input terminals in the internal logic circuit cells are not electrically connected to the input main line 3a in the area of the through hole 3g in the input main line 3a by the first wiring layer. This is because the wiring layers are not in competition with each other.

On the other hand, the through hole 11b corresponding to the output terminal of the input / output cell 11 and the through hole 3h corresponding to the input terminal of the output trunk line 3b of the input / output trunk line 3 of the second layer are formed by the wiring layer 11d of the third layer. The reason for electrical connection is as follows.

That is, since the input terminal in the internal logic circuit cell 6 is electrically connected to the input main line 3a by the first wiring layer 6g, the through hole 11b corresponding to the output terminal in the input / output cell 11 and the second layer are provided. When attempting to electrically connect the output main line 3b in the first input / output main line 3 with the first wiring layer, the first wiring layers compete with each other, thereby sacrificing one of the wiring layers. There will be restrictions.

Therefore, since there is no choice when electrically connecting the input main line 3a and the input terminal in the internal logic circuit cell 6 by the wiring layer, the wiring layer uses the first wiring layer 6g. Through hole 11b corresponding to the output terminal in the input / output cell 11 that can be freely selected and selected
And the through hole 3h corresponding to the input terminal of the output main line 3b in the input / output main line 3 of the second layer, the wiring layer 11 of the third layer.
By electrically connecting by d, a method is adopted in which the above-mentioned competition is eliminated and neither wiring layer is sacrificed, and an excellent wiring layer having a predetermined condition without any constraint condition is provided.

Further, for example, 5 V in the input / output cell 12
The through hole 12a corresponding to the input terminal for the power supply voltage (VDD) is a through hole 3i corresponding to the input terminal of the input main line 3a in the input / output main line 3 of the second layer and the wiring layer 12c of the first layer. It is connected.

In this case, the through hole 12a corresponding to the input terminal in the input / output cell 12 and the through hole 3i corresponding to the input terminal of the input trunk line 3a in the input / output trunk line 3 in the second layer are provided in the first wiring layer 12c. The input / output terminals in the internal logic circuit cells are not electrically connected to the input trunk line 3a by the first wiring layer in the area of the through hole 3i in the input trunk line 3a. This is because the eye wiring layers do not compete with each other.

Further, for example, 0 V in the input / output cell 12
The through hole 12b corresponding to the output terminal for the reference voltage (Vss) is a through hole 3j corresponding to the output terminal of the output main line 3b in the input / output main line 3 of the second layer and the wiring layer 12d of the first layer. It is connected.

In this case, the through hole 12b corresponding to the output terminal of the input / output cell 12 and the through hole 3j corresponding to the output terminal of the output trunk line 3b in the input / output trunk line 3 of the second layer are provided in the wiring layer 12d of the first layer. Are electrically connected to each other in the area of the through hole 3j in the output trunk line 3b because the input / output terminals in the internal logic circuit cells are not electrically connected to the output trunk line 3b by the first wiring layer. This is because the eye wiring layers do not compete with each other.

In the semiconductor integrated circuit device of this embodiment, an input / output main line composed of an input main line and an output main line is provided around a circuit cell region in which a plurality of circuit cells are arranged in the central portion of the chip and around the circuit cell region. Has an input / output main line area in which a plurality of input / output cells are arranged, and an input / output cell area in which a plurality of input / output cells are arranged outside the input / output main line. The input / output terminals of the input / output cells are electrically connected to the area different from the area of the output trunk line by the wiring layer.

The input / output trunk line is provided in the second wiring layer, and the wiring layer to which the input / output trunk line and the input / output terminals of the circuit cells are electrically connected is provided in the first wiring layer. The wiring layer in which the input / output trunk line and the input / output terminal of the input / output cell are electrically connected is provided in the first or third wiring layer.

Further, the input / output trunk line is provided in the second wiring layer, and the input / output terminals in the input / output cells are provided in both the first and third wiring layers. The wiring layer to which the input and output terminals of the input and output cells are electrically connected is selected as necessary and provided in the first or third wiring layer.

Next, a method of manufacturing the semiconductor integrated circuit device of this embodiment will be described.

First, a CMOSFET forming an internal logic circuit cell and an input / output cell is formed by a wafer processing step using a semiconductor substrate made of, for example, p-type silicon single crystal as a starting material. This manufacturing process can be performed by combining various prior arts.

Next, a first wiring layer is formed on the semiconductor substrate. As the first wiring layer, for example, an aluminum layer is formed by a sputtering method. The material of the first wiring layer is titanium nitride (TiN) as the lower or upper layer of the aluminum layer as the first wiring layer in order to secure the characteristics of stress migration resistance and electromigration resistance. A wiring layer in which a wiring structure is laminated by using a refractory metal layer such as a layer can be used. As the first wiring layer, a combination of electrically conductive materials such as a polycrystalline silicon layer or a laminated layer of a polycrystalline silicon layer and a refractory silicide layer can be used.

Next, after forming a photoresist film on the surface of the first wiring layer, a first layer is formed on the photoresist film by using a photomask for the first wiring layer using a photolithography technique. After forming the pattern for the wiring layer of, using the photoresist film as an etching mask,
The first wiring layer is selectively etched by a dry etching method or a wet etching method to pattern the first wiring layer, and then the unnecessary photoresist film is removed.

The pattern of the first wiring layer of the region 1a which is a part of the chip 1 of the semiconductor integrated circuit device of this embodiment is as shown in FIG.

Next, an interlayer insulating film is formed on the entire surface so as to cover the first wiring layer. The interlayer insulating film is formed by, for example, forming a silicon oxide film by a CVD method, and then forming an SOG (Spin On Glass) film by using a spin coating device (spinner) for flattening the surface. The interlayer insulating film is formed of a PSG (Phospho Silicate Glass) film or BPS after a silicon oxide film is formed by the CVD method.
It is possible to adopt various modes such as an interlayer insulating film having a laminated structure in which a G (Boro Phospho Silicate Glass) film or the like is formed by a CVD method.

Next, after forming a photoresist film on the surface of the interlayer insulating film, a through hole pattern is formed in the photoresist film by using a photo mask for the through hole by using a photolithography technique, and a photoresist is formed. After using the resist film as an etching mask, the interlayer insulating film is selectively etched by dry etching method or wet etching method to form through holes in the selective regions of the interlayer insulating film, after which it becomes unnecessary. Work to remove the photoresist film.

Next, a second wiring layer is formed on the through holes and the interlayer insulating film. The second wiring layer is formed by sputtering an aluminum layer, for example.
The second wiring layer may have various modes such as a wiring layer having a laminated structure made of the same material as the first wiring layer described above.

Next, the second wiring layer is patterned by using the photolithography technique to form the input / output trunk line (FIG. 4).

Next, an interlayer insulating film is formed on the entire surface so as to cover the second wiring layer, and then through holes are formed in selective regions by using a photolithography technique.

Next, a third wiring layer is formed on the through hole and the interlayer insulating film. The third wiring layer is formed by sputtering an aluminum layer, for example.
The third wiring layer can have various modes such as a wiring layer having a laminated structure made of the same material as the first wiring layer or the second wiring layer described above.

Next, the third wiring layer is patterned by using a photolithography technique to form a wiring layer for electrically connecting the input / output terminals of the input / output cells and the second input / output trunk line (FIG. 5). ).

The manufacturing process of the wiring layer having the three-layer structure is as follows.
Although various prior arts can be combined and omitted for simplification of description, when forming a pattern of each wiring layer, a wiring layer for interconnecting wiring layers in a circuit cell and a signal wiring layer, etc. Various wiring layers are formed.

(1) According to the semiconductor integrated circuit device of this embodiment, the input / output terminals of the input / output cells are provided in a region different from the region of the input / output main line electrically connected to the input / output terminals of the circuit cells by the wiring layer. Is electrically connected by the wiring layer, the wiring layer that electrically connects the input / output terminals of the circuit cell to the input / output trunk line is the wiring layer that electrically connects the input / output terminal of the input / output cell to the input / output trunk line. Since it can be electrically connected to the input / output trunk line without being restricted by the state of, the wiring layer that electrically connects the input / output terminal in the circuit cell to the input / output trunk line uses a wiring layer that has a predetermined condition. Can be electrically connected to the input / output mains.

Therefore, the circuit cell has a complete power supply rate, and the abnormal power supply state can be prevented, so that the occurrence of electromigration and the reduction of noise margin can be prevented. It is possible to improve the performance and reliability of the wiring layer such that it can operate.

(2) According to the semiconductor integrated circuit device of this embodiment, the input / output terminals of the input / output cells are prepared in the wiring layers of the first and third layers, and the input / output terminals of the input / output cells are provided. The input / output trunk line and the input / output in the internal logic circuit cell are provided by having the freedom of choice so that the electrical connection with the input / output trunk line can be made by selecting either the first wiring layer or the third wiring layer. Since the input / output terminals in the input / output cells can be electrically connected to the input / output trunks by selecting the wiring layer that does not conflict with the first wiring layer that electrically connects the terminals, the input / output trunks can be connected to the input / output terminals in the circuit cells. Since reliable electrical connection can be made using the first wiring layer, the power from the input / output cells can be efficiently supplied to the internal logic circuit cells via the input / output trunk lines.

(3) According to the semiconductor integrated circuit device of the present embodiment, the input / output terminals of the input / output cells are prepared in the first and third wiring layers, and the input / output terminals of the input / output cells are provided. Even if the choice is made so that the electrical connection with the input / output trunk line can be made by either the first wiring layer or the third wiring layer, the arrangement area of the input / output cell in the chip is internal. It is more regular than the layout area of the logic circuit cells, and even if the input / output terminals are provided in the two wiring layers of the first layer and the third layer, there is almost no influence on the layout restrictions. It is possible to make the design easy, the manufacturing process flexible, and the wiring structure having high performance and high reliability.

Further, since the first wiring layer is used for the electrical connection between the input / output terminal and the input / output main line in the internal logic circuit cell, the internal logic circuit cell in which a plurality of internal logic circuit cells are arranged is arranged. Since the second or more wiring layers in the region can be used for electrical connection of signal wiring layers or mutual wiring layers, the design is easy, the manufacturing process is flexible, and the wiring structure has high performance and high reliability. can do.

Although the invention made by the inventor of the present invention has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-described embodiment, the semiconductor integrated circuit device is, for example, an ASIC such as a gate array, in which a large number of internal logic circuit cells each composed of a semiconductor element having a CMOS structure are provided in the central portion of the chip 1. , A semiconductor substrate is provided with a bipolar transistor, a MOSFE
BiMO combining T and bipolar transistor
It can be applied to a semiconductor integrated circuit device having various semiconductor elements such as S or BiCMOS structure.

[0064]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, the input / output terminals of the input / output cells are provided in an area different from the area of the input / output main line electrically connected to the input / output terminals of the circuit cells by the wiring layer. By being electrically connected by the wiring layer, the wiring layer that electrically connects the input / output terminals in the circuit cell to the input / output trunk line is the wiring layer that electrically connects the input / output terminal in the input / output cell to the input / output trunk line. Since it can be electrically connected to the input / output trunk line without being restricted by the state, the wiring layer that electrically connects the input / output terminal in the circuit cell to the input / output trunk line should be a wiring layer having predetermined conditions. It can be electrically connected to the input / output mains.

Therefore, the circuit cell has a complete power supply rate, and the abnormal power supply state can be prevented, so that the occurrence of electromigration and the reduction of the noise margin can be prevented. It is possible to improve the performance and reliability of the wiring layer such that it can operate.

(2) According to the semiconductor integrated circuit device of the present invention, the input / output terminals of the input / output cells are prepared in the wiring layers of the first layer and the third layer and are connected to the input / output terminals of the input / output cells. The input / output trunk line and the input / output terminal in the internal logic circuit cell are provided by having the freedom to select the electrical connection with the output trunk line by selecting either the first wiring layer or the third wiring layer. Since it is possible to electrically connect the input / output terminal of the input / output cell to the input / output main line by selecting a wiring layer that does not conflict with the first wiring layer that electrically connects the Since the electrical connection can be surely made using the wiring layer of the layer, the power supply from the input / output cell can be efficiently supplied to the internal logic circuit cell via the input / output trunk line.

(3) According to the semiconductor integrated circuit device of the present invention, the input / output terminals of the input / output cells are prepared in the wiring layers of the first and third layers, and are connected to the input / output terminals of the input / output cells. Even if the electrical connection with the output trunk line is selected freely so that the electrical connection can be made by selecting either the first wiring layer or the third wiring layer, the arrangement area of the chip of the input / output cell is the internal logic. It is more regular than the area where the circuit cells are arranged, and even if the input / output terminals are provided in the two wiring layers of the first layer and the third layer, there is almost no influence on the layout restrictions, and the design Of the wiring structure, the manufacturing process is flexible, and the wiring structure has high performance and high reliability.

Further, since the first wiring layer is used for the electrical connection between the input / output terminal and the input / output main line in the internal logic circuit cell, the internal logic circuit cell in which a plurality of internal logic circuit cells are arranged is arranged. Since the second or more wiring layers in the region can be used for electrical connection of signal wiring layers or mutual wiring layers, the design is easy, the manufacturing process is flexible, and the wiring structure has high performance and high reliability. can do.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a chip of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a schematic plan view showing an enlarged part of a region in FIG.

3 is a schematic plan view showing a first wiring layer in a region shown in FIG.

FIG. 4 is a schematic plan view showing a second wiring layer in the area shown in FIG.

5 is a schematic plan view showing a third wiring layer in the region shown in FIG. 2. FIG.

FIG. 6 is a schematic perspective view showing a structure of a wiring layer provided on an input / output cell.

[Explanation of symbols]

1 chip Partial area of 1a chip 2 Internal logic circuit cell area 3 I / O trunk lines 3a Input main line 3b output main line 3c through hole 3d through hole 3e through hole 3f through hole 3g through hole 3h through hole 3i through hole 3j through hole 4 I / O cell area 5 Internal logic circuit cell 6 Internal logic circuit cell 6a through hole 6b through hole 6c through hole 6d through hole 6e Wiring layer 6f wiring layer 6g wiring layer 6h wiring layer 7 Internal logic circuit cell 7a through hole 7b through hole 7c through hole 7d through hole 7e Wiring layer 7f wiring layer 7g wiring layer 7h wiring layer 8 Internal logic circuit cell 9 Internal logic circuit cell 9a through hole 9b through hole 10 Internal logic circuit cell 10a through hole 10b through hole 11 I / O cells 11a through hole 11b through hole 11c wiring layer 11d wiring layer 12 I / O cells 12a through hole 12b through hole 12c wiring layer 12d wiring layer 13 First wiring layer 14 Third wiring layer 15 Insulating film 16 wire bonding pad electrode

Claims (2)

(57) [Claims] 1. A circuit cell region in which a plurality of circuit cells are arranged in the central portion of a chip, and an input / output unit in which an input / output trunk line composed of an input trunk line and an output trunk line is arranged around the circuit cell region. An area of the input / output main line having an input / output cell area in which a plurality of input / output cells are arranged outside the main line area and the input / output main line, and electrically connected to an input / output terminal in the circuit cell by a wiring layer. The input / output terminals of the input / output cells are electrically connected to each other in a region different from that by the wiring layer , and the input / output trunk is provided in the second wiring layer.
In the input / output main line and the circuit cell
The wiring layer to which the input / output terminals are electrically connected is the first layer wiring
The input / output trunk line and the input / output cell are provided in a layer.
The wiring layer in which the input / output terminals are electrically connected is one layer
A semiconductor integrated circuit device provided in the third or third wiring layer . 2. A plurality of circuit cells are arranged in the central portion of the chip.
The surrounding circuit cell area is
Turn to distribute the input / output trunk line consisting of the input trunk line and the output trunk line.
I / O trunk area that is placed and outside the I / O trunk line
I / O cell area where multiple I / O cells are arranged
By the input / output terminal and the wiring layer in the circuit cell.
Different from the area of the input / output trunk line that is electrically connected
In the area, the input / output terminals of the input / output cells are connected to the wiring layer.
The I / O trunk line is installed in the second wiring layer.
The input / output terminal of the input / output cell is 1
It is provided on both the third and third wiring layers,
The output trunk line and the input / output terminals of the input / output cells are electrically connected.
Continued wiring layers are selected as needed and
Alternatively, the semiconductor integrated circuit device is provided in the third wiring layer .