JP2911980B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, a first wiring region is formed in a plurality of islands, and the first wiring region is formed as a second wiring region. The present invention relates to a semiconductor integrated circuit device having a semi-custom configuration arbitrarily connected by a wiring region.

[Conventional technology]

At present, semi-custom integrated circuits (hereinafter referred to as ICs) mainly using CMOS gate arrays are widely used. In this type of IC, a desired circuit configuration can be realized on a wafer on which many elements such as MOS transistors are formed.
Design wiring patterns for each product type. Therefore, after designing this wiring pattern, any IC can be completed in a short time only by forming a wiring region based on the wiring pattern on the wafer. Usually, it is only necessary to design the four processes of the contact, the first wiring, the through hole, and the second wiring for each product type, which is advantageous in terms of price and time as compared with designing and manufacturing all the processes. is there.

However, as a further development of these semi-custom ICs recently, the contact and first wiring processes, which were previously designed for each product type, have been standardized, and only two processes, through-hole and second wiring formation, have been designed for each product type. Techniques have been used.

In this method, the first wiring region is used as a fixed wiring (underpass wiring) in addition to the use as a terminal portion of the element, and a through hole and a second wiring are provided at appropriate positions to connect with the element terminal. The connection and the connection between the elements are realized. Therefore, although there is a decrease in the arrangement density of elements and a decrease in the degree of freedom in wiring compared to the conventional method, it is 1 /
There is an advantage that an IC can be obtained at a price of 2 and a wiring forming period.

In designing an IC using this method, since only one layer can be freely wired, it is important how to increase the utilization of the first layer wiring. Therefore, in this type of IC, an extremely large number of connection portions between the first wiring and the second wiring are generated, and the connection between the first wirings is performed using the second wiring.

FIG. 4 shows an example thereof, wherein FIG. 4 (a) is a plan view and FIG. 4 (b) is a longitudinal sectional view thereof. That is, openings 4A and 4B are provided in the interlayer insulating film 3 on each of the two first wiring regions 2A and 2B to connect the two first wiring regions 2A and 2B, and the second wiring region 5 is formed over the openings to form the second wiring region 2A. The two first wiring regions 2A and 2B are connected.

[Problems to be solved by the invention]

In such a conventional connection structure, the openings 4A and 4B are provided so as to be included in the first wiring region, that is, smaller than the width of the first wiring regions 2A and 2B.
This is to prevent the semiconductor substrate 1 from being partially removed when the opening is provided. As a result, two openings 4A and 4B are required to connect the two first wiring regions 2A and 2B, and as a result, as many openings as the number of the first wiring regions are required.

Further, the second wiring region 5 is formed so as to cover these openings 4A and 4B, but this region is a region through which other second wiring regions cannot pass.

For example, FIG. 5 (a) shows a wafer in which a large number of first wiring regions 2 are formed in a strip-like island shape connected to various elements formed on a semiconductor substrate 1, and an opening is formed in the wafer. FIG. 5B shows a state where wiring is performed using the portions 4 ′ (4 A and 4 B) and the second wiring region 5.

In FIG. 5 (b), when it is attempted to pass through the second wiring region 5A as shown by another dashed line, the interval between the second wiring regions 5 for connection of the first wiring region is reduced. It is impossible to pass through this part.

Therefore, in order to reduce these unwiringable regions, it is necessary to form a large strip-shaped region of the first wiring region 2. However, assuming that the area of the chip is constant, increasing the area of the strip-shaped region reduces the number of the strip-shaped regions, which causes a problem that the degree of freedom in wiring is reduced accordingly.

Further, since the opening 4 'is provided with a minimum area, the resistance component in this portion cannot be ignored, and a considerably large contact resistance occurs in a wiring formed by connecting many first wiring regions.

An object of the present invention is to provide a semiconductor integrated circuit device having a wiring connection structure in which the degree of freedom in wiring is increased and the contact resistance is reduced.

[Means for solving the problem]

The semiconductor integrated circuit device of the present invention includes at least a first wiring layer, a second wiring layer, and an insulating layer that insulates the first wiring layer from the second wiring layer, and is formed by the first wiring layer. The first to fourth wirings, which are parallel to each other, and the fifth wiring formed of the second wiring layer form a right angle, and the first and second wirings and the third and fourth wirings are electrically connected to each other. Connected and
In a semiconductor integrated circuit having a structure in which a fifth wiring passes between an electrical connection between first and second wirings and an electrical connection between third and fourth wirings, the first and second wirings are provided. The electrical connection part of the wiring and the electrical connection part of the third and fourth wirings are formed on an insulating layer provided between the first and second wirings and the third and fourth wirings. An opening for exposing the upper end surface and the side surface is formed, and the opening is formed by a second wiring layer covering the opening.

[Action]

According to the present invention, by connecting the second wiring region to the first wiring region through the opening formed between the first wiring regions, the area of the opening and the second wiring region in the planar direction can be reduced. On the other hand, the contact resistance is reduced by increasing the substantial contact area between the second wiring region and the first wiring region.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a connection portion between a first wiring region and a second wiring region according to the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is a sectional view.

As the first wiring regions 2A and 2B, a low-resistance material such as aluminum is selectively formed on the semiconductor substrate 1 with a minimum interval determined by the resolution. Thereafter, an interlayer insulating film 3 is formed on the surface, and openings 4 are formed in the interlayer insulating film 3 so as to overlap with each other over the first wiring regions 2A and 2B. At this time, the insulating film 3 needs to be made of a material different from that of the semiconductor substrate 1, and a solvent that does not etch the surface of the lower semiconductor substrate 1 when the opening 4 is provided in the interlayer insulating film 3. Needs to be present.

Usually, since the surface of the semiconductor substrate 1 is a silicon oxide film, it is possible to use a polyimide material as the interlayer insulating film 3 and an alkali organic solvent as the solvent. Thus, even if the opening 4 is opened in a region where neither of the first wiring regions 2A and 2B exists, the solvent does not etch the surface of the semiconductor substrate 1.

After the opening 4 is provided so as to overlap the two first wiring regions 2A and 2B, the second wiring region 5 is formed so as to cover the opening 4, whereby the first wiring region 2A is formed. When
2B will be electrically connected.

With such a connection structure, the area of the second wiring region 5 in the planar direction is reduced. That is, the size of the opening 4 is 2 μm on each side, the minimum interval between the first wiring regions 2A and 2B is 2 μm, and the opening 4 is formed inside the first wiring regions 2A and 2B.
It is assumed that it must be formed within μm, and the second wiring region 5 must cover the opening 4 by 2 μm or more.

In the conventional connection structure, the size of the second wiring region required for connection between the first wirings at one location is at least 14 μm × 6 μm.
m. On the other hand, in the present invention, assuming that the amount of overlap between the opening and the first wiring region is 2 μm and the other dimensions are the same as the conventional one, the minimum size of the second wiring region is 10 μm.
μm × 6 μm, and the area is reduced by about 30%.

On the other hand, in the present invention, the second wiring region is formed on the side surface of the first wiring region.
Therefore, if the area of the opening in the plane direction is the same, the substantial contact area is increased, and the contact resistance between the two is reduced.

FIG. 2A shows a semiconductor substrate 1 similar to FIG. 5A.
The wafer on which a plurality of strip-shaped island-shaped first wiring regions 2 are formed is shown. FIG. 2B shows a state in which an interlayer insulating film is formed thereon and wiring is performed using the opening 3 and the second wiring region 5.

In FIG. 2 (b), the second wiring region 5A, which was impossible in FIG. 5 (b), is disposed between other second wiring regions 5 due to the reduction in the area of the second wiring region. It becomes possible. Thus, by reducing the area of the second wiring region 5, the number of the second wiring regions 5 can be increased, and the degree of freedom of wiring can be increased.

FIG. 3 shows a second embodiment of the present invention. FIG. 3 (a) is a plan view and FIG. 3 (b) is an enlarged sectional view. Here, the gate electrode of the silicon gate MOS transistor is configured as a first wiring region. In the figure, an oxide film 12 is formed on a semiconductor substrate 11, an element region is defined, a diffusion region 13 is formed in the element region as a source / drain region, and a gate is formed via a gate insulating film (not shown). The electrode 14 is formed of polycrystalline silicon. Then, the gate electrode 14
An opening 16 is provided in the interlayer insulating film 15 provided thereon, and the second
The adjacent gate electrodes 14 are electrically connected to each other by a wiring region (first-layer metal wiring) 17.

As described above, by applying the present invention to the connection between the gate electrodes of the MOS transistors, the area of the second wiring region can be reduced, and the degree of freedom of wiring in the second wiring region can be increased.

〔The invention's effect〕

As described above, according to the present invention, the opening is formed in the insulating film between the first wiring regions, and the second wiring region is connected to the first wiring region through the opening. In addition, the area of the second wiring region in the planar direction can be reduced, the number of the second wiring regions can be increased, and the degree of design freedom can be increased.
Since a part of the wiring region is formed larger than the outer dimension of the opening, the effect of increasing the substantial contact area between the second wiring region and the first wiring region and reducing the contact resistance can be obtained. is there.

[Brief description of the drawings]

FIG. 1 shows the structure of a main part of the present invention. FIG. 1 (a) is a plan view, FIG. 1 (b) is a sectional view thereof, and FIG. 2 shows a semiconductor integrated circuit device to which the present invention is applied. FIG. 3A is a plan view of a first wiring region, FIG. 3B is a plan view of a second wiring region, FIG. 3 shows a second embodiment of the present invention, and FIG. FIG. 4 (b) is a sectional view thereof, FIG. 4 shows an example of a conventional wiring connection structure, FIG. 4 (a) is a plan view, FIG. 4 (b) is a sectional view, and FIG. 3A and 3B show a semiconductor integrated circuit device using the technique shown in the figure, wherein FIG. 3A is a plan view of a first wiring region, and FIG. 3B is a plan view of a second wiring region. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2A, 2B ... 1st wiring area, 3 ... Interlayer insulating film, 4, 4 ', 4A, 4B ... Opening, 5, 5A ... 2nd wiring area, 11 ... Semiconductor Substrate, 12 oxide film, 13 diffusion region, 14 gate electrode (first wiring region), 15 interlayer insulating film, 16 second wiring region

Claims (1)

(57) [Claims] A first wiring layer, a second wiring layer, and an insulating layer insulating the first wiring layer and the second wiring layer; The first to fourth wirings and a fifth wiring formed in the second wiring layer form a right angle, the first and second wirings and the third and fourth wirings are electrically connected, respectively, and And a fifth connection between the electrical connection between the first and second wirings and the electrical connection between the third and fourth wirings.
In the semiconductor integrated circuit having the structure in which the first wiring passes through, the electrical connection part of the first and second wirings and the electrical connection part of the third and fourth wirings have the first, second, and third wirings. The first through fourth insulating layers are provided on an insulating layer provided between the fourth wirings.
A semiconductor integrated circuit device, wherein an opening for exposing the upper end surface and side surface of the wiring is formed and a second wiring layer covering the opening is formed.