JP2855991B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a mask layout of a periodic pattern such as a memory.

[0002]

2. Description of the Related Art At present, there are a large number of semiconductor devices having a periodic pattern such as a decoder section, and a high integration degree is required. You need more. In particular, regarding semiconductor memories, there are many periodic patterns having a large number of repetitions such as sense amplifiers in addition to decoders. Also, due to chip size limitations, these periodic patterns always include an end portion at which a repeated portion of the pattern ends. Exists.

FIG. 4 is a plan view showing an example of a periodic pattern of a conventional semiconductor device. FIG. 4A shows a periodic pattern of a photoresist film for shaping a silicide wiring layer connected to an aluminum wiring layer, and the intervals and widths of the wiring portions 8-1... And the connection portions 9-1. Designed with minimum design criteria. Are located at the ends of the periodic pattern.

In a conventional semiconductor device, in a periodic pattern in a decoder, a sense amplifier, or the like, a repetitive portion designed according to a minimum design standard and an end portion of the periodic pattern end as shown in FIG. It was designed with the same dimensions.

[0005] A method of manufacturing the conventional semiconductor device will be described. As shown in FIGS. 4A and 4B, a field oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1, and a gate oxide film 3 and a gate electrode 4 are formed on the surface of an active region partitioned. Then, N-type impurity diffusion layers 5-1 and 5-2 are formed, and an interlayer insulating film 6 is deposited. Next, a tungsten silicide film 7 is deposited on the entire surface. In a DRAM or the like, this tungsten silicide film is for forming a digit line connected to one of source / drain regions of a MOS transistor (not shown) (not shown) constituting a memory cell. That is,
In the case of a DRAM, after forming a MOS transistor of a memory cell and a capacitor to be illustrated, an interlayer insulating film 6 (shown directly covering the gate electrode 4 in the figure,
Actually, depending on the type of the memory cell, it may correspond to the order of the interlayer insulating film. ), A digit line contact hole is opened above one of the source / drain regions of the MOS transistor of the memory cell described above, and a tagusten silicide film 7 is deposited. Next, a photoresist film is applied and exposed using a predetermined exposure mask, and the resist film other than a portion to be a wiring is etched to form a wiring portion 8-.
An etching mask composed of 1,..., Connecting portions 9-1,. Next, etching is performed using this etching mask, and as shown in FIG.
, With tungsten silicide wiring layer 10-1,
... is formed. Here, when etching the tungsten silicide film of the wiring material, the wiring material to be eliminated and the etching gas are reacted and decomposed and removed using dry etching.

The tungsten silicide wiring layer 10-1,
The wiring intervals of 10-2,... Are the minimum design reference intervals, whereas the connection regions 11-1,.
As described above, the interval between adjacent wiring layers does not become the minimum design reference interval, and is often different from the internal shape of the periodic pattern. When etching is performed at a location inside the periodic pattern where the wiring interval is small, the etching gas is hard to rotate and hardly reacts. If an appropriate etching time is determined in order to etch the wiring material in a portion not covered with the photoresist film inside the periodic pattern, an etching gas is sufficiently supplied as in the end of the periodic pattern. Many portions will be etched.

Subsequently, an interlayer insulating film 12 is deposited, and a through hole 13 and a contact hole 14 are opened. That is,
Wet etching such as buffered hydrofluoric acid and CHF
Perform dry etching by ₃ or the like. Through hole 1
In the portion of No. 3, the tungsten silicide film (11-1, 1
It is considered that the etching does not actually proceed any more when 1-2,...) Are exposed.
In part 4, the etching proceeds until the N-type impurity diffusion layer 5-1 is exposed. Next, as shown in FIG. 6, an aluminum alloy film is deposited and patterned to form an upper layer wiring 1.
5-1... Are formed.

The upper wirings 15-1,..., For example, connect the digit lines (10-1, 10-2,...) In the memory with the source / drain regions (5-1) of the MOS transistors of the sense amplifier and the transfer gate. This is the wiring to be connected.

[0009]

As described above, as a result of excessive etching at the end of the periodic pattern as compared with the internal region of the pattern, as shown in FIG. Are smaller than design values (11-2, 11-4,... Are assumed to be as designed values). This is particularly remarkable in 11-1. Therefore, if the position of the through hole is displaced as shown by the broken line due to misalignment in the formation of the through hole 13, in the worst case, the opening 13 a reaching the P-type silicon substrate 1 may be formed. There is. Therefore, the upper wiring 15-1 and the P-type silicon substrate 1
May be short-circuited. If another wiring layer exists between the tungsten silicide film and the P-type silicon substrate, a short circuit or poor insulation will occur between the wiring layer and the other wiring layer.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a semiconductor element including an impurity diffusion layer selectively formed on a surface portion of a semiconductor substrate, and a step of depositing a first interlayer insulating film, A step of forming a resist film in a predetermined region of the first conductive film in a periodic pattern, etching the first conductive film using the resist film as a mask, and forming a connection region having a connection region. Forming a first wiring layer;
Depositing an interlayer insulating film, and performing etching using a mask member that selectively covers the second interlayer insulating film to form a through hole reaching the connection region and a contact hole reaching a predetermined impurity diffusion layer. A second conductive film is deposited and patterned to form a second conductive film.
Forming a wiring layer, wherein the dimensions of the resist film for forming the connection region are set larger at the end of the periodic pattern than at other portions.

[0011]

Referring to FIG. 1, in one embodiment of the present invention, a field oxide film 2, a gate oxide film 3, an interlayer insulating film 6, and a tungsten silicide film 7 are formed on a P-type silicon substrate 1 in the same manner as in the conventional example. After that, a photoresist film including wiring portions 8-1,..., Connecting portions 9A-1,. At this time, the connection portions 9A-1, 9A at the ends of the periodic pattern
-3, 9A-5,... Are larger than the internal connection parts 9-2, 9-4,. Similarly, the dimension of the connection portion 9A-1 is increased by B at the bottom of the figure. The thickness of the tungsten silicide film 7 is 200 nm, the width of the wiring portion is 0.8 μm, the interval is 0.7 μm, and the connection portions 9-2 and 9-4.
Is 1.6 μm × 1.7 μm, A and B are both 0.2 μm.

[0012] Next, the tungsten silicide wiring layer etching was carried out by CHF ₃ gas 10-1,10-
2,... Connection regions 11A-1, 11-2,.
The connection regions 11A-1, 11-2, 11A-3,... Have substantially the same shape. Next, through holes 13 and connection holes 14 are formed in the same manner as in the conventional example, and as shown in FIG. 3, an aluminum alloy film is deposited and patterned to form upper wirings 15-1,.

Since the shape of the connection region can be formed substantially uniformly in the periodic pattern portion, even if there is misalignment, it does not exceed a margin determined in advance. Therefore, short-circuiting between wirings and defective insulation, which have conventionally been problems, do not occur.

[0014]

As described above, according to the present invention, the periodic pattern is formed by performing etching using a mask in which the dimensions of the wirings and connection portions at the ends of the periodic pattern of the semiconductor device are set larger than those of the internal region. Even if many edges are etched, it can be formed to have substantially the same dimensions as the internal area, and the holes to connect the different wiring layers will shift and short-circuit with the lower substrate or other wiring layers. Insulation failure can be prevented, and the yield of semiconductor devices can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1A) and a cross-sectional view (FIG. 1B) of a semiconductor chip for explaining one embodiment of the present invention.

FIGS. 2A and 2B are a plan view (FIG. 2A) and a cross-sectional view (FIG. 2B) for describing a post-process corresponding to FIG.

3A and 3B are a plan view (FIG. 3A) and a cross-sectional view (FIG. 3B) for explaining a post-step of a step corresponding to FIG.

FIG. 4 is a plan view (FIG. 4A) and a cross-sectional view (FIG. 4B) of a semiconductor chip for explaining a conventional example.

5A and 5B are a plan view (FIG. 5A) and a cross-sectional view (FIG. 5B) for describing a post-process corresponding to FIG.

6A and 6B are a plan view (FIG. 6A) and a cross-sectional view (FIG. 6B) for describing a post-process corresponding to FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5-1 and 5-2 N-type impurity diffusion layer 6 Interlayer insulating film 7 Tungsten silicide film 8-1 to 8-5 Photoresist film (wiring part) 9-1, 9A-1, 9-2, 9-3, 9A-3, ...
Photoresist film (connection part) 10-1 to 10-5 Tungsten silicide wiring layer 11-1, 11A-1, 11-2, 11-3, 11A-
3, connection area 12 interlayer insulating film 13 through hole 13a opening 15-1 to 15-5 wiring layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/027 H01L 21/3065 H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (1)

(57) [Claims] A step of forming a semiconductor element including an impurity diffusion layer selectively formed on a surface portion of a semiconductor substrate; a step of depositing a first interlayer insulating film; and a step of depositing a first conductive film. Forming a resist film on a predetermined region of the first conductive film in a periodic pattern and etching the first conductive film using the resist film as a mask to form a first wiring layer having a connection region Depositing a second interlayer insulating film, etching using a mask member for selectively covering the second interlayer insulating film, and forming a through hole reaching the connection region and a predetermined impurity diffusion layer. Forming a second conductive layer by depositing a second conductive film and patterning the second conductive film to form a second wiring layer. Wherein the dimension of the periodic pattern is set larger at the end of the periodic pattern than at other portions.