JPH06275847A - Semiconductor device having floating gate and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and its manufacture, in which a satisfactory contact structure being little in the variation of transistor characteristics can be realized in the semiconductor device with an ordinary transistor existing in an array of transistors having a floating gate. CONSTITUTION:The title semiconductor device has a struture, in which a memory-cell transistor 2 having a floating gate 11 and a selective transistor 4 having no floating gate are connected in series via diffused impurity layer 40 formed on the surface of a semiconductor substrate, and an upper layer side wiring layer 48 is connected with the diffused impurity layer 40 via contact hole 54. An etching groove 52 formed on the surface of the semiconductor substrate placed between the memory-cell transistor 2 and selective transistor 4 is formed in a position near to the selective transistor 4 side and the contact hole 54 is formed so as not to overlap with the etching groove 52.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a floating gate and a method of manufacturing the same, and more particularly, to a semiconductor device having an ordinary transistor in an array of transistors having a floating gate. There is little variation in characteristics,
The present invention relates to a semiconductor device capable of realizing a good contact structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a semiconductor device having a floating gate, particularly a NOR flash memory semiconductor device, a normal transistor may be arranged as a selection transistor in a transistor array having a floating gate. For example, as shown in FIG.
In the OR type flash memory semiconductor device, a plurality of memory cell transistors 2 each including a transistor having a floating gate are connected in an array, and each array includes a normal transistor having no floating gate. The selection transistors 4 are connected in series. In FIG. 10, reference numeral 6 is a main bit line, reference numeral 8 is a sub bit line, and reference numeral 10 is a common source line.

A schematic cross section of such a NOR type flash memory semiconductor device is shown in FIG. 11, and its plan view is shown in FIG.
Shown in. As shown in FIGS. 11 and 12, the NOR flash memory semiconductor device is formed on the semiconductor substrate 1. The memory cell transistor 2 has a double gate structure having the floating gate 11 and the control gate 12, and the selection transistor 4
Has a MOS transistor structure having a single gate electrode 14.

Since the memory cell transistor 2 and the selection transistor 4 are connected by the sub-bit line 8 shown in FIG. 10, the sub-bit shown in FIG. 10 is formed above the control gate 12 via an interlayer insulating layer. A wiring layer 8a to be the bit line 8 is laminated. In addition, on the sub-bit line wiring layer 8a to be the sub-bit line 8, an inter-layer insulating layer is provided, as shown in FIG.
The main bit line wiring layer 6a to be the main bit line 6 shown in FIG.

Sub-bit line wiring layer 8a is connected to drain impurity diffusion layer 18 of each memory cell transistor 2 formed on the surface of semiconductor substrate 1 through contact hole 16. In addition, the main bit line wiring layer 6
a is connected to the source / drain impurity diffusion layer 22 of the selection transistor 4 through the contact hole 20. In addition, in FIGS. 11 and 12, reference numeral 24 represents FIG.
The source impurity diffusion layer of each memory cell transistor, which is the common source line 10 shown in FIG.

In the case of manufacturing such a NOR type flash memory semiconductor device, the polysilicon layer forming the floating gate 11 of the memory cell transistor 2 is deleted at the selection transistor 4 and the control gate 12 is formed. The polysilicon layer that constitutes the gate electrode of the selection transistor 4 is formed, and between the memory cell transistor 2 and the selection transistor 4,
It is necessary to form the contact hole 16.

[0007]

Therefore, for example, as shown in FIG. 13, in the process of manufacturing a semiconductor device, on the surface of the semiconductor substrate 1 located between the memory cell transistor 2 and the selecting transistor 4, Etching groove 30
May be formed. As shown in FIG. 13, when the etching groove 30 is formed in the vicinity of the specific memory cell transistor 2 adjacent to the selecting transistor 4, the diffusion resistance of the impurity diffusion layer 18 at that portion is changed to the etching groove. It becomes higher than that of the diffusion layer portion not formed. Therefore, only the characteristics of the specific memory cell transistor 2 are different from the characteristics of the other memory cell transistors, and the characteristics of the memory as a whole greatly vary.

Further, as shown in FIG. 14, when the contact hole 16 is formed so as to overlap the etching groove 30, the contact characteristics between the wiring layer 8a and the impurity diffusion layer 18 are not stable, and the inside of the contact hole 16 is unstable. However, there is a problem that the coverage of the wiring layer 8a also deteriorates, and the manufacturing yield decreases.

The present invention has been made in view of the above circumstances, and in a semiconductor device in which an ordinary transistor exists in an array of transistors having a floating gate, there is little variation in transistor characteristics and a good contact structure is realized. It is an object of the present invention to provide a semiconductor device that can be manufactured and a manufacturing method thereof.

[0010]

In order to achieve the above object, in a semiconductor device of the present invention, a first transistor having a floating gate and a second transistor having no floating gate are provided on a surface of a semiconductor substrate. The first transistor and the second transistor are formed in series and are connected in series via an impurity diffusion layer formed on the surface of the semiconductor substrate, and the first transistor and the second transistor are connected to the impurity diffusion layer. In a semiconductor device having a structure in which a wiring layer formed on the upper side of two transistors is connected through a contact hole, etching formed on the surface of a semiconductor substrate located between the first transistor and the second transistor. A groove is formed at a position close to the second transistor side, and the contact hole is formed with respect to the etching groove. Characterized in that is formed so as not to overlap.

The semiconductor device manufacturing method of the present invention is
A step of forming a gate insulating layer on the surface of the semiconductor substrate and forming a first conductive layer to be a floating gate on the gate insulating layer; and a step of forming the first transistor on the surface of the semiconductor substrate where the second transistor is formed. A step of removing the first conductive layer, a step of forming an intermediate insulating layer on the first conductive layer, a step of forming a control gate of the first transistor on the intermediate insulating layer, and a gate of the second transistor A step of forming a second conductive layer to be an electrode, a step of etching the second conductive layer into a pattern of the gate electrode of the second transistor, and a step of forming the second conductive layer into a pattern of the control gate of the first transistor. Etching step, and etching the intermediate insulating layer and the first conductive layer into a pattern of the floating gate of the first transistor And a step of forming an etching groove on the surface of the semiconductor substrate located in the vicinity of the second transistor during the etching process of the first conductive layer, and a semiconductor substrate located between the first transistor and the second transistor. Forming a source / drain region impurity diffusion layer on the surface of the substrate, forming an interlayer insulating layer on the first transistor and the second transistor, and forming the source / drain region impurity on the interlayer insulating layer. And a step of forming a contact hole exposing the surface of the diffusion layer so as not to overlap the etching groove.

[0012]

In the semiconductor device of the present invention, the resistance of the impurity diffusion layer of the specific first transistor adjacent to the second transistor is the same as that of the other first transistor, and only the characteristics of the specific first transistor are different. The characteristics of the semiconductor device as a whole are improved since they do not vary from others.

Further, since the contact hole does not overlap the etching groove, the coverage of the wiring layer formed in the contact hole is improved, the resistance at the contact portion is stably lowered, and the manufacturing yield is improved. To do. Further, according to the manufacturing method of the present invention, a semiconductor device having excellent characteristics as described above can be easily obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device having a floating gate and a method of manufacturing the same according to an embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic sectional view of a main portion of a semiconductor device having a floating gate according to an embodiment of the present invention, FIG.
9A to 9C are schematic cross-sectional views of main parts showing the manufacturing process of the semiconductor device of the embodiment. The structure of the semiconductor device according to the present embodiment shown in FIG. 1 is adopted as the structure between the memory cell transistor 2 and the selection transistor 4 in the NOR flash memory semiconductor device shown in FIG. 10, for example.

In the structure of this embodiment, as shown in FIG.
For example, a memory cell transistor 2 having a floating gate 11 as a first transistor on the surface of a semiconductor substrate 1 composed of a silicon single crystal wafer or the like.
And a selecting transistor 4 which is an ordinary transistor having no floating gate as the second transistor. The memory cell transistor 2 and the selection transistor 4 are connected in series via an impurity diffusion layer 40 formed on the surface of the semiconductor substrate 1.

The memory cell transistor 2 has a floating gate 11 and a control gate 12.
These are laminated on the surface of the semiconductor substrate 1 with the gate insulating layer 42 and the intermediate insulating layer 44 interposed therebetween. An interlayer insulating layer 46 is laminated on the memory cell transistor 2, and a wiring layer 48 is laminated thereon. Wiring layer 48 corresponds to sub bit line 8 in the circuit shown in FIG. 10, for example.

The selection transistor 4 has a gate electrode 14
Have. The gate electrode 14 is formed on the surface of the semiconductor substrate 1,
The gate insulating layer 50 is stacked. An interlayer insulating layer 46 is laminated on the gate electrode.

In the present embodiment, in the process of manufacturing such a semiconductor device, the etching groove 52 formed on the surface of the semiconductor substrate 1 is formed at a position closer to the selection transistor 4 side than the memory cell transistor 2. It Moreover, the contact hole 54 formed in the interlayer insulating layer 46 for connecting the wiring layer 48 and the impurity diffusion layer 40.
Is formed at a position that does not overlap the etching groove 52.

As a result, according to the present embodiment, the resistance of the impurity diffusion layer 40 of the specific memory cell transistor 2 adjacent to the selection transistor 4 becomes the same as that of the other memory cell transistors, and Only the characteristics of the memory cell transistor of 2 will not differ from others, and the characteristics of the memory as a whole will be improved. Further, since the contact hole 54 does not overlap the etching groove 52, the coverage of the wiring layer 48 formed in the contact hole 54 is improved, the resistance at the contact portion is stably lowered, and the manufacturing yield is also improved. improves.

The groove width of the etching groove 52 is not particularly limited, but is, for example, 0.1 to 0.4 μm, and the groove width may be 100 nm or more.

Next, an example of a manufacturing method for obtaining the structure of the semiconductor device according to the above-described embodiment will be described. First, as shown in FIG. 2, the LOC is formed on the surface of the semiconductor substrate 1.
After forming the element region by the OS method or the like, the gate insulating layer 42 of the memory cell transistor is formed. The gate insulating layer 42 is formed of, for example, a silicon oxide layer formed by a thermal oxidation method, and the film thickness thereof is not particularly limited, but is about 10 nm, for example. Next, this gate insulating layer 4
A first conductive layer 11a, which will be the floating gate of the memory cell transistor, is formed on the oxide film to be 2.
The first conductive layer 11a is formed of, for example, a polysilicon film formed by a CVD method, and the film thickness thereof is not particularly limited, but is about 100 nm, for example.

Next, as shown in FIG. 3, the first conductive layer 11 is formed.
a is etched to remove the portion of the first conductive layer 11a corresponding to the position where the selection transistor is formed. Then, as shown in FIG. 4, an insulating film to be the intermediate insulating layer 44 is formed. The insulating film to be the intermediate insulating layer 44 is composed of a silicon oxide film obtained by a CVD method, an ONO film (a multilayer film in which a silicon nitride film is stacked between silicon oxide films), or the like. At the same time, the gate insulating layer 50 for the selecting transistor is formed in the region where the selecting transistor is formed. The film thickness of the gate insulating layer 50 is, for example, 3
It is about 0 nm.

A second conductive layer 12a is formed on the intermediate insulating layer 44 and the gate insulating layer 50 as a control gate in the memory cell transistor region and as a gate electrode in the selection transistor region. The second conductive layer is
For example, it is formed of a polysilicon film obtained by the CVD method, and the film thickness thereof is not particularly limited, but is, for example, 20.
It is about 0 nm.

Next, as shown in FIG. 5, the second conductive layer 12 is formed.
A resist film 6 for processing a selection transistor is formed on the surface of a.
0 is formed, an opening 62 is formed in the resist film 60, and the second conductive layer 12a is patterned through the opening 62 by etching such as RIE to obtain the gate electrode 14 of the selection transistor. .

Next, as shown in FIG. 6, the resist film 60 for processing the selecting transistor is removed, then a resist film 64 for processing the memory cell transistor is formed, and an opening is formed in the resist film 64. 66, and the second conductive layer 12 is formed through the opening 66 by etching such as RIE.
By patterning a, the control gate 12 of the memory cell transistor is obtained.

Next, as shown in FIG. 7, the intermediate insulating layer 44 is etched using the same resist film 64. At that stage, the gate insulating layer 50 of the unnecessary portion of the selection transistor is also etched, and the surface 70 of the semiconductor substrate 1 not covered with the first conductive layer 11a or the resist film 64 is exposed. Further, subsequently, the first conductive layer 11
A is etched to obtain the floating gate 11 having a predetermined pattern. At that time, the surface 70 of the semiconductor substrate 1 exposed in the step shown in FIG. 7 is simultaneously etched,
The etching groove 52 is formed. The depth of the etching groove 52 may be 100 nm or more, for example. As shown in FIG. 7, the groove width of the etching groove 52 is determined according to the distance L between the end of the resist film 64 and the end of the first conductive layer 11a, and is, for example, 0.1 to 0.4 μm, preferably. Is 0.2 to 0.3 μm. This distance L cannot be 0 or less. This is because the first conductive layer 11a cannot be etched well.

In the present embodiment, the patterning of the first conductive layer 11a shown in FIG. 3 is performed so that the position where the etching groove 52 is formed is near the selection transistor 4.

As shown in FIG. 8, when the final processing of the first conductive layer 11a is completed, the source / drain region impurity diffusion layers 40 are formed on the surface of the semiconductor substrate 1 by ion implantation or the like. To do. Next, as shown in FIG. 9, an interlayer insulating layer 46 made of, for example, a silicon oxide film is formed by a CVD method to form a contact hole 54 facing the source / drain region impurity diffusion layer 40. . The contact hole 54 is formed at a position that does not overlap the etching groove 52.

Although not shown in FIGS. 8 and 9, since the plurality of memory cell transistors 2 are connected in series as shown in the circuit diagram of FIG. When the impurity diffusion layer 40 for the drain region is formed, the impurity diffusion layer for the source / drain region is also formed between the memory cell transistors 2. And
In order to form the circuit configuration shown in FIG.
The contact holes facing the impurity diffusion layer between the memory cell transistors 2 in the pattern where
It is formed at the same time when the contact hole 54 is formed.

After forming the contact hole 54, as shown in FIG.
As shown in, the wiring layer 48 is formed. The wiring layer 48 is
For example, it is composed of a polysilicon film or an aluminum metal film formed by the CVD method.

According to the manufacturing method of this embodiment, the semiconductor device having excellent characteristics as described above can be easily obtained.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above-described embodiments, an example in which the structure and manufacturing method of the present invention are applied to a NOR flash memory semiconductor device has been described, but the structure and manufacturing method of the present invention are not limited to this, and other semiconductors are used. It can also be applied to a device. However, in an array of transistors with floating gates,
It is necessary that the semiconductor device has an ordinary transistor.

[0034]

As described above, according to the present invention, the resistance of the impurity diffusion layer of the specific first transistor adjacent to the second transistor becomes equal to that of the other first transistor, Only the characteristic of the first transistor of No. 1 does not vary from others, and the characteristic of the semiconductor device as a whole is improved.

Further, since the contact hole does not overlap the etching groove, the coverage of the wiring layer formed in the contact hole is good, the resistance at the contact portion is stably low, and the manufacturing yield is improved. To do. Further, according to the manufacturing method of the present invention, a semiconductor device having excellent characteristics as described above can be easily obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of essential parts of a semiconductor device having a floating gate according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 3 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 4 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 5 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 6 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 7 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 8 is a main-portion schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment;

FIG. 9 is a schematic sectional view of a key portion showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 10 is an equivalent circuit diagram of a NOR flash memory semiconductor device.

FIG. 11 is a schematic cross-sectional view of a main part of a NOR flash memory semiconductor device.

FIG. 12 is a plan view of an essential part of a NOR flash memory semiconductor device.

FIG. 13 is a schematic cross-sectional view of a main part of a NOR flash memory semiconductor device according to a conventional example.

FIG. 14 is a schematic cross-sectional view of a main part of a NOR flash memory semiconductor device according to another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Memory cell transistor 4 ... Selection transistor 11 ... Floating gate 11a ... First conductive layer 12 ... Control gate 12a ... Second conductive layer 14 ... Gate electrode 40 ... Source / drain region impurity diffusion layer 42 ... Gate insulating layer 44 ... Intermediate insulating layer 46 ... Interlayer insulating layer 48 ... Wiring layer 50 ... Gate insulating layer 52 ... Etching groove 54 ... Contact hole

Claims (4)

[Claims] 1. A first transistor having a floating gate and a second transistor not having a floating gate are formed on a surface of a semiconductor substrate, and the first transistor and the second transistor are formed on the semiconductor substrate. Are connected in series via an impurity diffusion layer formed on the surface of the wiring layer, and the wiring layer formed on the upper side of the first transistor and the second transistor is connected to the impurity diffusion layer via a contact hole. In the semiconductor device having the above structure, the etching groove formed on the surface of the semiconductor substrate located between the first transistor and the second transistor is formed at a position close to the second transistor side, and The contact hole is formed so as not to overlap this etching groove. A semiconductor device having a Ngugeto. 2. The semiconductor device having a floating gate according to claim 1, wherein the depth of the etching groove formed on the surface of the semiconductor substrate is 100 nm or more. 3. A first transistor having a floating gate and a second transistor not having a floating gate are formed on a surface of a semiconductor substrate, and the first transistor and the second transistor are a semiconductor substrate. Are connected in series via an impurity diffusion layer formed on the surface of the wiring layer, and the wiring layer formed on the upper side of the first transistor and the second transistor is connected to the impurity diffusion layer via a contact hole. Forming a gate insulating layer on a surface of a semiconductor substrate, and forming a first conductive layer to be a floating gate on the gate insulating layer, the second transistor A step of removing the first conductive layer at a surface position of the semiconductor substrate on which the intermediate insulating layer is formed, and forming an intermediate insulating layer on the first conductive layer. And a step of forming a second conductive layer on the intermediate insulating layer, the second conductive layer being a control gate of the first transistor and a gate electrode of the second transistor. Etching the gate electrode pattern of the first transistor, etching the second conductive layer into the control gate pattern of the first transistor, and etching the intermediate insulating layer and the first conductive layer into the floating of the first transistor. A step of etching the gate pattern, a step of forming an etching groove on the surface of the semiconductor substrate located in the vicinity of the second transistor during the etching of the first conductive layer, the first transistor and the second transistor Impurity diffusion layers for source / drain regions are formed on the surface of the semiconductor substrate located between A step of forming an interlayer insulating layer on the first transistor and the second transistor, and a contact hole for exposing the surface of the source / drain region impurity diffusion layer in the interlayer insulating layer is formed in the etching groove. A method of manufacturing a semiconductor device having a floating gate, the step of forming the semiconductor device so that it does not overlap. 4. The method for manufacturing a semiconductor device having a floating gate according to claim 3, wherein the depth of the etching groove formed on the surface of the semiconductor substrate is 100 nm or more.