JP3214052B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device equipped with a mask ROM and having multilayer wiring.

[0002]

2. Description of the Related Art Integrated circuit devices having a mask ROM previously used only one layer of metal wiring. Therefore, the program for storing information in the ROM unit is RO
After forming a contact hole for the drain of the transistor in the M portion corresponding to the stored information, the contact hole is formed by patterning a metal wiring, and then an overcoat film is formed to complete the product.

However, recently, in order to increase the speed of an integrated circuit device on which a mask ROM is mounted, a multi-layer metal wiring has been used for a peripheral circuit portion thereof.
Conventionally, in such an integrated circuit device, the ROM layer program and the peripheral circuit section wiring are performed by the first layer metal wiring, and the upper layer of the peripheral circuit section is further layered by the second layer metal wiring. Wiring was done.

[0004]

However, as in the above-mentioned conventional integrated circuit device, the first integrated circuit device has a multi-layer wiring structure.
When the ROM section is programmed with the metal wiring of the layer, the TAT is long because patterning of the metal wiring of the second layer is required thereafter.

[0005]

In the integrated circuit device according to the present invention, the uppermost wiring 35 of the multilayer wirings 24 and 35 is provided.
A first contact hole 21 corresponding to the diffusion layer 15 in all the memory cells of the ROM portion is formed in the interlayer insulating films 16 and 17 of each layer disposed below (immediately) the wiring 24 immediately below. The wiring 24 of each layer disposed below the uppermost wiring 35 is patterned for each of the first contact holes 21, and an interlayer insulating film 25 covering the wiring 24 immediately below the first contact hole 21. , 26, 27,
31 , immediately above the first contact hole 21.
E) at the second position corresponding to the information stored in the ROM section.
The contact hole 32 is formed, the uppermost layer of the wiring 35 is Patani <br/> are in g to the second contact hole 32.

[0006]

In the integrated circuit device according to the present invention, the multilayer wiring 2
4 and 35, the wiring 24 of each layer disposed below the uppermost wiring 35 is the diffusion layer 15 and the wiring 3 of the uppermost layer.
5 is connected, and the program is executed by the wiring 35 in the uppermost layer. For this reason, the time from the start of the program to the completion of the product is shorter than in the case where the program is performed by the wiring 24 of the first layer.

In addition, since the wiring 24 of each layer is patterned for each of the first contact holes 21 formed in the interlayer insulating films 16 and 17 of each layer, any of the first and second contact holes is formed. It is sufficient that the layers 21 and 32 are formed so as to reach the diffusion layer 15 or the wiring 24 immediately below. Therefore, both contact holes 21 and 32 are shallow,
The wirings 24 and 35 have high step coverage. In addition, the second
The tact holes 32 are formed in the interlayer insulating films 25, 26, 27, 31.
And formed at a position immediately above the first contact hole 21.
Therefore, the program is executed in the uppermost wiring 35.
Despite this, the memory cell area has not increased.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to an integrated circuit device equipped with a mask ROM and having two-layer metal wiring will be described below with reference to FIG.

FIG. 1 shows a manufacturing process in a ROM section in the present embodiment. In order to manufacture the present embodiment, as shown in FIG.
After forming a well 12 of a conductivity type opposite to the conductivity type of the wafer 11, an SiO ₂ film 13 is formed in an element isolation region by a LOCOS method.

Thereafter, an SiO ₂ film 14 as a gate oxide film is formed on the surface of the element active region. Then, after depositing a polycrystalline Si film and doping the polycrystalline Si film with impurities, the polycrystalline Si film is patterned to form a gate electrode (not shown). However, the gate electrode may be formed of a polycide film or the like instead of the polycrystalline Si film.

Then, impurities are ion-implanted into the well 12 using the gate electrode, the SiO ₂ film 13 and the like as a mask.
A diffusion layer (not shown) as a source and a diffusion layer 15 as a drain are formed in the well 12. Then, a two-layered SiN / PSG film 16 and a BPSG film 17 are sequentially deposited, and these films are used as interlayer insulating films.

Next, as shown in FIG. 1B, contact holes 21 are formed in the BPSG film 17 and the like for the diffusion layers 15 in all the memory cells in the ROM section. Therefore, the contact hole 21 is opened irrespective of the storage information to be programmed. The opening of these contact holes 21 is
This is performed simultaneously with the opening of the contact hole (not shown) in the peripheral circuit portion.

Thereafter, the barrier metal film 22 and the Al film 23
Are sequentially deposited, and these films are patterned so as to be in contact with the diffusion layer 15 through the contact holes 21 to form the first-layer metal wiring 24 in both the ROM section and the peripheral circuit section. . However, in the peripheral circuit part, the metal wiring 2
4, an ordinary wiring is formed, but in the ROM portion, only a metal wiring 24 having an isolated pattern corresponding to each contact hole 21 is formed.

Next, as shown in FIG. 1C, the metal wiring 24 is covered with a P-TEOS film 25 which is an SiO ₂ film formed by plasma CVD using TEOS as a raw material. And
The SOG film 26 is spin-coated to flatten the surface.
A TEOS film 27 is deposited. The integrated circuit device of this embodiment is manufactured in this state. Therefore, P-TEO
The S films 25 and 27 and the SOG film 26 have a function as a surface protection film in addition to a function as an interlayer insulating film and a flattening film.

When program data, that is, storage information to be programmed is received from the user, a PSG film 31 is deposited on the P-TEOS film 27 as shown in FIG. Then, a contact hole 32 corresponding to the storage information to be programmed is formed in the PSG film 31 or the P-TEOS film 2 so as to reach the metal wiring 24 and directly above the contact hole 21.
Open 5 mag.

Therefore, unlike the contact hole 21, the contact hole 32 is selectively opened. For this reason, there is the metal wiring 24 in which the contact hole 32 is not opened and the P-TEOS film 25 or the like remains covered. The opening of the contact holes 32 is performed simultaneously with the opening of the contact holes (not shown) in the peripheral circuit portion. Further, the PSG film 31 in the contact hole 32 is subjected to taper etching.

Thereafter, the barrier metal film 33 and the Al film 34
Are sequentially deposited, and these films are patterned so as to be in contact with the metal wiring 24 through the contact holes 32, thereby forming the second-layer metal wiring 35 in both the ROM section and the peripheral circuit section. . Then, an overcoat film (not shown) is formed to complete the product.

In the integrated circuit device of the present embodiment completed as described above, since the contact hole 32 is formed immediately above the contact hole 21, programming is performed by the first-layer metal wiring. The memory cell area does not increase as compared with the conventional integrated circuit device.

In the above embodiment, the present invention is applied to an integrated circuit device having two-layer metal wiring.
The present invention can be applied to an integrated circuit device having three or more layers of metal wiring.

[0020]

In the integrated circuit device according to the present invention, since the time from the start of the program to the completion of the product is short, TA
Since T is short and the step coverage of the wiring is high, the disconnection of the wiring is small and the reliability is high. In addition, the top layer wiring
Memory cell area increases despite programming
Since it is not large, a decrease in the degree of integration is prevented.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 15 diffusion layer 16 SiN / PSG film 17 BPSG film 21 contact hole 24 metal wiring 25 P-TEOS film 26 SOG film 27 P-TEOS film 31 PSG film 32 contact hole 35 metal wiring

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 G11C 17/08 H01L 27/112

Claims (1)

(57) [Claims] 1. An integrated circuit device having a mask ROM mounted thereon and having a multi-layer wiring, wherein an interlayer insulating film of each layer disposed below a wiring immediately below an uppermost wiring of the multi-layer wiring. A first contact hole corresponding to a diffusion layer in all the memory cells of the ROM portion, wherein wirings of each layer disposed below the uppermost wiring are formed in each of the first contact holes. Of the interlayer insulating film covering the wiring immediately below the first core.
A position immediately above the Ntakuto hole, said being the second contact hole formed corresponding to the information stored in the ROM unit, the path <br/> Tanin grayed against the uppermost wiring said second contact hole has been that the integrated circuit device.