JP3285750B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring and a method of manufacturing the same, and more particularly to a process for connecting between an impurity diffusion layer of a semiconductor substrate and each wiring layer and between upper and lower wiring layers. And the measures to improve the reliability of the semiconductor device.

[0002]

2. Description of the Related Art In recent years, wiring structures for supplying signals to active elements such as transistors and passive elements such as resistors in a semiconductor device have become complicated in response to expansion of functions and higher integration of the semiconductor device. In general, a multilayer wiring structure has been used.
In a manufacturing process of a semiconductor device having a general multilayer wiring structure, after forming an element on a semiconductor substrate, wiring of each layer is sequentially formed thereon via an insulating film. In this case, in order to connect between each wiring layer and the element or each wiring layer, a connection hole (contact hole or via hole) is opened in the insulating film, and a metal for forming an upper layer wiring is formed in the connection hole. The plug is formed by depositing the same material or another material, and wirings and electrodes connected to the plug are formed. Hereinafter, DRA
A conventional method of forming a contact portion will be described with reference to FIGS. 6A to 6H, taking a manufacturing process of a MOS transistor formed in an M memory cell portion as an example.

First, in a step shown in FIG. 6A, a word line 105 is formed on a silicon substrate 101. However, 1
The word line 105 is formed across a number of active regions and element isolation between the active regions, and functions as a gate electrode on a gate insulating film on the active region. An upper surface protective film is formed on each gate electrode, and a sidewall and an isolation insulating film are formed on the sides of each gate electrode. FIG. 6A shows all of these insulating films as the silicon oxide film layer 104. Although not shown in FIG. 6A, a MOS transistor including a gate electrode and an impurity diffusion layer (source / drain region) formed in a silicon substrate is formed. Then, a first interlayer insulating film 106 made of a CVD silicon oxide film is formed on the silicon oxide film layer 104 thus formed.

Next, in a step shown in FIG. 6B, a portion of the first interlayer insulating film 106 and a part of the silicon oxide film layer 104 reaching the impurity diffusion layer of the silicon substrate 101 is formed by photolithography. One contact hole 107a is formed.

Next, in the step shown in FIG.
Tungsten is deposited on the entire surface of the substrate, a first plug 108a is formed in the first contact hole 107a, and at the same time, a tungsten film 10 is formed on the first interlayer insulating film 106.
9 is deposited, and a photoresist mask Fr is formed on the tungsten film 109.

Next, in a step shown in FIG. 6D, the tungsten film 109 is patterned using the photoresist mask Fr by a photolithography method, and a bit line 109a connected to the first plug 108a is formed. Form.

Next, in a step shown in FIG. 6E, a second interlayer insulating film 110 made of a silicon oxide film is deposited on the first interlayer insulating film 106 and the bit line 109a. , A second contact hole 107b reaching the impurity diffusion layer of the silicon substrate 101 is formed.

Next, in the step shown in FIG. 6 (f), tungsten silicide is deposited in the second contact hole 107b and on the second interlayer insulating film 110 to form the second plug 1
At the same time as forming 08b, a tungsten silicide film 112 is formed on the second interlayer insulating film 110.

Next, in a step shown in FIG. 6G, the tungsten silicide film 112 is patterned to form a charge storage electrode 112a connected to the second plug 108b. Further, a capacitor insulating film 113 made of a silicon nitride film and a silicon oxide film, and a plate electrode 114 made of a polysilicon film containing an n-type impurity are sequentially formed.

FIG. 6 (h) shows, in the step shown in FIG. 6 (g), not only the memory cell region Rmem but also the peripheral circuit region Rmem.
FIG. 3 is a diagram also showing a structure in per.

Although subsequent steps are omitted, an upper layer wiring and the like are further formed via a third interlayer insulating film and the like.

FIG. 7 is a sectional view of a conventional semiconductor device having a multilayer wiring structure. Elements such as MOS transistors 203 are formed on the silicon substrate 201 in the active region surrounded by the element isolation 202. On the silicon substrate 201, a thickness of 40
A first interlayer insulating film 204 having a thickness of about 0 to 500 nm is deposited, and a first layer wiring 205 is formed on the first interlayer insulating film 204.
Are formed. Also, the first interlayer insulating films 204 and 1
The second, third, and fourth interlayer insulating films 206, 210, and 213 are sequentially deposited on the layer wiring 205, and the second and third interlayer insulating films 206, 210, and 213 are respectively deposited on the interlayer insulating films 206, 210, and 213. Third and fourth wiring layers 209, 212, and 216 are formed. Then, the second layer wiring 209 and the first layer wiring 2
05 is a first plug 208 in which a conductive material is buried in a first contact hole 207a opened in the second interlayer insulating film 206. The second plug 211 formed by embedding a conductive material in the second contact hole 207b opened in the insulating film 206 and the third interlayer insulating film 210 allows the
The second-layer wiring 216 and the first-layer wiring 205 correspond to the second interlayer insulating film 206, the third interlayer insulating film 210, and the fourth interlayer insulating film 2.
13 are electrically connected to each other by third plugs 215 in which a conductive material is embedded in the third contact holes 207c opened. Although FIG. 7 shows all the contact holes 207a to 207c as if they were on the same cross section, actually, each of the three contact holes 207a to 207c is formed on the same cross section. is not.

Each of the interlayer insulating films 206, 210, 21
An example of the method of forming No. 3 is as follows. TEOS is deposited to a thickness of about 500 nm by a plasma CVD method.
TEOS is etched back by 100 nm by the r sputtering method, and TEOS is further deposited to about 1600 nm. Thereafter, a resist is deposited to a thickness of about 800 nm, an inverted pattern of the lower wiring is formed by photolithography, and a resist is deposited to a thickness of 1500 nm. Next, about 8 TEOS
The resist and the TEOS are etched back leaving 00 nm, and the interlayer insulating film is flattened. That is, in the end,
The thickness of the interlayer insulating film is about 800 nm.

[0014]

However, the above conventional manufacturing method has the following problems.

First, since the first contact hole 207a shown in FIG. 7 only penetrates the first interlayer insulating film 206, the first contact hole 207a is relatively shallow, about 800 nm. On the other hand, the second contact hole 207
Since b penetrates through the two interlayer insulators 206 and 210, the depth becomes about 1600 nm or more. In consideration of the thickness of the wiring layer, the depth may exceed 2 μm. In addition, the third
The contact hole 207c has three interlayer insulating films 206,
210, 213, the depth is 2400n
m or more. However, with the recent increase in the degree of integration of semiconductor devices, the diameter of the contact holes has to be reduced. When the diameter of the contact hole becomes, for example, about 0.5 to 0.6 μm, the aspect ratio (the value obtained by dividing the depth by the diameter) of the second and third contact holes 207b and 207c becomes a large value of 3 or more. . Therefore, when forming the plug, the so-called shadowing effect or the like tends to cause poor deposition of the wiring material in the contact hole, which causes voids, an increase in contact portion resistance, poor connection, etc., and deteriorates the reliability of the semiconductor device. There was a risk of causing it.

Second, since the absolute step H4 between the upper surface of the plate electrode 65a and the lower surface of the bit line 109a formed in the step shown in FIG. 6 (g) is large, patterning of the upper wiring in a later step is performed. Accuracy may be degraded or disconnection may occur. That is, as shown in FIG.
If the absolute step difference H4 is large, the slope in the step region Rst between the memory cell region Rmem and the peripheral circuit region Rper becomes steep, so that disconnection of the upper layer wiring is likely to occur, and the reliability may be deteriorated. Was.

Further, if an attempt is made to reduce the height of the charge storage electrode 112a in the memory cell region, it is necessary to increase the area of the charge storage electrode 112a, which hinders high integration of the semiconductor device. Therefore, the charge storage electrode 11
Due to the restriction due to the shape of 2a, there is a problem that the degree of freedom in designing the memory cell portion of the DRAM cannot be sufficiently secured.

The present invention has been made in view of the above points, and a first object is to form a connection hole for connecting between a wiring layer and a semiconductor substrate or connecting each wiring layer. Even for connection holes that connect distant layers, by taking measures to reduce the aspect ratio as much as possible,
An object of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof.

A second object of the present invention is to provide a semiconductor device having a high degree of design freedom and high reliability by taking measures to reduce a step between a bit line and a charge storage electrode in a memory cell portion of a DRAM. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

[0020]

The first method for fabricating a semiconductor device SUMMARY OF THE INVENTION The present invention comprises a first step of forming a first and second lower side conductive member on a semi-conductor substrate, the first And a second step of forming a first insulating film on the second lower conductive member, and opening a part of the first insulating film to form the first and second lower conductive members. Forming a first and a second connection hole reaching the conductive member, respectively, and depositing a conductive material in the first and the second connection hole to form a first and a second buried layer. Forming a first conductive film and a second insulating film on the first and second buried layers and the first insulating film, and then forming the first conductive film on the first conductive film and the second insulating film. Patterning the film and the second insulating film so as to belong to the wiring layer above the lower conductive member and to form the first buried layer; While forming the first upper conductive member and an upper surface protective film which is connected to the layer, a fifth step of exposing the top surface of said second buried layer, said first
A sixth step of forming a sidewall on the side surface of the upper conductive member and the upper protective film, and the first insulating film, the sidewall, the upper protective film, and the second protective film.
After depositing a second conductive film on the buried layer of
Forming a second upper-layer conductive member belonging to a wiring layer further above the first upper-layer conductive member and connected to the second buried layer by patterning the conductive film of No. 7; And the third step is the third step.
When the diameter of the first and second connection holes is 0.6 μm or less,
The operation is performed so that the ratio becomes 3 or less.

According to this method, the first connection hole connecting the first upper layer conductive member and the first lower layer conductive member, the second upper layer conductive member and the second lower layer side are provided. Another second insulating film is formed on the first insulating film as in the related art, in that the second connecting hole for connecting the conductive member and the second connecting hole are formed simultaneously and in the common first insulating film. And then forming the second connection hole. As described above, since the first and second connection holes are formed at the same time, the number of masks and the number of steps for forming the connection holes are reduced as compared with a method in which connection holes are individually formed for different wiring layers. And the manufacturing cost is reduced. In addition, since the second connection hole is formed in the first insulating film common to the first connection hole, the second connection hole is formed between the first insulating film and the other insulating film as in the related art. As compared with the case where the second connection hole is formed, the aspect ratio of the second connection hole can be reduced even when the diameter of the second connection hole needs to be reduced due to high integration. When the aspect ratio is reduced, the state of deposition of the conductive material during the formation of the second buried layer is improved, and electrical connection failure in the second buried layer can be prevented. On the other hand, the first and second upper conductive members are separated and insulated in a self-aligned manner by the sidewalls, so that there is no possibility of causing a short circuit. Therefore, it is easy to manufacture a highly reliable semiconductor device having a multilayer wiring structure.

The first and second lower conductive members are
The first and second impurities on the semiconductor substrate may be formed in the same wiring layer electrically connected to the semiconductor substrate, or in the same wiring layer electrically insulated from the semiconductor substrate. It may be a diffusion layer.

In the first step, a third impurity diffusion layer is further formed on the semiconductor substrate. In the third step, the third lower conductive layer is formed on a part of the first insulating film. Forming a third connection hole reaching the conductive member simultaneously with the first and second connection holes, and in the fourth step,
The first conductive material is also deposited in the third connection hole to form a third buried layer, and in one of the fifth step and the seventh step, the third Forming an intermediate conductive member connected to the buried layer, depositing an interlayer insulating film over the entire surface of the substrate after the seventh step, flattening the interlayer insulating film, Forming a fourth connection hole reaching the intermediate conductive member in a part of the interlayer insulating film; and forming a fourth buried layer by depositing a conductive material in the fourth connection hole. And depositing a third conductive film on the fourth buried layer and the interlayer insulating film, and then patterning the third conductive film to form a further upper wiring of the second upper conductive member. Belonging to the fourth layer
Forming a third upper-layer-side conductive member connected to the buried layer.

According to this method, the connection holes for connecting the third upper conductive member belonging to the uppermost wiring layer and the third lower conductive member are formed in the third and fourth connection holes. Since the two insulating films are separately formed, the aspect ratio of each connection hole can be suppressed to a small value, and particularly, the manufacture of a semiconductor device having three or more multilayer wirings is facilitated.

[0025] In the above SL first step, further forming a third impurity diffusion layer on the semiconductor substrate, in the third step, the lower side portion to the third of the first insulating film A third connection hole reaching the conductive member is formed simultaneously with the first and second connection holes, and in the fourth step,
The conductive material is also deposited in the third connection hole to form a third buried layer. In the fifth step, the surface of the third buried layer is exposed, and in the seventh step, After further depositing a third insulating film on the second conductive film, the second conductive film and the third insulating film are simultaneously patterned, and the upper surface of the third buried layer is exposed. Forming a second sidewall on the side surface of the second upper conductive member and the third insulating film after the seventh step;
Depositing a third conductive film on the insulating film, the third buried layer, the third insulating film, and the second sidewall, and then patterning the third conductive film to form the second conductive film. Forming a third upper conductive member belonging to a wiring layer further above the upper conductive member and connected to the third buried layer.

According to this method, the first to third connection holes for connecting the first to third upper conductive members belonging to three different wiring layers and the three lower conductive members of the lower layer, respectively. Are formed simultaneously and at the same depth. Therefore, the above-described operation is more remarkably obtained.

According to a second method of manufacturing a semiconductor device of the present invention ,
In a method of manufacturing a semiconductor device functioning as a DRAM, a first step of forming a transistor including a gate electrode and first and second impurity diffusion layers at least on a semiconductor substrate in a memory cell region; And a second step of depositing a first insulating film on the gate electrode.
And the first and second portions of the first insulating film reaching the first and second impurity diffusion layers, respectively.
A third step of forming a first contact hole, a fourth step of depositing a conductive material in the first and second contact holes to form first and second buried layers, After sequentially depositing a first conductive film and a second insulating film on the first insulating film and the respective buried layers, the first conductive film and the second insulating film are patterned to form the first conductive film and the second insulating film. Forming a bit line connected to the buried layer and a bit line upper protective film while exposing the upper surface of the second buried layer; and forming a fifth step on the side surfaces of the bit line and the bit line upper protective film. A sixth step of forming sidewalls;
After depositing a second conductive film on the first insulating film, the sidewalls, the bit line upper surface protective film, and the second burying layer, the second conductive film is patterned to form the second conductive film. Forming a charge storage electrode connected to the second buried layer; and forming a second charge storage electrode on the charge storage electrode, the first insulating film, the sidewall, and the bit line upper surface protection film. After depositing the insulating film and the third conductive film,
An eighth step of patterning the second insulating film and the third conductive film to form a capacitive insulating film and a plate electrode , wherein the first step includes:
Forming a third impurity diffusion layer in the peripheral circuit region of
In the third step, the third insulating film is formed on a part of the first insulating film.
The third connection hole reaching the impurity diffusion layer of
Formed simultaneously with the second connection hole, and in the fourth step,
Deposits the conductive material also in the third connection hole,
3 is formed, and in the fifth step,
The bit line connected to the third buried layer and on the bit line
A surface protection film is formed.

According to this method, the second connection hole for connecting the charge storage electrode and the impurity diffusion layer is formed simultaneously with the first connection hole for connecting the bit line and the impurity diffusion layer. In addition, the number of masks for forming the connection holes and the number of steps are reduced, and the manufacturing cost is reduced. Further, since the lower end of the charge storage electrode and the lower end of the bit line are at the same height, even if the height dimension of the charge storage electrode is increased, the step of the entire substrate does not increase so much. Therefore, the degree of freedom in designing the height dimension and the lateral dimension of the charge storage electrode is increased.

[0029] Then, the inclination of the stepped region between the memory cell region and the peripheral circuit region of the D RAM becomes smooth, reduced probability of disconnection of the uppermost layer of the wiring occurs, the reliability is improved.

[0030] The third step, the first and second
It is preferable that the diameter of the connection hole is 0.6 μm or less and the aspect ratio is 3 or less.

The semi-conductor device of the present invention includes a semiconductor substrate, a first and second lower side conductive member formed on the semiconductor substrate, on the first and second lower side conductive member A first insulating film formed on the first insulating film, first and second connection holes opened in a part of the first insulating film and reaching the first and second lower conductive members, respectively; First and second conductive materials deposited in the first and second connection holes.
Embedded layer, a first upper-layer conductive member belonging to a wiring layer above the lower-layer conductive member and connected to the first buried layer, and a first upper-layer conductive member. An upper surface protective film formed on the upper surface and made of an insulating material;
And a sidewall formed on the side surface of the upper conductive member and the upper surface protective film and made of an insulating material; and a second wiring layer belonging to a wiring layer further above the first upper conductive member.
And a second upper layer conductive member that is in contact with the upper surface of the buried layer, wherein the diameter of the first and second connection holes is 0.6 μm.
Below, the aspect ratio is 3 or less .

According to this structure, the depth of the second connection hole becomes equal to the depth of the first connection hole, so that the aspect ratio of the second connection hole becomes smaller than that of the conventional multilayer wiring structure. By such an action, the reliability of the semiconductor device is improved.

[0033] The upper Symbol first and second lower side conductive member D
An impurity diffusion layer on both sides of a gate of a transistor formed in a memory cell region of a RAM, the first upper conductive member is a bit line of the DRAM, and the second upper conductive member is a DRAM of the DRAM. It can be a charge storage electrode.

According to this structure, the height position of the lower end of the charge storage electrode is equal to the height position of the lower end of the bit line. Therefore, even if the height dimension of the charge storage electrode is increased, the level difference of the entire substrate can be significantly increased. Absent. Therefore, the degree of freedom in designing the height dimension and the lateral dimension of the charge storage electrode is increased.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A semiconductor device according to a first embodiment and a method for manufacturing the same will be described below with reference to FIGS.

First, in the step shown in FIG. 1A, a detailed description of the procedure is omitted, but the single-crystal silicon substrate 1 is prepared in advance.
A first interlayer insulating film 2 made of a silicon oxide film is formed thereon, and a contact hole 3 reaching an impurity diffusion layer (not shown) of a silicon substrate is formed in a part of the first interlayer insulating film 2.
Are formed. In addition, tungsten 1 connected to the silicon substrate 1 through the contact hole 3
The layer wiring 4 is formed. In the present embodiment, this 1
The first and second wiring layers 4 are formed on the semiconductor substrate.
This is a case where the first and second lower conductive members are formed of a common member. Then, a thickness of 800 nm is formed on the first layer wiring 4 by the method described for the conventional semiconductor device shown in FIG.
A second interlayer insulating film 5 of about m silicon oxide film is formed.

In the step shown in FIG. 1B, the first layer wiring and the second layer wiring are formed on a part of the second interlayer insulating film 5 by photolithography using the same photoresist mask. First contact hole 7a for forming a contact portion between
And a second contact hole 7b for forming a contact portion between the first-layer wiring and the third-layer wiring are simultaneously opened.

In the step shown in FIG. 1C, tungsten is deposited on the entire surface of the substrate by the CVD method. That is,
The first and second plugs 8a and 8b are formed by filling the first and second contact holes 7a and 7b with tungsten, and a first conductive film is formed on the plugs 8a and 8b and the second interlayer insulating film 5 at the same time. A certain tungsten film 9 is formed. Further, a silicon oxide film 10 is deposited on the tungsten film 9, and a photoresist mask Fr1 is formed on the silicon oxide film 10 to cover the first plug 8a and its surrounding area.

In the step shown in FIG. 1D, the silicon oxide film 10 and the tungsten film 9 are patterned by using a photoresist mask Fr1 to form a first upper conductive member connected to the first plug 8a. Is formed, and the second plug 8b is left in the second contact hole 7b while forming the second-layer wiring 9a and the upper surface protection film 10a.
The upper surface of b is exposed.

In the step shown in FIG. 1E, a silicon oxide film 14 for forming a sidewall is deposited on the entire surface of the substrate by the CVD method.

In the step shown in FIG. 1F, the silicon oxide film 14 is etched back by anisotropic etching to expose the surface of the second plug 8b, and at the same time, the second-layer wiring 9a and the upper protective film 10a. Side wall 1 on the side of
4a is formed.

In the step shown in FIG. 1 (g), a tungsten film as a second conductive film is deposited on the entire surface of the substrate by the CVD method, and the second film connected to the second plug 8b is formed by the photolithography method. A third-layer wiring 17a, which is an upper-layer-side conductive member, is formed.

Although the subsequent steps are omitted, for example, a silicon oxide film is deposited on the third-layer wiring 17a, and an interlayer insulating film is deposited and planarized as described for the semiconductor device shown in FIG. By utilizing this, it is possible to further form an upper interlayer insulating film and a wiring. Such processing is similarly applied to each embodiment described later.

In the step shown in FIG. 1C, first, tungsten is deposited in the first and second contact holes 7a and 7b by the selective CVD method, and the first and second plugs 8 are formed.
After forming a and 8b, a tungsten film 9 may be deposited thereon by sputtering or the like.

As shown in FIG. 1 (g), the semiconductor device formed by the manufacturing method of the present embodiment has first and second semiconductor devices.
Are connected to the first conductive layer 4 by a common first-layer wiring 4.
The upper conductive member on the upper layer is constituted by the second-layer wiring 9a, and the second conductive member on the upper layer is constituted by the third-layer wiring 17a. The second-layer wiring 9a and the first-layer wiring 4 are connected to the third-layer wiring 17a and the first-layer wiring 17a through a first plug 8a in which tungsten is buried in the first contact hole 7a.
The second wiring 4 is connected to the second wiring 4 via a second plug 8a in which tungsten is embedded in the second contact hole 7b. In this case, the first and second contact holes 7a and 7b are formed by simultaneously opening the same second interlayer insulating film 5. That is, as before,
Instead of separately forming contact holes for connecting the third-layer wiring and the first-layer wiring and contact holes for connecting the second-layer wiring and the first-layer wiring, FIG. As shown in b), both contact holes 7a, 7b
Are formed in a single photolithography process using the same mask, so that the number of contact hole opening masks can be reduced, and the photolithography and etching processes for contact hole opening can be reduced. .

Moreover, the third layer wiring 17a and the first layer wiring 4
Is the same as the depth of the first contact hole 7a for connecting the second-layer wiring 9a and the first-layer wiring 4 to each other. As described above, in the conventional manufacturing method, for example, the contact hole connecting the third-layer wiring and the first-layer wiring penetrates the two interlayer insulating films, so that the contact hole has a large depth. When the diameter of the contact hole is reduced due to integration, the aspect ratio increases, and there is a possibility that a defect such as a connection failure may be caused. On the other hand, in the manufacturing method of the present embodiment, the depth of the second contact hole 7b is only required to be equal to the thickness of the second interlayer insulating film 5, and even when the diameter of the contact hole is reduced, the aspect ratio is increased. Nothing. For example, if the diameter of the contact hole is 0.4 to 0.6 μm
m, the thickness of the second interlayer insulating film 5 is 1.8 μm.
m (usually about 800 nm), and the aspect ratio becomes 3 or less. Therefore, it is possible to effectively prevent a failure such as a connection failure due to a deposition failure of a member constituting the plug, and to provide a highly reliable semiconductor device.

The depth of the second contact hole 7b for connecting the third-layer wiring 17a and the first-layer wiring 4 is reduced, so that the second contact hole 7b is opened when the second contact hole 7b is opened. , The horizontal position shift between the upper end and the lower end is reduced. Therefore, even when the pattern of the first-layer wiring 4 is fine, a connection failure between the third-layer wiring 17a and the first-layer wiring 4 due to the displacement of the opening position of the second contact hole 7b is possible. Can be prevented.

Furthermore, in the present embodiment, the first and second plugs 8a and 8b all reach the same first-layer wiring 4, but the first-layer wiring to which the plugs 8a and 8b are connected is connected. May be electrically separated and insulated from each other. In particular, in such a case, when forming the second contact hole for connecting the third-layer wiring and the first-layer wiring, not only the alignment between the second contact hole and the first-layer wiring is taken into consideration, but also the second contact hole is formed. It is necessary to consider that the second contact hole does not interfere with the plug connecting between the second layer wiring and the first layer wiring. In this case, in the conventional method of individually forming the first and second contact holes, there is a possibility that a short circuit may occur due to a positional shift between the masks for forming the contact holes. On the other hand, in the present embodiment, since the contact holes 7a and 7b are formed simultaneously using the same photoresist mask, no interference occurs due to mask displacement between the plugs 8a and 8b. On the other hand, the third-layer wiring 17a and the second-layer wiring 9a are
4a separates and insulates in cell alignment.
As described above, in the semiconductor device formed by the manufacturing method of the present embodiment, the separation and insulation between the members that should not be electrically connected is reliably performed, and the reliability is also improved.

In the first embodiment, the first contact hole 7a is a contact hole connecting the first-layer wiring 4 and the second-layer wiring 9a, but the first contact hole 7a is formed in the silicon substrate 1. It may be a contact hole for connecting the impurity diffusion layer and the second-layer wiring 9a. Similarly, the second contact hole 7b may be a contact hole for connecting the impurity diffusion layer in the silicon substrate 1 and the third-layer wiring 17a.

Further, the first layer wiring 4, the second layer wiring 9a,
Although the third layer wiring 17a and each of the plugs 8a and 8b are made of tungsten, the same effect can be exerted even if each member is made of aluminum, molybdenum or copper.

Second Embodiment Next, a method of manufacturing a semiconductor device according to a second embodiment will be described with reference to FIGS.

The steps shown in FIGS. 2A to 2G are basically the same as the steps shown in FIGS. 1A to 1G. However, in the present embodiment, in the process shown in FIG.
The contact hole 3 for connecting the first layer wiring 4 and the semiconductor substrate as shown in FIG. And
The first layer wiring 4 is separated into two parts 4a and 4b.

Then, in the step shown in FIG. 2B, the first and second contact holes 7a, 7b are formed so as to reach the respective portions 4a, 4b of the first-layer wiring.

The following steps are the same as in the first embodiment, and a description thereof will be omitted.

Finally, in the semiconductor device formed by the manufacturing method of this embodiment, as shown in FIG. 2 (g), the second-layer wiring 9a and the member 4a of the first-layer wiring 4 Connected via a plug 8a, the third-layer wirings 17a and 1
The member 4b of the layer wiring 4 is connected via the second plug 8b. Further, the respective members 4a and 4b of the first layer wiring are not connected to the impurity diffusion layers in the silicon substrate 1. Such a first-layer wiring may be necessary in layout, but in such a case, the same effect as in the first embodiment can be obtained.

In this embodiment, as in the first embodiment, the first layer wiring 4, the second layer wiring 9a,
Although the layer wiring 17a and each of the plugs 8a and 8b are made of tungsten, the same effect can be obtained even if each member is made of aluminum, molybdenum, or copper.

Third Embodiment Next, a semiconductor device according to a third embodiment and a method for manufacturing the same will be described with reference to FIGS.

First, in a step shown in FIG. 3A, a first interlayer insulating film 22 made of a silicon oxide film is deposited on a single crystal silicon substrate 21. After that, the first interlayer insulating film 22
A photoresist mask (not shown) is formed on the substrate, and using this photoresist mask,
Three contact holes 27a, 2 reaching the three impurity diffusion layers of the silicon substrate in a part of the first interlayer insulating film 22
7b and 27c are simultaneously opened. Although not shown, each impurity diffusion layer is formed at an individual position near the surface of the silicon substrate 21 and is electrically insulated from each other. In the present embodiment, each impurity diffusion layer in the silicon substrate 21 is the first to third lower conductive members formed on the semiconductor substrate.

In the step shown in FIG. 3B, first, the CVD
Tungsten is deposited on the entire surface of the substrate by a method. That is, the first to third plugs 28a to 28c are formed by filling the first to third contact holes 27a to 27c with tungsten, and at the same time, the first conductive film is formed on the plugs 28a to 28c and the first interlayer insulating film 22. A tungsten film 29 as a film is formed. Further, a silicon oxide film 30 is deposited on the tungsten film 29, and a photoresist mask Fr2 is formed on the silicon oxide film 30 to cover the first plug 28a and its surrounding area.

In the step shown in FIG. 3C, the silicon oxide film 30 and the tungsten film 29 are patterned by using a photoresist mask Fr2 to form a first upper conductive member connected to the first plug 28a. First layer wiring 2
9a and the upper surface protection film 30a, and each plug 28 in the second and third contact holes 27b and 27c.
b, 28c, leaving the second and third plugs 28b, 28c
To expose the upper surface of the

In the step shown in FIG. 3D, a silicon oxide film 34 for forming a sidewall is deposited on the entire surface of the substrate by the CVD method.

In the step shown in FIG. 3E, the silicon oxide film 34 is etched back by anisotropic etching to expose the surfaces of the second and third plugs 28b and 28c, and at the same time, the first layer wiring 29a is formed. Then, a sidewall 34a is formed on the side surface of the upper surface protective film 30a.

In the step shown in FIG. 3F, a tungsten film 3 as a second conductive film is formed on the entire surface of the substrate by a CVD method.
7 is deposited.

In the step shown in FIG. 3G, first, the tungsten film 37 is patterned by photolithography.
A third-layer wiring 37a as a second upper-layer conductive member connected to the second plug 28b and an intermediate wiring 37b as an intermediate conductive member connected to the third plug 28c are formed. Then, a second interlayer insulating film 38 made of a silicon oxide film (BPSG film) doped with boron and phosphorus is deposited on the entire surface of the substrate.

In the step shown in FIG. 3H, after the second interlayer insulating film 38 is reflowed and flattened, the intermediate wiring 37b on the third plug 28c is partially added to the second interlayer insulating film 38.
Is formed.

In the step shown in FIG. 3I, tungsten is deposited on the entire surface of the substrate to form a fourth plug 40 in which tungsten is buried in the fourth contact hole 39, and at the same time, the second interlayer insulating film 38 is formed. A tungsten film 41, which is a third conductive film, is formed thereon.

In the step shown in FIG. 3 (j), the tungsten film 41 is patterned to form the silicon substrate 21 through the fourth plug 40, the intermediate wiring 37b and the third plug 28c.
A third-layer wiring 41a connected to the impurity diffusion layer (third lower conductive member) is formed.

Also in this embodiment, the first-layer wiring 29a
A first contact hole 27a for connecting the (first upper conductive member) and the impurity diffusion layer (first lower conductive member) on the silicon substrate 21, and a second wiring 37a
The second contact hole 27b for connecting the (second upper conductive member) and the impurity diffusion layer (second lower conductive member) on the silicon substrate 21 is made the same by photolithography. Since the openings are formed simultaneously using the mask, the number of masks for opening the contact holes can be reduced, and the photolithography process for opening the contact holes can be reduced.

In addition, in the present embodiment, the second layer wiring 37
The intermediate wiring 37b connected to the third plug 28c is formed in the same wiring layer as the wiring a, and the third wiring 41a (third upper conductive member) and the impurity diffusion layer (the 3 lower conductive member) and the third plug 28
c, via the intermediate wiring 37b and the fourth plug 40. In other words, a contact hole for connecting the third-layer wiring 41a and the impurity diffusion layer on the silicon substrate 21 is opened separately into the third contact hole 27c and the fourth contact hole 39. Therefore, an increase in the aspect ratio unlike the case where the first and second interlayer insulating films 22 and 38 are simultaneously opened is not caused, and a connection failure due to a deposition failure of tungsten or the like can be effectively prevented. In particular, the reliability can be improved even in a semiconductor device having a multilayer wiring structure of three or more layers.

In the third embodiment, the intermediate wiring 37b may be formed simultaneously with the formation of the first-layer wiring 29a. In this case, the upper surface protective film and the side wall are also formed at the same time, but the upper portion is further covered by the second interlayer insulating film 38, so that there is basically no difference from the manufacturing process of the present embodiment.

The wirings 29a, 37a, 37b, 4
The plug 1a and each of the plugs 28a to 28c, 40 may be made of aluminum, molybdenum, or copper instead of tungsten in the present embodiment.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIGS.

In this embodiment, three impurity diffusion layers as first to third lower conductive members are formed on the silicon substrate 21 as in the third embodiment. Then, in the steps shown in FIGS. 4A to 4E, the same processing as the steps shown in FIGS. 3A to 3E already described is performed.

Thereafter, in a step shown in FIG. 4F, a tungsten film 37 and a silicon oxide film 45 are sequentially deposited on the entire surface of the substrate.

Next, in the step shown in FIG. 4G, the tungsten film 37 and the silicon oxide film 45 are patterned to form a second-layer wiring 37a connected to the second plug 28b and an upper surface protection film 45a. At the same time as forming, the third plug 2
8c is exposed.

Next, in a step shown in FIG. 4H, a silicon oxide film for sidewall formation (not shown) is deposited on the entire surface of the substrate, and this silicon oxide film is etched back to form a second layer. A sidewall 46a is formed on a side surface between the wiring 37a and the upper surface protection film 45a. At this time, the upper surface of the third plug 28c is exposed.

Next, in a step shown in FIG. 4I, a tungsten film 47 is deposited on the entire surface of the substrate, and in a step shown in FIG.
A third-layer wiring 47a connected to the plug 28c is formed.

In the present embodiment, the step of forming the fourth contact hole 39 shown in FIG. 3H is not required as compared with the third embodiment, and the number of masks can be further reduced.
The photolithography process can be reduced.

The third wiring 47a (third upper conductive member) and the impurity diffusion layer (third upper layer) on the silicon substrate 21 are formed.
(The lower conductive member) is connected only through the third plug 28c, so that the reliability is further improved for the above-described reason.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIGS. 5 (a) to 5 (g) show the DR
The sectional shape is displayed separately for the AM memory cell region Rmem and the peripheral circuit region Rper.

First, in the step shown in FIG. 5A, a word line made of a polysilicon film containing an n-type impurity having a thickness of about 250 nm is formed on a silicon substrate 51 via a gate oxide film having a thickness of about 10 nm. 55 are formed. However, 1
The word line 55 is formed over a number of active regions and element isolation between the active regions, and functions as a gate electrode on a gate insulating film on the active region.
In addition, an upper surface protective film is formed on each gate electrode,
Side walls and isolation insulating films are formed on the sides of each gate electrode. In FIG. 5A, all of these insulating films are shown as silicon oxide film layers 54. Although not shown in FIG. 5A, a MOS transistor including a gate electrode and an impurity diffusion layer (source / drain region) formed in a silicon substrate is formed. Then, the silicon oxide film layer 5 thus formed is formed.
A first interlayer insulating film 56 made of a CVD silicon oxide film having a thickness of about 500 nm is formed on the substrate 4.

Next, in a step shown in FIG. 5B, a memory cell region is formed in a part of the first interlayer insulating film 56 and the silicon oxide film layer 54 by photolithography using the same photoresist mask. First and second contact holes 57a and 57b having a diameter of about 0.3 to 0.4 μm reaching two impurity diffusion layers (first and second lower conductive members) of the silicon substrate 51 in Rmem; , Peripheral circuit region Rper
And a third contact hole 57c having a diameter of about 0.3 to 0.4 μm reaching the impurity diffusion layer (third lower conductive member) on the silicon substrate 51 in FIG.

Next, in the step shown in FIG.
In the first to third contact holes 57a to 57c and in the first
Polysilicon containing n-type impurities and tungsten silicide are deposited on the interlayer insulating film 56, and first to third plugs 58a are formed in the first to third contact holes 57a to 57c.
At the same time as forming the layers 58c, a laminated film 59 (first conductive film) having a thickness of about 200 to 300 nm is deposited on the first interlayer insulating film 56. Further, a silicon oxide film 60 having a thickness of about 300 to 400 nm is deposited on the laminated film 59, and a photoresist covering the first and third contact holes 57a and 57c and its peripheral region is formed on the silicon oxide film 60. The masks Fr3 and Fr4 are formed.

Next, in the step shown in FIG. 5D, the silicon oxide film 60 and the laminated film 59 are patterned by the photo-etching method using the above-mentioned photoresist masks Fr3 and Fr4. Bit line 59a (first upper conductive member) and upper protective film 60a connected to first plug 58a, and bit line 59b and upper protective film 6 connected to third plug 58c in peripheral circuit region Rper.
0b. At this time, the laminated film 59 on the second plug 58b and the surrounding first interlayer insulating film 56 is removed, and the upper surface of the second plug 58b is exposed.

Next, in the step shown in FIG. 5E, after depositing a silicon oxide film on the entire surface of the substrate, this silicon oxide film is etched back to form each bit line 59a, 59b and each upper surface protective film. Sidewalls 64a and 64b are formed on the side surfaces of 60a and 60b, respectively.

Next, in a step shown in FIG. 5F, a tungsten silicide film 65 is formed on the entire surface of the substrate. After that, a photoresist mask Fr5 is formed on the tungsten silicide film 65 to cover the second plug 58b and its surroundings.

Next, in the step shown in FIG. 5 (g), the tungsten silicide film 65 is patterned using a photoresist mask Fr5, so that the charge stored in the thickness connected to the second plug 58b is about 500 to 600 nm. Electrode 65
a is formed. Thereafter, a capacitance insulating film 66 made of a silicon nitride film and a silicon oxide film, and a plate electrode 67 made of a polysilicon film containing an n-type impurity and having a thickness of about 100 to 200 nm are sequentially formed.

Although subsequent steps are omitted, an upper layer wiring and the like are further formed via a third interlayer insulating film and the like.

In the manufacturing method of this embodiment, the first and third contact holes 57 for connecting the bit lines 59a and 59b to the impurity diffusion layers on the silicon substrate 51 are also provided.
a, 57c, and a second connection between the charge storage electrode 65a of the memory cell and the impurity diffusion layer on the silicon substrate 51.
Since the contact holes 57b are simultaneously opened by the photolithography method using the same photoresist mask, the number of masks for opening the contact holes is reduced, and the photolithography process for opening the contact holes is reduced. It becomes possible.

In addition, the following advantages can be obtained as compared with the conventional manufacturing method shown in FIGS. 6 (a) to 6 (h).

First, in the conventional manufacturing method, the depth of the second contact hole 107b for connecting the charge storage electrode 112a and the impurity diffusion layer of the silicon substrate 101 is
As shown in FIG. 6E, the total thickness of the silicon oxide film layer 104, the first interlayer insulating film 106, and the second interlayer insulating film 110 is H2 (about 2 μm in depth). Has a value H1 (about 1.5 to 1.6 microns in depth) equal to the sum of the thicknesses of the silicon oxide film layer 54 and the first interlayer insulating film 56. That is, in the present embodiment, compared to the conventional manufacturing method,
The second contact hole 57b becomes shallower by the thickness of the second interlayer insulating film 110 shown in FIG. Therefore, the aspect ratio of the second contact hole 57b is reduced,
A connection failure or the like of a semiconductor device manufactured by the manufacturing method of the present embodiment can be effectively prevented, and reliability can be improved.

Second, as shown in FIG. 5G, the difference in height between the upper surface of the plate electrode 114 in the memory cell region Rmem and the lower surface of the bit line 59 in the peripheral circuit region Rper, that is, the so-called absolute The level difference H3 is smaller than the absolute level difference H4 in the conventional DRAM shown in FIG.
This is because, in the present embodiment, the lower ends of the charge storage electrode 65a and the bit line 59 are at the same height position (on the first interlayer insulating film 56). FIGS. 8A and 8B are diagrams comparing the structure of the conventional DRAM having the absolute step H4 and the structure of the DRAM according to the present embodiment having the absolute step H3. In the conventional DRAM, there is a problem that the upper wiring is easily disconnected due to the steep inclination in the step region Rst between the memory cell region Rmem and the peripheral circuit region Rper. However, in the DRAM of this embodiment, Since the slope in the step region Rst becomes gentle, the probability of occurrence of disconnection of the upper layer wiring becomes extremely small. That is, the reliability can be improved.

Further, even if the thickness of the charge storage electrode 65a is increased, an increase in the level difference of the entire substrate is suppressed, so that there is a margin for changing the shape of the charge storage electrode 65a according to the type and structure of the semiconductor device, that is, design. The degree of freedom is increased. That is, it is possible to sufficiently cope with high integration of a semiconductor device.

(Other Embodiments) In the fifth embodiment, the word line 55 is formed of a polysilicon film containing an n-type impurity.
Monolayer films such as molybdenum film, tungsten film, titanium film, platinum film, molybdenum silicide film, titanium silicide film, platinum silicide film, etc., and molybdenum silicide film, titanium silicide film or platinum silicide film and polysilicon film containing n-type impurity And a laminated film of the above.

The plugs 58a to 58c and the bit lines 59a and 59b are formed of a laminated film of polysilicon containing n-type impurities and tungsten silicide, but a polysilicon film containing n-type impurities, a tungsten film, a molybdenum Film, a titanium film, a platinum film, a molybdenum silicide film, a titanium silicide film, a single layer film such as a platinum silicide film, or a laminated film of a molybdenum silicide film, a titanium silicide film or a platinum silicide film and a polysilicon film containing an n-type impurity. May be configured.

Although the charge storage electrode 65a is formed of a tungsten silicide film, a single-layer film such as a polysilicon film containing an n-type impurity, a titanium silicide film, a molybdenum silicide film, tungsten, or a poly-silicon film containing an n-type impurity is used. It may be composed of a laminated film of a silicon film, a platinum film and a tantalum film.

The capacitor insulating film 66 is formed of a laminated film of a silicon nitride film and a silicon oxide film. However, a tantalum oxide film, a strontium titanate film, a strontium titanate film to which barium is added, a lead, zirconium and titanium A single-layer film such as an oxide (PZT) film containing oxygen, an oxide (PLZT) film containing lead, lanthanum, zirconium, and titanium;
It may be composed of a laminated film of a tantalum oxide film and a silicon oxide film.

Further, the plate electrode 67 is formed of a polysilicon film containing an n-type impurity, but may be formed of a titanium nitride film, a tungsten film, a tungsten silicide film, a molybdenum film, a molybdenum silicide film, or the like.

The first and second lower conductive members of the present invention do not have to be at exactly the same height. For example, when the first lower-layer conductive member is a gate electrode of a MOS transistor and the second lower-layer conductive member is a source / drain lead electrode of a MOS transistor, the height positions of both are substantially the same. Since they are equal, the same effects as in the above embodiments can be exerted. In this case, the gate electrode serving as the first lower conductive member is not connected to the impurity diffusion layer of the semiconductor substrate, and the lead electrode serving as the second lower conductive member is connected to the impurity diffusion layer of the semiconductor substrate. Although connected, the present invention can be realized in such a form.

[0100]

According to the first method of manufacturing a semiconductor device of the present invention,
According to this, the first and second connection holes reaching the first and second lower conductive members are opened in the common first insulating film, and the first and second buried layers are formed in the respective connection holes. After forming the first buried layer, a first upper conductive member, an upper surface protective film, and a side wall connected to the second buried layer are formed in a state where the first buried layer is exposed. Since the second upper conductive member connected to the second buried layer is formed, the number of masks and the number of steps for forming each connection hole can be reduced while having a multilayer wiring structure. It is possible to reduce the manufacturing cost and manufacture a highly reliable semiconductor device by preventing electrical connection failure and short circuit.

According to the second method for manufacturing a semiconductor device of the present invention,
Then, when the bit line and the charge storage electrode of the DRAM are formed, the same steps as those for forming the first and second upper conductive members according to claim 1 and the like are performed. In addition to the effects of claim 1 and the like, the difference in height between the charge storage electrode and the bit line can be reduced, thereby improving reliability and the degree of freedom in designing the height and lateral dimensions of the charge storage electrode. Can be expanded.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 3 is a sectional view illustrating a manufacturing process of a semiconductor device according to a third embodiment.

FIG. 4 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fourth embodiment.

FIG. 5 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fifth embodiment.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 7 is a sectional view showing a structure of a memory cell portion of a conventional DRAM.

FIG. 8 is a diagram showing a difference in probability of occurrence of disconnection of an upper wiring due to a difference in absolute step amount between a conventional DRAM and a DRAM of the present invention.

[Explanation of symbols]

Reference Signs List 1 silicon substrate (semiconductor substrate) 2 first interlayer insulating film 3 contact hole 4 first layer wiring (first and second lower conductive members) 5 second interlayer insulating film 7a first contact hole 7b second contact hole 8a first plug 8b second plug 9 tungsten film (first conductive film) 9a second layer wiring (first upper conductive member) 10 silicon oxide film 10a upper surface protective film 14 silicon oxide film 14a sidewall 17a 3 Layer wiring (second upper conductive member) 21 Silicon substrate (semiconductor substrate) 22 First interlayer insulating film 27a First contact hole 27b Second contact hole 27c Third contact hole 28a First plug 28b Second plug 28c Third plug 29 Tungsten film (first conductive film) 29a First layer wiring (first upper layer conductive member) Reference Signs List 30 silicon oxide film 30a top protection film 34 silicon oxide film 34a sidewall 37 tungsten film (second conductive film) 37a second layer wiring (second upper layer conductive member) 38 third interlayer insulating film 39 fourth contact Hole 40 Fourth plug 41, 47 Tungsten film (third conductive film) 41a, 47a Third layer wiring (third upper conductive member) 51 Silicon substrate (semiconductor substrate) 54 Silicon oxide film layer 55 Word line 56 First interlayer insulating film 57a First contact hole 57b Second contact hole 57c Third contact hole 58a First plug 58b Second plug 58c Third plug 59 Tungsten film (first conductive film) 59a, 59b Bit line (first film) Upper layer side conductive member) 60 silicon oxide film 60a, 60b upper surface protective film 64 Con oxide film 64a, 64b side wall 65 laminated film (second conductive film) 65a 2-layer wiring (second upper conductive member) 66 capacitive insulating film 67 plate electrode

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Susumu Akamatsu 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Shunsuke 1006 Kadoma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. In-company (56) References JP-A-7-115133 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (10)

(57) [Claims] A first step of forming first and second lower conductive members on a semiconductor substrate; and forming a first insulating film on the first and second lower conductive members. Forming a second step; opening a part of the first insulating film;
A third step of forming first and second connection holes respectively reaching the lower conductive member; and depositing a conductive material in the first and second connection holes,
A fourth step of forming first and second buried layers, and depositing a first conductive film and a second insulating film on the first and second buried layers and the first insulating film. After that, the first conductive film and the second insulating film are patterned,
While forming a first upper conductive member and an upper surface protective film belonging to a wiring layer higher than each of the lower conductive members and connected to the first buried layer, the second buried layer is A fifth step of exposing an upper surface, a sixth step of forming a sidewall on a side surface of the first upper-layer-side conductive member and the upper protective film, and a step of forming the first insulating film, the sidewall, After depositing a second conductive film on the upper protective film and the second buried layer, the second conductive film is patterned to form the first conductive film.
And a seventh step of forming a second upper conductive member connected to said second buried layer belongs further upper wiring layer than the upper layer side conductive member, the third step is , Diameter of the first and second connection holes
Is 0.6 μm or less and the aspect ratio is 3 or less.
A method of manufacturing a semiconductor device, the method being performed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the first and second lower conductive members are formed in the same wiring layer connected to a semiconductor substrate. A method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the first and second lower conductive members are connected to a same wiring electrically insulated from a semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed in a layer. 4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the first step, first and second impurities on the semiconductor substrate are used as the first and second lower conductive members. A method for manufacturing a semiconductor device, wherein a diffusion layer is formed. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, a third impurity diffusion layer is further formed on the semiconductor substrate, and in the third step, the first impurity diffusion layer is formed. Forming a third connection hole reaching the third lower conductive member simultaneously with the first and second connection holes in a part of the insulating film; A conductive material is also deposited in the third connection hole to form a third buried layer. In one of the fifth step and the seventh step, the third buried layer is formed on the third buried layer. Forming an intermediate conductive member to be connected, depositing an interlayer insulating film over the entire surface of the substrate after the seventh step, flattening the interlayer insulating film, Partially reached the above intermediate conductive member Forming a fourth connection hole, forming a fourth buried layer by depositing a conductive material in the fourth connection hole, and forming a fourth buried layer on the fourth buried layer and the interlayer insulating film. After the third conductive film is deposited on the third conductive film, the third conductive film is patterned to form a third conductive film that belongs to a wiring layer further above the second upper conductive member and is connected to the fourth buried layer. Forming a conductive member on the upper layer side. 6. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, a third impurity diffusion layer is further formed on the semiconductor substrate, and in the third step, the first impurity diffusion layer is formed. Forming a third connection hole reaching the third lower conductive member simultaneously with the first and second connection holes in a part of the insulating film; Is also deposited in the third connection hole to form a third buried layer. In the fifth step, the upper surface of the third buried layer is exposed. In the seventh step, the second buried layer is formed. After further depositing a third insulating film on the conductive film, the second conductive film and the third insulating film are simultaneously patterned, and
Exposing the upper surface of the buried layer, forming a second sidewall on the side surface of the second upper conductive member and the third insulating film after the seventh step, After depositing a third conductive film on the first insulating film, the third buried layer, the third insulating film, and the second sidewall, the third conductive film is patterned, Forming a third upper conductive member belonging to a wiring layer further above the second upper conductive member and connected to the third buried layer. Device manufacturing method. 7. A method of manufacturing a semiconductor device functioning as a DRAM, comprising: a first step of forming a transistor including a gate electrode and first and second impurity diffusion layers on at least a semiconductor substrate in a memory cell region; A second step of depositing a first insulating film on the semiconductor substrate and the gate electrode; reaching a part of the first insulating film to the first and second impurity diffusion layers, respectively; A third step of forming first and second connection holes; and depositing a conductive material in the first and second connection holes.
Forming a first conductive film and a second insulating film on the first insulating film and each of the burying layers in a fourth step of forming first and second burying layers; The first conductive film and the second insulating film are patterned to form a bit line connected to the first buried layer and a bit line upper surface protective film, while exposing an upper surface of the second buried layer. A sixth step of forming sidewalls on side surfaces of the bit line and the bit line upper surface protective film; a first step of forming the first insulating film, the sidewalls, the bit line upper surface protective film, Depositing a second conductive film on the second buried layer and patterning the second conductive film to form a charge storage electrode connected to the second buried layer; The charge storage electrode and the first insulator; After depositing a second insulating film and a third conductive film on the edge film, the sidewalls, and the bit line upper surface protective film, the second insulating film and the third conductive film are patterned. An eighth step of forming a capacitor insulating film and a plate electrode . In the first step, a peripheral circuit area of the DRAM is provided.
Forming a third impurity diffusion layer on the first insulating film ; and forming the third impurity diffusion layer on a part of the first insulating film in the third step.
The third connection hole reaching the third impurity diffusion layer is
In the fourth step, the conductive material is formed at the same time as the third contact hole.
The third buried layer is formed by depositing also in the through hole, and in the fifth step, the third buried layer is connected to the third buried layer.
Forming a bit line to be formed and a bit line upper surface protection film . 8. The method of manufacturing a semiconductor device according to claim 7 , wherein the third step is performed so that the first and second connection holes have a diameter of 0.6 μm or less and an aspect ratio of 3 or less. A method of manufacturing a semiconductor device, the method being performed. 9. A semiconductor substrate, first and second lower conductive members formed on the semiconductor substrate, and first and second lower conductive members formed on the first and second lower conductive members. An opening in a part of the first insulating film;
First and second connection holes reaching the lower conductive member respectively; first and second buried layers formed by depositing a conductive material in the first and second connection holes; A first upper-layer conductive member belonging to a wiring layer higher than each lower-layer conductive member and connected to the first buried layer; an insulating layer formed on the first upper-layer conductive member; An upper protective film made of a material; a sidewall made of an insulating material formed on a side surface of the first upper conductive member and the upper protective film; and a further upper layer than the first upper conductive member. and a second upper conductive member in contact with the upper surface of the second buried layer belongs to the wiring layer, astigmatism in diameter of the first and second connection holes 0.6μm or less
A semiconductor device having a pect ratio of 3 or less . 10. The semiconductor device according to claim 9 , wherein said first and second lower conductive members are impurity diffusion layers on both sides of a gate of a transistor formed in a memory cell region of a DRAM. A semiconductor device, wherein the first upper layer conductive member is a bit line of the DRAM, and the second upper layer conductive member is a charge storage electrode of the DRAM.