JPH088349A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a defect caused by the positional shift between a contact hole and the pattern of a storage electrode in a semiconductor device, for example, at the time of patterning the storage electrode. CONSTITUTION:A TEOS 16 and a first polysilicon are deposited sequentially on the source-drain 15 on the semiconductor substrate side. The outline pattern of each film and a contact hole 20 are then patterned using a common mask thus forming a storage electrode 18 and the contact hole 20. A first side wall 21 of second polysilicon is then formed in the contact hole 20 in order to conduct the storage electrode 18 and the source-drain 15. At the same time, a second side wall is formed on the outer periphery of the storage electrode 18 followed by formation of a capacitive insulating film 23 and a cell plate 24. Since the outline pattern of the storage electrode 18 and the contact hole 20 are formed using a same mask, pattern shift due to the positional shift of mask is eliminated and thereby occurrence of defect is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a measure for preventing defects in a contact hole formed through an insulating film.

[0002]

2. Description of the Related Art FIGS. 3A to 3D and 4A,
FIG. 3B shows a method of manufacturing a conventional semiconductor device (memory cell of DRAM).

First, as shown in FIG. 3A, the silicon substrate 1 is thermally oxidized to form a thermal oxide film 2 having a thickness of 50 nm on the surface. Further, a silicon nitride film 3 having a film thickness of 100 (nm) is formed. Subsequently, the silicon nitride film 3 is selectively etched using a predetermined resist pattern as a mask to form a pattern of the silicon nitride film 3 having an opening in a field oxide film formation planned region, and the silicon nitride film 3 is used as a mask. Boron ions are implanted into the silicon substrate through the openings 3 to form the ion implantation layer 4.

Next, as shown in FIG. 3B, a film thickness of 600 nm is obtained by using the silicon nitride film 3 as an oxidation resistant mask.
Field oxide film 5 is formed. At this time, the implanted boron ions are activated and become the field inversion prevention layer 6 (channel stopper). Then, after removing the thermal oxide film 2 and the silicon nitride film 3 by etching, the exposed surface of the silicon substrate 1 is thermally oxidized to form a thermal oxide film 7 having a film thickness of 20 (nm). Further, a film thickness of 500 is formed on the thermal oxide film 7 and the field oxide film 5.
A first polysilicon film 8 of (nm) is deposited.

Next, as shown in FIG. 3C, etching is performed using a resist as a mask to pattern the first polysilicon film 8 and the thermal oxide film 7 to form a gate oxide film 10 and a gate 11. At the same time, a step pattern 25 (word line) made of the first polysilicon film 8 is formed on the field oxide film 5. Next, phosphorus ions are implanted to form the source / drain 15 of the transistor.

Next, as shown in FIG. 3D, the film thickness is 2
A TEOS oxide film 16 of 00 (nm) is formed on the entire surface.
Then, the TEOS oxide film is selectively etched using the resist as a mask, and a contact hole 26 that penetrates part of the TEOS oxide film 16 and reaches the source / drain 15 is formed.
To form.

Next, as shown in FIG. 4A, the film thickness is 2
After accumulating a 00 (nm) second polysilicon film on the entire surface, the storage electrode 27 is formed by etching this using a resist pattern as a mask. At this time,
Since the second polysilicon film is also deposited in the contact hole 26, the storage electrode 27 is in contact with the source / drain 15 through the contact hole 26.

Next, as shown in FIG. 4B, the surface of the storage electrode 27 formed of the second polysilicon film is thermally oxidized to form a thermal oxide film having a thickness of 10 (nm). After that, this is patterned to form a capacitance insulating film 23. Subsequently, a third polysilicon film having a film thickness of 400 (nm) is deposited on the entire surface, and selective etching is performed using the resist pattern as a mask to form the cell plate 24.

After the memory cells of the DRAM are formed in this manner, other necessary steps are performed to form the semiconductor device (D
RAM) is manufactured.

[0010]

However, the above-described conventional method of manufacturing a semiconductor device has the following problems.

5A to 5C are all shown in FIG.
It is a figure which shows the example of some possible shapes of the state in the VV cross section in (a). In the conventional method for manufacturing a semiconductor device, as described above, the TEOS oxide film 16 is used.
After the contact holes 26 are formed in the contact holes 26, the storage electrodes 27 are deposited on the contact holes 26 and then patterned. At this time, if the positions of the masks used in the photolithography process are correct, the pattern shown in FIG. The storage electrode 27 has a shape substantially matching the position of the contact hole 26 as shown in FIG. However, if the position of the mask for patterning the contact hole 26 and the position of the mask for patterning the storage electrode 27 deviate in the photolithography process, as shown in FIG. The electrodes 27 and the electrodes 27 are formed at positions displaced from each other. This shift is generally called overlay shift of the exposure apparatus, and it is difficult to completely eliminate it. In particular, if the outer peripheral portion of the storage electrode and the contact hole 26 are displaced so as to overlap each other, as shown in FIG.
As shown in (c), when patterning the second polysilicon film in the step of forming the storage electrode 27, the surface of the silicon substrate 1 exposed in the contact hole 26 is also etched, and the silicon substrate 1 is exposed. A damaged portion 28 is generated. That is, a serious defect is given to the semiconductor device.

The above problems in the contact portion are not only caused when the storage electrode contact of the DRAM memory cell is formed, but generally a contact hole is opened in the insulating film to make contact between the upper conductive film and the lower conductive portion. Also occurs when forming.

The present invention has been made in view of the above circumstances, and an object thereof is, as a method of manufacturing a semiconductor device, effectively preventing the occurrence of defects in a contact portion due to a displacement of a mask in a photolithography process. To do.

[0014]

In order to achieve this object, a means for solving the problems described in the present invention is to form a conductive film on an insulating film and then to simultaneously form a contact hole and a contact hole at the same time as patterning of the conductive film and the insulating film. Is formed, and a sidewall is formed in the contact hole to electrically connect the conductive film to the conductive portion in the lower layer, which is a method for manufacturing a semiconductor device.

Specifically, the means taken by the invention of claim 1 is as follows.
As a method of manufacturing a semiconductor device, a step of forming an insulating film on a conductive portion provided on the semiconductor substrate side, a step of depositing a first conductive film on the insulating film, and The first conductive film and the insulating film are selectively removed so that a part of the first conductive film and the insulating film remains and a conductive part below the first conductive film and the insulating film is penetrated into the remaining part. Patterning so that a contact hole reaching the contact hole is formed, and a sidewall of the contact hole,
And a step of forming a sidewall which is made of a second conductive film and electrically connects the conductive portion and the first conductive film.

The means taken by the invention of claim 2 is defined by claim 1.
In the invention described above, the semiconductor device is a DRAM, and the conductive portion is a source / drain of a switching transistor of a memory cell of the DRAM. then,
The step of patterning the first conductive film and the insulating film is a method of simultaneously patterning the outer shape pattern of the remaining portion of the storage electrode and the insulating film and the contact holes to the source / drain.

The means taken by the invention of claim 3 is the method of claim 2
In the invention, the step of forming the sidewall in the contact hole is a method of forming the sidewall made of the first conductive film also on the outer peripheral side wall of the remaining portion of the storage electrode and the insulating film.

The means taken by the invention of claim 4 is defined by claim 1.
In the present invention, the conductive portion is the source / drain of the switching transistor of the memory cell of the DRAM. At this time, the step of patterning the first conductive film and the insulating film is a method of patterning the outer shape pattern of the remaining portion of the bit line and the insulating film and the contact holes to the source / drain.

The means taken by the invention of claim 5 is the method of claim 1.
In the invention described above, the first conductive film is a metal wiring on the interlayer insulating film. At this time, the step of patterning the first conductive film and the insulating film is a method of simultaneously patterning the outer shape pattern of the remaining portion of the metal wiring and the interlayer insulating film and the contact hole to the conductive portion under the interlayer insulating film.

It is equipped with.

[0021]

By the above method, in the invention of claim 1, the insulating film and the first conductive film are simultaneously patterned in a laminated state. At that time, since the outer pattern and the contact hole of both are patterned at the same time using the same mask,
Relative displacement between the outer shape pattern and the contact hole due to the displacement of the mask is reliably prevented. On the other hand, since the conductive portion below the insulating film and the first conductive film are in the conductive state via the sidewall formed on the side wall of the contact hole, the conductive failure in the contact hole does not occur.

According to the second aspect of the invention, even when the size of the outer shape of the storage electrode arranged in the memory cell of the DRAM is not so different from the diameter of the contact hole, the pattern shift between the storage electrode and the contact hole is caused. The occurrence of defects due to

According to the third aspect of the present invention, since the sidewall is formed also on the outer peripheral portion of the storage electrode, the sidewall integrated with the storage electrode has a structure surrounding the outer periphery of the lower insulating film, and the storage is stored in the memory cell. A sufficient amount of charge that can be obtained is secured.

According to the invention of claim 4, when the bit line of the DRAM memory cell is formed, the bit line and the source / drain are connected through the contact hole without causing a defect in the source / drain below. Is secured.

According to the fifth aspect of the present invention, even when the metal wiring is formed on the interlayer insulating film, the metal wiring and the metal wiring are formed through the contact hole without causing a defect in the conductive portion below the interlayer insulating film. The connection with the conductive portion is secured.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A DRAM manufacturing process according to an embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (d) and 2 (a).
This will be described with reference to (c).

First, as shown in FIG. 1A, the silicon substrate 1 doped with P-type impurities is thermally oxidized to form a thermal oxide film 2 having a thickness of 50 nm on the surface. Further, after depositing a silicon nitride film 3 having a film thickness of 100 (nm) on the thermal oxide film 2, patterning is performed to form a mask of the silicon nitride film 3 having an opening in a field oxide film formation planned region. Boron ions are implanted into the silicon substrate 1 through the openings of the silicon nitride film 3 to form the ion implantation layer 4.

Next, as shown in FIG. 1B, a film thickness of 600 (n) is obtained by using the silicon nitride film 3 as an oxidation resistant mask.
The field oxide film 5 of m) is formed. At this time, the boron ions implanted in the previous step are activated and become the field inversion prevention layer 6 (channel stopper). Then, after removing the thermal oxide film 2 and the silicon nitride film 3 by etching, the surface of the silicon substrate 1 is thermally oxidized again to form a thin thermal oxide film 7 having a thickness of 20 (nm), Further, a first polysilicon film 8 having a film thickness of 500 (nm) is deposited on the thermal oxide film 7 and the field oxide film 5. Further, the surface of the first polysilicon film 8 is thermally oxidized to form an on-gate oxide film 9 having a film thickness of 100 (nm).

Next, as shown in FIG. 1C, etching is performed using a resist as a mask to pattern the first polysilicon film 8 and the thermal oxide film 7 to form a gate oxide film 10, a gate 11 and a gate. An upper oxide film 12 is formed, and a first step pattern 13 made of a first polysilicon film 8 and a second step pattern 14 made of the gate upper oxide film 9 are formed on the field oxide film 5. The first step pattern 13 and the second step pattern 14 can increase the surface area of the storage electrode formed in the next step. By increasing the surface area of the storage electrode, the amount of charge stored in the memory cell of the DRAM can be further increased, which is advantageous for improving the characteristics of the semiconductor device. After that, phosphorus ions are implanted from above the silicon substrate 1 to form the source / drain 15 of the transistor. The steps up to this point are the same as those of the conventional manufacturing method shown in FIGS. 3A to 3C except for the formation of the oxide film 12 on the gate.

Next, as shown in FIG. 1D, the film thickness is 2
A TEOS oxide film 16 having a thickness of 00 (nm) is formed on the entire surface, and a second polysilicon film 17 having a thickness of 300 (nm) is further deposited on the entire surface. The TEOS film 16 is the insulating film according to the invention of claim 1, and the second polysilicon film 17 is the first conductive film according to the invention of claim 1.

Next, as shown in FIG. 2A, a resist pattern is formed using a storage electrode forming mask having an opening in the center, and the second polysilicon film 17 and the TEOS oxide film are formed using this as a mask. 16 and 16 are selectively etched. At that time, first, the external pattern of the storage electrode 18 and the second pattern
A contact hole penetrating the polysilicon film 17 is formed, and then the outer pattern of the TEOS oxide film 16 and T
A contact hole 20 which penetrates the EOS oxide film 16 and reaches the source / drain 15 is formed. That is,
Using the common mask, the outer pattern of the storage electrode 18 and the TEOS oxide film 16 and the contact hole 20 are formed. If the film forming the storage electrode 18 and the film forming the insulating film cannot be treated with the same etching agent, the etching agent may be changed in the middle and the outer pattern and contact hole of each film may be sequentially patterned. Good.

Next, as shown in FIG. 2B, a film thickness of 40
A third polysilicon film having a thickness of 0 (nm) is formed on the entire surface, anisotropic etching is performed, and the first sidewall 21 made of the third polysilicon film is formed on the side wall of the contact hole 20.
To form. This third polysilicon film is the second conductive film according to the invention of claims 1 and 3. The storage electrode 18 and the source / drain 15 are electrically connected by the first sidewall 21. Therefore, the connection between the source / drain 15 and the storage electrode 18 is secured through the contact hole 20. In addition, the contact hole 20
At the same time as the formation of the sidewalls 21 inside the storage electrodes 18,
The second sidewall 22 made of the third polysilicon film is also formed on the outer peripheral portion of the TEOS oxide film 16.

Next, as shown in FIG. 2C, the surfaces of the storage electrode 18 and the first and second sidewalls 21 and 22 are thermally oxidized to form a thermal oxide film having a thickness of 10 (nm). After the formation, this is patterned to form the capacitance insulating film 23. Subsequently, a fourth polysilicon film is formed on the entire surface and is patterned to form the cell plate 24.

Although the subsequent steps are omitted, after forming the memory cell, necessary steps are performed to manufacture the semiconductor device.

As described above, in the above-described embodiment, in the manufacturing process of the semiconductor device, the TEOS oxide film 1 is formed as in the conventional case.
Instead of forming a contact hole in 6 and then depositing a polysilicon film forming a storage electrode and patterning this to form a storage electrode, a TEOS oxide film 16 and a second polysilicon film 17 are formed. After the layer films are sequentially deposited, the outer pattern of the storage electrode 18 and the TEOS oxide film 16 and the contact hole 20 are simultaneously formed by using the storage electrode forming mask. Therefore, the accuracy of the position of the contact hole 20 with respect to the outer shape pattern of the storage electrode 18 depends on the position accuracy of the outer shape pattern of the storage electrode 18 and the contact hole pattern formed in the central portion of the storage electrode forming mask. , It has nothing to do with the alignment accuracy of the mask. Therefore, it is possible to prevent the source / drain defects due to the positional displacement of the mask, which is equivalent to the above-mentioned FIGS. 5B and 5C.

On the other hand, the source / drain 15 is formed by the sidewalls 21 formed in the contact holes 20.
Since electrical connection between the storage electrode 18 and the storage electrode 18 is ensured, there is no fear that transmission of signals will be hindered. In addition, the storage electrode 1
8 and the TEOS oxide film 16 at the time of patterning the other source / drain 15 or the gate 11 side.
Even the EOS oxide film 16 is removed, but by forming an interlayer insulating film after the step of FIG. 2C, it is possible to prevent interference with an upper member, which hinders manufacturing of a semiconductor device. There is no such thing.

In the above embodiment, the sidewall 22 is formed also on the outer peripheral portion of the storage electrode 18, but the present invention is not necessarily limited to the method of this embodiment, and the sidewall 22 is formed. You don't have to. However, forming the sidewalls 22 as in the above-described embodiment has an advantage that the surface area of the storage electrode 18 is increased and the amount of charge that can be stored can be increased.

The manufacturing method of the present invention is not applied only to the step of forming the storage electrode and the storage electrode contact as in the above embodiment. Although the embodiment is omitted, for example, the right source / drain 15 of the two source / drain 15 of FIGS. 1A to 1D and FIGS. 2A to 2C.
Although a bit line (not shown) of the DRAM memory cell is in contact with, the present invention can be applied to the step of forming the bit line and the bit line contact hole. At that time, almost the same as in the above embodiment, the interlayer insulating film and the conductive film forming the bit line were simultaneously deposited, and then the outer pattern and the contact hole were simultaneously patterned,
After that, sidewalls may be formed in the contact holes. In addition, the word line (gate 1 in the above embodiment)
It can also be applied to the case where a contact hole is formed up to the word line when the upper layer wiring is provided on the first and first step patterns 13) via the interlayer insulating film.

Further, according to the present invention, not only the DRAM memory cell but also a general semiconductor device has a multi-layered wiring structure in which a plurality of metal wiring layers are provided with an interlayer insulating film interposed between the metal wiring layers. It can also be applied to the step of forming a contact hole for connecting the. It can also be applied to a step of forming a contact hole from an upper layer wiring to an impurity diffusion region such as an emitter in a bipolar transistor manufacturing process.

[0040]

As described above, according to the present invention,
As a method of manufacturing a semiconductor device, an insulating film and a first conductive film are sequentially deposited on a conductive portion formed on the semiconductor substrate side, and the outer pattern of the first conductive film and the insulating film and a contact hole are used as a common mask. After patterning by using, the side wall for conducting the first conductive film and the conductive portion is formed in the contact hole, so that the occurrence of the defect in the contact portion due to the displacement of the mask is effectively prevented. Therefore, the yield of the semiconductor device can be improved and the characteristics can be stabilized.

[0041]

[Brief description of drawings]

[0042]

FIG. 1 is a cross-sectional view showing a change in structure of a semiconductor device up to a step of depositing a polysilicon film for a storage electrode in a process of manufacturing a DRAM memory cell of an example.

[0043]

FIG. 2 is a cross-sectional view showing a change in structure of a semiconductor device from a patterning process of storage electrodes and contact holes to a process of forming a cell plate in a process of manufacturing a DRAM memory cell of an example.

[0044]

FIG. 3 is a cross-sectional view showing a change in structure of a semiconductor device up to a step of forming a contact hole in an insulating film in a conventional process of manufacturing a DRAM memory cell.

[0045]

FIG. 4 is a cross-sectional view showing a change in structure of a semiconductor device from a storage electrode forming step to a cell plate forming step in a conventional DRAM memory cell manufacturing process.

[0046]

FIG. 5 is a cross-sectional view showing a state that can occur in a contact portion in a conventional manufacturing method.

[0047]

[Explanation of symbols]

 1 silicon substrate 2 thermal oxide film 3 silicon nitride film 4 ion implantation layer 5 field oxide film 6 field inversion prevention layer 7 thermal oxide film 8 first polysilicon film 9 oxide film 10 gate oxide film 11 gate 12 gate oxide film 13 1 step pattern 14 second step pattern 15 source / drain 16 TEOS oxide film 17 second polysilicon film 18 first storage electrode 20 contact hole 21 first sidewall 22 second sidewall 23 capacitive insulating film 24 cell plate 25 step pattern 26 Contact hole 27 Storage electrode 28 Damaged part

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H01L 21/768

Claims (5)

[Claims] 1. A step of forming an insulating film on a conductive portion provided on the semiconductor substrate side, a step of depositing a first conductive film on the insulating film, and a step of forming the first conductive film using a common mask. The film and the insulating film are selectively removed, and a part of the first conductive film and the insulating film remains, and the first conductive film and the insulating film penetrate into the remaining part to reach the lower conductive part. A step of patterning so as to form a contact hole; and a step of forming a sidewall, which is formed of a second conductive film and electrically connects the conductive portion and the first conductive film, on a sidewall of the contact hole. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a DRAM, the conductive portion is a source / drain of a switching transistor of a memory cell of the DRAM, the first conductive film and the insulating film. In the step of patterning the film, a method of manufacturing a semiconductor device, wherein the outer pattern of the storage electrode and the remaining portion of the insulating film and the contact hole to the source / drain are simultaneously patterned. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of forming a sidewall in the contact hole, a side of the first conductive film is formed also on an outer peripheral side wall of the remaining portion of the storage electrode and the insulating film. A method of manufacturing a semiconductor device, which comprises forming a wall. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive portion is a source / drain of a switching transistor of a memory cell of a DRAM, and the step of patterning the first conductive film and the insulating film comprises: A method of manufacturing a semiconductor device, which comprises patterning an outer pattern of a remaining portion of a line and an insulating film and a contact hole to the source / drain. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive film is a metal wiring on the interlayer insulating film, and in the step of patterning the first conductive film and the insulating film, the metal wiring is formed. And a method of manufacturing a semiconductor device, characterized in that the outer pattern of the remaining portion of the interlayer insulating film and the contact hole to the conductive portion under the interlayer insulating film are simultaneously patterned.