JP3252795B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3252795B2 JP3252795B2 JP14548098A JP14548098A JP3252795B2 JP 3252795 B2 JP3252795 B2 JP 3252795B2 JP 14548098 A JP14548098 A JP 14548098A JP 14548098 A JP14548098 A JP 14548098A JP 3252795 B2 JP3252795 B2 JP 3252795B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- interlayer insulating
- wiring
- contact hole
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は例えばＳＲＡＭの
ように下層の層間絶縁膜上にポリシリコン配線（抵抗と
して機能する）を形成し、その上に上層の層間絶縁膜を
形成し、その上に形成するＡｌ等金属配線と接続するた
めのコンタクトホールをポリシリコン配線層を貫通して
設け、いわゆるサイドコンタクトさせる半導体装置の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a polysilicon wiring (functioning as a resistor) on a lower interlayer insulating film, such as an SRAM, and forming an upper interlayer insulating film on the polysilicon wiring. a contact hole for connecting with Al or the like metal wiring which forms provided through the polysilicon wiring layer, a method of manufacturing a semiconductor device for so-called side contact.
【０００２】[0002]
【従来の技術】半導体装置の従来の製造方法と構造を高
抵抗を負荷とするＳＲＡＭの場合を例に図面を用いて説
明する。図１は工程途中の要部断面図で図２はその後の
工程の同一部分を示す断面図である。 （１）Ｐ型単結晶シリコンでなる半導体基板１の表面に
素子形成領域を確定するフィールド酸化膜２を選択的に
形成し素子形成領域にゲート酸化膜３を形成する。 （２）次に全面に例えば上下面をポリシリコンで挟んだ
ＷＳｉ膜を形成し、それをパターニングしてトランスフ
ァトランジスタＡ、ドライバトランジスタＢ、図外の他
のトランジスタのゲート電極（ゲート配線）４Ａ、４Ｂ
をそれぞれの素子形成領域を２分するように形成する。
ここでドライバトランジスタのゲート電極４Ｂはフィー
ルド酸化膜３をまたぐように伸びて端部はトランスファ
トランジスタの素子形成領域に達している。 （３）次にこれらゲート電極４Ａ，４Ｂとフィールド酸
化膜３とを（その他図外において必要個所に形成したホ
トレジスト膜も）マスクにしてイオン注入により浅く低
濃度にＰを導入してＬＤＤ部５を形成後ＣＶＤにより全
面に酸化膜を形成し、全面異方性ドライエッチングによ
りエッチバックしてゲート電極４Ａ，４Ｂの上面を露出
させるとそれらの端部にサイドウォール６が形成され
る。 （４）次にこのサイドウォール６、ゲート電極４Ａ，４
Ｂおよびフィールド酸化膜３を（その他図外において必
要個所に形成したホトレジスト膜も）マスクにしてイオ
ン注入により比較的深く高濃度にＡｓを導入してソース
・ドレイン領域７を形成する。 （５）次に第１の酸化膜８、第１のＢＰＳＧ９をＣＶＤ
により形成して第１層目の層間絶縁膜とする。なお、第
１のＢＰＳＧ９は厚めに形成して熱処理リフローさせて
なだらかにし、その後全面エッチバックして所定の厚み
を残したものである。 （６）次に、半導体基板１の所定の活性領域に達するコ
ンタクトホール（図示せず）をエッチング形成してスパ
ッタにより表面にＳｉ膜が積層されたＷＳｉ膜を形成し
パターニングしてＶｃｃライン１０Ａ、Ｇｎｄライン１
０Ｂ等の配線を形成すると共に後の工程で形成するポリ
シリコンでなる抵抗のそれより上層の配線との接続のた
めのコンタクト配置予定位置にエッチングストッパ１０
Ｃを形成する。 （７）次に全面にＣＶＤにより第２の酸化膜１１を形成
しこれを２層目の層間絶縁膜とする。その後トランスフ
ァトランジスタＡのドレイン領域７の表面の一部をそこ
へ伸びているドライバトランジスタＢのゲート電極４Ｂ
の端部を含んで露出する共通コンタクトホール１２をド
ライエッチングにより形成し、そこにＰを高濃度にイオ
ン注入する。１３はその注入部分を示す。 （８）次にＣＶＤによりポリシリコン膜を形成し、フォ
トレジスト膜をマスクに後述する負荷抵抗とする部分に
イオン注入によりＰを導入して所定の層抵抗とし、同様
に後述する基準電圧作成用の抵抗とする部分にＰをより
高濃度に導入して所定の層抵抗とし、パターニングして
共通コンタクトホール１２でトランスファトランジスタ
Ａのドレイン領域７とドライバトランジスタＢのゲート
電極４Ｂとに一端が接続した負荷抵抗１４Ａと基準電圧
作成用の抵抗１４Ｂを形成する。なお、基準電圧作成用
の抵抗１４Ｂは両端が上層の配線に接続されるものでそ
の接続点の下方には前述したエッチングストッパ１０Ｃ
が配置されている。 （９）次にＣＶＤにより第３の酸化膜、第２のＢＰＳＧ
膜１６を積層形成し、この２層あわせて３層目の層間絶
縁膜とする。なお、第２のＢＰＳＧ膜１６は厚めに形成
して熱処理リフローさせて表面を滑らかにした後全面エ
ッチバックして所定の厚みを残したものである。 （１０）次に半導体基板１の活性領域に向けてのコンタ
クトホール１７Ａと同時に基準電圧作成用抵抗１４Ｂに
向けてのコンタクトホール１７Ｂをエッチング形成す
る。このエッチングは当初ウェットエッチングで開口部
にテーパを設けその後異方性ドライエッチでエッチング
する。抵抗１４Ｂに向けてのコンタクトホール１７Ｂは
抵抗１４Ｂの表面を露出させてそれ以上に進まない方が
好ましいが半導体基板１の表面に向けての深いエッチン
グを行なっている間にエッチングスピードの差を大きく
とれないのでポリシリコンでなる抵抗１４がエッチング
され、その下の第２の酸化膜もエッチングされ、エッチ
ングスピードの差の大きいＷＳｉでなるエッチングスト
ッパ１０Ｃで止まるものである。即ち別々にエッチング
形成する手間を省き、同時エッチングとし、抵抗１４Ｂ
にはエッチング端面でコンタクトを得ようと（サイドコ
ンタクト）するものである。以上の工程により図１に示
す形状を得る。2. Description of the Related Art A conventional manufacturing method and structure of a semiconductor device will be described with reference to the drawings, taking as an example the case of an SRAM having a high resistance load. FIG. 1 is a cross-sectional view of a main part in the middle of a process, and FIG. 2 is a cross-sectional view showing the same part in a subsequent process. (1) A field oxide film 2 for defining an element formation region is selectively formed on the surface of a semiconductor substrate 1 made of P-type single crystal silicon, and a gate oxide film 3 is formed in the element formation region. (2) Next, for example, a WSi film having upper and lower surfaces sandwiched by polysilicon is formed on the entire surface, and is patterned to form a transfer transistor A, a driver transistor B, and a gate electrode (gate wiring) 4A of another transistor (not shown). 4B
Is formed so that each element formation region is divided into two.
Here, the gate electrode 4B of the driver transistor extends over the field oxide film 3 and its end reaches the element formation region of the transfer transistor. (3) Next, using the gate electrodes 4A, 4B and the field oxide film 3 as masks (and also a photoresist film formed at a necessary place outside the figure), P is introduced into the LDD portion 5 by shallow and low concentration by ion implantation. After forming an oxide film on the entire surface by CVD and etching back by anisotropic dry etching on the entire surface to expose the upper surfaces of the gate electrodes 4A and 4B, sidewalls 6 are formed at their ends. (4) Next, the sidewall 6 and the gate electrodes 4A, 4
Using the B and the field oxide film 3 as a mask (and also a photoresist film formed at a necessary portion outside the figure), As is introduced relatively deeply and at a high concentration by ion implantation to form the source / drain regions 7. (5) Next, the first oxide film 8 and the first BPSG 9 are formed by CVD.
To form a first interlayer insulating film. In addition, the first BPSG 9 is formed to be thicker and smooth by heat treatment and reflow, and thereafter, is etched back all over to leave a predetermined thickness. (6) Next, a contact hole (not shown) reaching a predetermined active region of the semiconductor substrate 1 is formed by etching, and a WSi film having a Si film laminated on the surface is formed by sputtering and patterned to form a Vcc line 10A. Gnd line 1
0B and the like, and an etching stopper 10 is formed at a position where a contact is to be arranged for connection with a wiring of a layer above the resistance of polysilicon formed in a later step.
Form C. (7) Next, a second oxide film 11 is formed on the entire surface by CVD, and this is used as a second interlayer insulating film. Thereafter, the gate electrode 4B of the driver transistor B extending over a part of the surface of the drain region 7 of the transfer transistor A
Is formed by dry etching, including the end of P, and P ions are implanted into the common contact hole 12 at a high concentration. Reference numeral 13 denotes the injection portion. (8) Next, a polysilicon film is formed by CVD, and P is introduced by ion implantation into a portion serving as a load resistance described later using a photoresist film as a mask to obtain a predetermined layer resistance. P is introduced at a higher concentration into a portion to be a resistor, a predetermined layer resistance is formed, and patterning is performed. A load resistor 14A and a resistor 14B for creating a reference voltage are formed. The resistor 14B for generating the reference voltage has both ends connected to the upper layer wiring, and the etching stopper 10C described below is provided below the connection point.
Is arranged. (9) Next, a third oxide film and a second BPSG by CVD
A film 16 is formed by lamination, and the two layers are combined to form a third interlayer insulating film. The second BPSG film 16 is formed to be thicker, is subjected to a heat treatment reflow to smooth the surface, and is then etched back to leave a predetermined thickness. (10) Next, simultaneously with the contact hole 17A toward the active region of the semiconductor substrate 1, the contact hole 17B toward the reference voltage generating resistor 14B is formed by etching. In this etching, an opening is tapered by wet etching at first, and then anisotropic dry etching is performed. It is preferable that the contact hole 17B toward the resistor 14B exposes the surface of the resistor 14B and does not proceed any further. However, the difference in etching speed increases during the deep etching toward the surface of the semiconductor substrate 1. Therefore, the resistor 14 made of polysilicon is etched and the second oxide film thereunder is also etched, and stops at the etching stopper 10C made of WSi having a large difference in etching speed. That is, the trouble of separately forming the etching is eliminated, the simultaneous etching is performed, and the resistor 14B
In order to obtain a contact at the etched end face (side contact). Through the above steps, the shape shown in FIG. 1 is obtained.
【０００３】（１１）次に図２に示すようにスパッタに
よりＴｉ／ＴｉＮの積層膜１８Ａを形成する。 （１２）次にＮ2雰囲気中でアニールしてＴｉとＳｉを
反応させコンタクトを得る。アニール条件はランプアニ
ール、６５０℃、６０秒である。 （１３）次に、スパッタによりＡｌ膜（Ａｌ−Ｃｕ−Ｓ
ｉ）１８、ＴｉＮ膜１８Ｂを順次形成し、これら積層膜
１８Ａ，１８，１８Ｂをパターニングしてコンタクトホ
ール１７Ａを介してトランスファトランジスタＡにつな
がるデジット線とか抵抗１４Ｂにコンタクトホール１７
Ｂを介してつながる配線等を形成する。 （１４）その後ＰＳＧ膜２０とＳｉＮ膜２１とをカバー
膜として形成し、パッド部（図示せず）の開口その他必
要な工事をへてＳＲＡＭは完成する。(11) Next, as shown in FIG. 2, a laminated film 18A of Ti / TiN is formed by sputtering. (12) Next, annealing is performed in an N 2 atmosphere to react Ti and Si, thereby obtaining a contact. Annealing conditions are lamp annealing, 650 ° C., and 60 seconds. (13) Next, an Al film (Al-Cu-S
i) 18 and a TiN film 18B are sequentially formed, and these laminated films 18A, 18 and 18B are patterned and a digit line connected to the transfer transistor A via the contact hole 17A or a contact hole 17 for the resistor 14B.
A wiring or the like connected via B is formed. (14) After that, the PSG film 20 and the SiN film 21 are formed as a cover film, and the SRAM is completed after opening a pad portion (not shown) and other necessary works.
【０００４】[0004]
【発明が解決しようとする課題】上記従来の製造方法で
は半導体基板１の表面に向け穿たれるコンタクトホール
１７Ａともっと上層のポリシリコンでなる抵抗１４Ｂに
向け穿たれるコンタクトホール１７Ｂを同一のエッチン
グ工程として工程を簡略にしている。しかしながら現状
では酸化膜でなる層間絶縁膜に対するエッチングスピー
ドとポリシリコン膜でなる抵抗１４Ｂに対するエッチン
グスピードとの差を大きく出来ないので同時にエッチン
グすると抵抗１４Ｂに向けてのコンタクトホール１７Ｂ
が先に開き、その後半導体基板１の表面に向けてコンタ
クトホール１７Ａが開くまで抵抗１４Ｂがエッチングさ
れ裏まで貫通する。そこでサイドコンタクトにより接続
しなければならないが、従来充分なコンタクトがえられ
ない場合があり抵抗１４Ｂの決定する基準電圧がばらつ
き特性上の不具合となることがあった。上記したアニー
ルの条件はもともと半導体基板の活性領域にＴｉ／Ｔｉ
Ｎでなるバリヤ膜を表面コンタクトさせるに適した条件
をそのまま適用しているものである。そこで本発明者は
ポリシリコン膜に対するサイドコンタクトの場合の条件
を種々検討した結果この発明の方法を見出した。In the above-mentioned conventional manufacturing method, the same etching is applied to the contact hole 17A drilled toward the surface of the semiconductor substrate 1 and the contact hole 17B drilled toward the resistor 14B made of a higher polysilicon layer. The steps are simplified. However, at present, the difference between the etching speed for the interlayer insulating film made of an oxide film and the etching speed for the resistor 14B made of a polysilicon film cannot be increased.
The resistor 14B is etched and penetrates to the back until the contact hole 17A is opened toward the surface of the semiconductor substrate 1 after that. Therefore must be connected by the side contact, but there is the reference voltage determining the conventional might sufficient contactor bets can not be obtained resistance 14B is that a malfunction of the variation characteristic. The annealing conditions described above were originally based on Ti / Ti
Conditions suitable for bringing the barrier film made of N into surface contact are applied as they are. The inventor of the present invention has found the method of the present invention as a result of various studies on conditions for side contact with the polysilicon film.
【０００５】[0005]
【課題を解決するための手段】半導体基板上に下層の層
間絶縁膜を形成し、その上にポリシリコン膜でなる配線
を形成し、それを覆う上層の層間絶縁膜を形成し、前記
上層および下層の層間絶縁膜を貫通して半導体基板表面
の活性領域に達する第１のコンタクトホールと前記上層
の層間絶縁膜および前記配線をなすポリシリコン膜を貫
通する第２のコンタクトホールを同時にドライエッチン
グで形成し、その上にＴｉ／ＴｉＮ積層膜を形成し、ア
ニール処理によりＴｉ／ＴｉＮ積層膜を活性領域に表面
コンタクトさせると共にポリシリコン膜にサイドコンタ
クトさせる半導体装置の製造方法において、前記アニー
ル処理の温度を６１０℃〜６３０℃と低くした。アニー
ル温度が６３０℃を超えて高すぎるとこのようなサイド
コンタクトの場合コンタクト抵抗が大きくなりばらつき
も大きくなることを見出した。また、６１０℃に満たな
い低い温度では、半導体基板とのコンタクトもポリシリ
コン膜のサイドコンタクトの部分も温度が低いほどコン
タクト抵抗が高くなる傾向が見られる。A lower interlayer insulating film is formed on a semiconductor substrate, a wiring made of a polysilicon film is formed thereon, and an upper interlayer insulating film covering the wiring is formed. The first contact hole penetrating the lower interlayer insulating film and reaching the active region on the surface of the semiconductor substrate and the second contact hole penetrating the upper interlayer insulating film and the polysilicon film forming the wiring are simultaneously dry-etched. Forming a Ti / TiN laminated film thereon, and making the Ti / TiN laminated film a surface contact with the active region and a side contact with the polysilicon film by annealing. Was lowered to 610 ° C. to 630 ° C. It has been found that if the annealing temperature exceeds 630 ° C. and is too high, the contact resistance increases and the variation increases in the case of such a side contact. At a low temperature of less than 610 ° C., the contact resistance tends to increase as the temperature of both the contact with the semiconductor substrate and the side contact of the polysilicon film decreases.
【０００６】[0006]
【発明の実施の形態】この発明の製造方法は半導体基板
上に下層の層間絶縁膜を形成し、その上にポリシリコン
膜でなる配線を形成し、それを覆う上層の層間絶縁膜を
形成し、前記上層および下層の層間絶縁膜を貫通して半
導体基板表面の活性領域に達する第１のコンタクトホー
ルと上層の層間絶縁膜および前記配線をなすポリシリコ
ン膜を貫通する第２のコンタクトホールを同時にドライ
エッチングで形成し、そこにＴｉ／ＴｉＮ積層膜をバリ
ア層として形成しコンタクトをとる半導体装置に適用す
るものである。後述する実施例ではＳＲＡＭを例に説明
するがそれに限定されるものではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing method of the present invention comprises forming a lower interlayer insulating film on a semiconductor substrate, forming a wiring made of a polysilicon film thereon, and forming an upper interlayer insulating film covering the wiring. A first contact hole penetrating the upper and lower interlayer insulating films and reaching the active region on the surface of the semiconductor substrate, and a second contact hole penetrating the upper interlayer insulating film and the polysilicon film forming the wiring at the same time. The present invention is applied to a semiconductor device which is formed by dry etching, and in which a Ti / TiN laminated film is formed as a barrier layer to make contact. In the embodiments described below, an SRAM will be described as an example, but the present invention is not limited to this.
【０００７】Ｔｉ／ＴｉＮ積層膜を形成後アニール処理
を行なう。この発明の特徴はアニールの条件にある。ア
ニール温度が６１０℃〜６３０℃が適当である。雰囲気
はＮ２で、通常ランプ加熱による急速加熱の毎葉処理で
行ない、昇温後６０〜１００秒保持する。複数ウェーハ
を同時にバッチ処理する場合は保持時間はもっと長くし
ても良い。After forming the Ti / TiN laminated film, an annealing process is performed. The feature of the present invention lies in the annealing conditions. An annealing temperature of 610 ° C to 630 ° C is appropriate. The atmosphere is N2, which is usually performed by rapid heating by lamp heating for each leaf treatment, and is maintained for 60 to 100 seconds after the temperature is raised. When batch processing a plurality of wafers simultaneously, the holding time may be longer.
【０００８】その後Ａｌを主とする膜（例えばＣｕ，Ｓ
ｉ入りＡｌ）を形成し、その膜と共にＴｉ／ＴｉＮ積層
膜をパターニングしてＡｌ配線を形成する。Thereafter, a film mainly containing Al (for example, Cu, S
i-containing Al) is formed, and a Ti / TiN laminated film is patterned together with the film to form an Al wiring.
【実施例】この発明の一実施例を図面を用いて説明す
る。製造する半導体装置もその構成部位も図１，Ｂに示
す従来とかわらないので図面を共用する。 （１）図１に示す中間加工体を準備するまでは従来の製
造方法と同じなので説明を略す。 （２）図１に示す構造を得た後、図２に示すようにスパ
ッタによりＴｉ／ＴｉＮの積層膜１８Ａを形成する。Ｔ
ｉは０．０８μｍ、ＴｉＮは０．１μｍの厚みである。
なお、ＴｉＮのスパッタ成膜はＮ２ガスを含む雰囲気中
でＴｉをスパッタするものである。 （３）次にＮ2雰囲気中でアニールしてＴｉとＳｉを反
応させコンタクトを得る。アニール条件はランプアニー
ル、６２０℃、６０秒である。 （４）以後従来と同様に、スパッタによりＡｌ膜（Ａｌ
−Ｃｕ−Ｓｉ）１８、ＴｉＮ膜１８Ｂを順次形成し、こ
れら積層膜１８Ａ，１８，１８Ｂをパターニングしてコ
ンタクトホール１７Ａを介してトランスファトランジス
タＡにつながるデジット線とか抵抗１４Ｂにコンタクト
ホール１７Ｂを介してつながる配線等を形成し、残りの
必要な工程をへてＳＲＡＭは完成する。An embodiment of the present invention will be described with reference to the drawings. Since the semiconductor device to be manufactured and its constituent parts are not different from those shown in FIGS. 1 and 1B, the drawings are shared. (1) The process up to the preparation of the intermediate workpiece shown in FIG. (2) After obtaining the structure shown in FIG. 1, a laminated film 18A of Ti / TiN is formed by sputtering as shown in FIG. T
i has a thickness of 0.08 μm and TiN has a thickness of 0.1 μm.
The TiN film is formed by sputtering Ti in an atmosphere containing N2 gas. (3) Next, annealing is performed in an N 2 atmosphere to allow Ti and Si to react to obtain a contact. Annealing conditions are lamp annealing, 620 ° C., and 60 seconds. (4) Thereafter, the Al film (Al
-Cu-Si) 18 and a TiN film 18B are sequentially formed, and these laminated films 18A, 18 and 18B are patterned, and a digit line connected to the transfer transistor A via the contact hole 17A or a resistor 14B via the contact hole 17B. An interconnect is formed, and the SRAM is completed through the remaining necessary steps.
【０００９】この実施例によればアニール温度を低くし
たのでポリシリコン膜にＴｉ／ＴｉＮ膜を良好にサイド
コンタクトさせることが出来る。According to this embodiment, since the annealing temperature is lowered, the Ti / TiN film can be favorably brought into side contact with the polysilicon film.
【００１０】[0010]
【発明の効果】以上説明したように、この発明の製造方
法によればポリシリコン膜でなる配線上に層間絶縁膜を
配し、層間絶縁膜にコンタクトホールを設けてその上に
下側にＴｉ／ＴｉＮ積層膜を有する上層配線を配するに
際してコンタクトホールがポリシリコン膜でなる配線を
貫通して形成されてサイドコンタクトとする場合にも安
定したコンタクトが得られる。As described above, according to the manufacturing method of the present invention, an interlayer insulating film is disposed on a wiring made of a polysilicon film, a contact hole is provided in the interlayer insulating film, and Ti When arranging an upper layer wiring having a / TiN laminated film, a stable contact can be obtained even when a contact hole is formed through a wiring made of a polysilicon film to serve as a side contact.
【図１】 この発明の一実施例および従来例の一工程を
示す断面図。FIG. 1 is a sectional view showing one embodiment of the present invention and one step of a conventional example.
【図２】 上に引き続く工程を示す断面図。FIG. 2 is a cross-sectional view showing a process subsequent to the above.
１ 半導体基板 ８ 第１の酸化膜（下層の層間絶縁膜） ９ 第１のＢＰＳＧ膜（下層の層間絶縁膜） １１ 第２の酸化膜（下層の層間絶縁膜） １４Ｂ 抵抗（ポリシリコン膜でなる配線） １５ 第３の酸化膜（上層の層間絶縁膜） １６ 第２のＢＰＳＧ膜（上層の層間絶縁膜） ７ ソース・ドレイン（活性領域） １７Ａ 活性領域に達するコンタクトホール（第１のコ
ンタクトホール） １７Ｂ 抵抗に向けてのコンタクトホール（第２のコン
タクトホール） １８Ａ Ｔｉ／ＴｉＮ積層膜 １８ Ａｌ−Ｃｕ−Ｓｉ膜（Ａｌを主とする膜）Reference Signs List 1 semiconductor substrate 8 first oxide film (lower interlayer insulating film) 9 first BPSG film (lower interlayer insulating film) 11 second oxide film (lower interlayer insulating film) 14B resistor (consisting of polysilicon film) 15) Third oxide film (upper interlayer insulating film) 16 2nd BPSG film (upper interlayer insulating film) 7 Source / drain (active region) 17A Contact hole reaching active region (first contact hole) 17B Contact hole for resistance (second contact hole) 18A Ti / TiN laminated film 18 Al-Cu-Si film (film mainly composed of Al)
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3205 H01L 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768
Claims (3)
し、 その上にポリシリコン膜でなる配線を形成し、 それを覆う上層の層間絶縁膜を形成し、 前記上層および下層の層間絶縁膜を貫通して半導体基板
表面の活性領域に達する第１のコンタクトホールと前記
上層の層間絶縁膜および前記配線をなすポリシリコン膜
を貫通する第２のコンタクトホールを同時にドライエッ
チングで形成し、 その上にＴｉ／ＴｉＮ積層膜を形成し、 アニール処理により前記Ｔｉ／ＴｉＮ積層膜を前記活性
領域に表面コンタクトさせると共に前記ポリシリコン膜
にサイドコンタクトさせる半導体装置の製造方法におい
て、 前記アニール処理の温度が６１０℃〜６３０℃であるこ
とを特徴とする半導体装置の製造方法。A lower interlayer insulating film is formed on a semiconductor substrate, a wiring made of a polysilicon film is formed thereon, an upper interlayer insulating film covering the wiring is formed, and the upper and lower interlayer insulating films are formed. A first contact hole penetrating the film and reaching the active region on the surface of the semiconductor substrate, and a second contact hole penetrating the upper interlayer insulating film and the polysilicon film forming the wiring are simultaneously formed by dry etching. A method of manufacturing a semiconductor device in which a Ti / TiN laminated film is formed thereon, and the Ti / TiN laminated film is brought into surface contact with the active region and side-contacted with the polysilicon film by annealing. 610 ° C. to 630 ° C., a method for manufacturing a semiconductor device.
なうランプアニール処理である請求項１に記載の半導体
装置の製造方法。2. The method according to claim 1, wherein the annealing is a lamp annealing performed in an N 2 gas atmosphere.
と共に前記Ｔｉ／ＴｉＮ積層膜をパターニングしてＡｌ
配線を形成する請求項１または２に記載の半導体装置の
製造方法。3. Thereafter, a film mainly composed of Al is formed, and the Ti / TiN laminated film is patterned together with the film.
3. The method according to claim 1, wherein the wiring is formed.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14548098A JP3252795B2 (en) | 1998-05-27 | 1998-05-27 | Method for manufacturing semiconductor device |
| KR1019990019057A KR100297143B1 (en) | 1998-05-27 | 1999-05-26 | Method for manufacturing semiconductor device |
| US09/320,971 US6117792A (en) | 1998-05-27 | 1999-05-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14548098A JP3252795B2 (en) | 1998-05-27 | 1998-05-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11340327A JPH11340327A (en) | 1999-12-10 |
| JP3252795B2 true JP3252795B2 (en) | 2002-02-04 |
Family
ID=15386239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14548098A Expired - Fee Related JP3252795B2 (en) | 1998-05-27 | 1998-05-27 | Method for manufacturing semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6117792A (en) |
| JP (1) | JP3252795B2 (en) |
| KR (1) | KR100297143B1 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6602125B2 (en) | 2001-05-04 | 2003-08-05 | Coinstar, Inc. | Automatic coin input tray for a self-service coin-counting machine |
| US7653599B2 (en) | 2002-02-15 | 2010-01-26 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US7865432B2 (en) | 2002-02-15 | 2011-01-04 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US8033375B2 (en) | 2002-02-15 | 2011-10-11 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US8874467B2 (en) | 2011-11-23 | 2014-10-28 | Outerwall Inc | Mobile commerce platforms and associated systems and methods for converting consumer coins, cash, and/or other forms of value for use with same |
| US8967361B2 (en) | 2013-02-27 | 2015-03-03 | Outerwall Inc. | Coin counting and sorting machines |
| US9022841B2 (en) | 2013-05-08 | 2015-05-05 | Outerwall Inc. | Coin counting and/or sorting machines and associated systems and methods |
| US9129294B2 (en) | 2012-02-06 | 2015-09-08 | Outerwall Inc. | Coin counting machines having coupon capabilities, loyalty program capabilities, advertising capabilities, and the like |
| US9594982B2 (en) | 2012-06-05 | 2017-03-14 | Coinstar, Llc | Optical coin discrimination systems and methods for use with consumer-operated kiosks and the like |
| US10346819B2 (en) | 2015-11-19 | 2019-07-09 | Coinstar Asset Holdings, Llc | Mobile device applications, other applications and associated kiosk-based systems and methods for facilitating coin saving |
| US10600069B2 (en) | 2010-11-01 | 2020-03-24 | Cardpool, Inc. | Gift card exchange kiosks and associated methods of use |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4677654B2 (en) * | 2000-04-19 | 2011-04-27 | 日本電気株式会社 | Transmission type liquid crystal display device and manufacturing method thereof |
| US7166904B2 (en) * | 2004-02-03 | 2007-01-23 | International Business Machines Corporation | Structure and method for local resistor element in integrated circuit technology |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521113A (en) * | 1995-03-16 | 1996-05-28 | United Microelectronics Corporation | Process for forming a butting contact through a gate electrode |
| US5945350A (en) * | 1996-09-13 | 1999-08-31 | Micron Technology, Inc. | Methods for use in formation of titanium nitride interconnects and interconnects formed using same |
-
1998
- 1998-05-27 JP JP14548098A patent/JP3252795B2/en not_active Expired - Fee Related
-
1999
- 1999-05-26 KR KR1019990019057A patent/KR100297143B1/en not_active IP Right Cessation
- 1999-05-27 US US09/320,971 patent/US6117792A/en not_active Expired - Lifetime
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6602125B2 (en) | 2001-05-04 | 2003-08-05 | Coinstar, Inc. | Automatic coin input tray for a self-service coin-counting machine |
| US7653599B2 (en) | 2002-02-15 | 2010-01-26 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US7865432B2 (en) | 2002-02-15 | 2011-01-04 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US8033375B2 (en) | 2002-02-15 | 2011-10-11 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US8229851B2 (en) | 2002-02-15 | 2012-07-24 | Coinstar, Inc. | Methods and systems for exchanging/transferring gift cards |
| US8332313B2 (en) | 2002-02-15 | 2012-12-11 | Coinstar, Inc. | Methods and systems for exchanging and/or transferring various forms of value |
| US10600069B2 (en) | 2010-11-01 | 2020-03-24 | Cardpool, Inc. | Gift card exchange kiosks and associated methods of use |
| US9799014B2 (en) | 2011-11-23 | 2017-10-24 | Coinstar Asset Holdings, Llc | Mobile commerce platforms and associated systems and methods for converting consumer coins, cash, and/or other forms of value for use with same |
| US8874467B2 (en) | 2011-11-23 | 2014-10-28 | Outerwall Inc | Mobile commerce platforms and associated systems and methods for converting consumer coins, cash, and/or other forms of value for use with same |
| US10716675B2 (en) | 2011-11-23 | 2020-07-21 | Coinstar Asset Holdings, Llc | Mobile commerce platforms and associated systems and methods for converting consumer coins, cash, and/or other forms of value for use with same |
| US11100744B2 (en) | 2011-11-23 | 2021-08-24 | Coinstar Asset Holdings, Llc | Mobile commerce platforms and associated systems and methods for converting consumer coins, cash, and/or other forms of value for use with same |
| US9129294B2 (en) | 2012-02-06 | 2015-09-08 | Outerwall Inc. | Coin counting machines having coupon capabilities, loyalty program capabilities, advertising capabilities, and the like |
| US9594982B2 (en) | 2012-06-05 | 2017-03-14 | Coinstar, Llc | Optical coin discrimination systems and methods for use with consumer-operated kiosks and the like |
| US8967361B2 (en) | 2013-02-27 | 2015-03-03 | Outerwall Inc. | Coin counting and sorting machines |
| US9022841B2 (en) | 2013-05-08 | 2015-05-05 | Outerwall Inc. | Coin counting and/or sorting machines and associated systems and methods |
| US9183687B2 (en) | 2013-05-08 | 2015-11-10 | Outerwall Inc. | Coin counting and/or sorting machines and associated systems and methods |
| US10346819B2 (en) | 2015-11-19 | 2019-07-09 | Coinstar Asset Holdings, Llc | Mobile device applications, other applications and associated kiosk-based systems and methods for facilitating coin saving |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11340327A (en) | 1999-12-10 |
| US6117792A (en) | 2000-09-12 |
| KR100297143B1 (en) | 2001-09-28 |
| KR19990088568A (en) | 1999-12-27 |
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