JP2846055B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a capacitor in a DRAM memory cell or the like.

(Prior Art) FIG. 2 shows a method of manufacturing a conventional DRAM (stacked) memory cell.

First, as shown in FIG. 2A, a thick field oxide film 2 is selectively formed on a surface portion of a silicon substrate 1 by a LOCOS method to perform element isolation. Next, a thin oxide film 3 serving as a gate insulating film is formed on the surface of the substrate 1, and a polysilicon 4 for forming a gate electrode is formed on the entire surface. This is doped with phosphorus using POCl ₃ as a diffusion source. Have conductivity. Next, anisotropic etching of the gate photolitho, the polysilicon 4 and the oxide film 3 is performed to form a gate electrode 4a and a gate insulating film 3a as shown in FIG. afterwards,
By arsenic ⁽⁷⁵ As ⁺⁾ of the gate electrode 4a as a mask ion implantation, forming a pair of diffusion layers 5a, 5b of the source and drain in the substrate 1. Thus, a MOS transistor as a transfer gate transistor is completed.

Next, as shown in FIG.
The D SiO ₂ film 6 is grown as a first interlayer insulating film. Then, a contact hole 7 is formed in the CVD SiO ₂ film 6 by photolithography and anisotropic etching on one of the diffusion layers 5a of the source and the drain. Thereafter, a polysilicon 8 for forming a charge storage electrode of a capacitor is formed on the entire surface including the inside of the contact hole 7, and
Doping phosphorus with Cl ₃ as a diffusion source to make it conductive,
The polysilicon 8 is patterned by photolithography as shown in FIG. 2B to form a capacitor charge storage electrode 8a electrically connected to the one diffusion layer 5a. Next, the charge storage electrode
A thin silicon nitride film 9 serving as a capacitor insulating film is formed on the entire surface including the surface of 8a, and a polysilicon 10 for forming a plate electrode of the capacitor is formed on the entire surface thereof. After doping the polysilicon 10 with phosphorus using POCl ₃ as a diffusion source to impart conductivity, the polysilicon 10 is patterned by photolitho etching as shown in FIG. Charge storage electrode 8a
A plate electrode 10a of the capacitor is formed on top of the silicon nitride film 9 (capacitor insulating film). At this time, the silicon nitride film 9 is simultaneously etched into the same pattern as the plate electrode 10a. Thus, the capacitor is completed.

Thereafter, as shown in FIG. 2 (c), a BPSG film 11 is grown on the entire surface of the substrate 1 as a second interlayer insulating film, and a flow for smoothing the surface is performed at about 900 ° C. Contact holes are formed in the BPSG film 11 and the CVD SiO ₂ film 6 by etching on the other diffusion layer 5b of the source / drain.
Open 12 Further, a bit line 13 connected to the other diffusion layer 5b through the contact hole 12 is formed by aluminum sputtering and photolithographic etching.

(Problems to be Solved by the Invention) However, in the above-described conventional manufacturing method, when the area of the charge storage electrode 8a is reduced along with the reduction in the area of the cell, a sufficient capacitor capacity can be obtained. However, there is a problem in that device characteristics such as hold time failure are deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which eliminates the above-described problem that the capacitor capacity cannot be sufficiently secured, and can obtain a large capacitor capacity even if the capacitor forming area is small.

According to the present invention, a charge storage electrode of a capacitor having a structure in which an impurity-doped polysilicon layer and an impurity non-doped polysilicon layer are stacked on each other with a thin silicon oxide film interposed therebetween is formed. The side surface of the charge storage electrode is selectively etched using impurity doping or non-doping, so that the side surface has an uneven structure.

(Operation) In the above invention, the surface area of the charge storage electrode can be increased by forming the side surface of the charge storage electrode with an uneven structure. Therefore, thereafter, a capacitor insulating film is formed on the entire surface of the charge storage electrode including the uneven side surface, and a plate electrode of the capacitor is formed so as to cover the entire surface. Capacitors can be formed.

The thin silicon oxide film between the polysilicon layers of the charge storage electrode is used to form a stacked structure of an impurity-doped polysilicon layer and an impurity non-doped polysilicon layer.
Although it acts as a mask to prevent diffusion of impurities from the impurity-doped polysilicon layer to the impurity non-doped polysilicon layer, it is unnecessary after the formation of the side surface irregularities,
For example, aggregation and destruction are performed by rapid annealing using a lamp, ion implantation of impurities, or heat treatment at a high temperature for a long time. As a result, the plurality of polysilicon layers are integrated. Further, the impurity is doped from the impurity-doped polysilicon layer to the impurity non-doped polysilicon layer by a high-temperature, long-time heat treatment, or a low-temperature heat treatment after rapid annealing or impurity ion implantation. As a result, the polysilicon layer of the charge storage electrode is entirely doped with impurities, and conductivity is imparted to the entire polysilicon layer.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. One embodiment is a case where the present invention is applied to a method of manufacturing a capacitor of a stacked memory cell of a DRAM. Of course, the present invention can be applied to other methods of manufacturing a capacitor.

First, as shown in FIG. 1A, a P-type silicon substrate 21 is formed.
A thick field oxide film 22 is selectively formed on the surface of the device by the LOCOS method to perform element isolation. Next, a thin oxide film 23 of 300 mm serving as a gate insulating film is formed on the surface of the substrate 21, and a polysilicon layer 24 for forming a gate electrode is further formed on the entire surface.
It is formed to a thickness of 2500 mm, and is doped with phosphorus using POCl ₃ as a diffusion source to have conductivity. Next, anisotropic etching of the gate photolitho, the polysilicon layer 24 and the oxide film 23 is performed to form a gate electrode 24a and a gate insulating film 23a as shown in FIG. Thereafter, the acceleration arsenic ⁽⁷⁵ AS ⁺⁾ of the gate electrode 24a as a mask voltage 40 KeV, dose 5E15ions /
By implanting ions in cm ² , the source
A pair of diffusion layers 25a and 25b as drains are formed. Thus, a MOS transistor as a transfer gate transistor is completed.

Next, as shown in FIG. 1B, a silicon oxide film 26 and a silicon nitride film 27 are grown on the entire surface of the substrate 21 as a first interlayer insulating film by 3000 .ANG. And this two-layer film 2
In steps 6 and 27, a contact hole 28 is opened on one of the source / drain diffusion layers 25a by photolithography and anisotropic etching.

Thereafter, the two-layer films 26 and 27 including the contact holes 28 are formed.
As shown in FIG. 1C, a polysilicon layer 29 is formed on the entire upper surface.
Is formed to a thickness of 1000 mm. Then, this polysilicon layer 29
Dose 1E16ions / cm ² of arsenic ⁽⁷⁵ As ^+), the accelerating voltage 40Ke
V ions are implanted, and a silicon oxide film 30 is formed on the surface of the polysilicon layer 29 by thermal oxidation to a thickness of 10 to 20 mm, and then a second polysilicon layer 31 is formed on the polysilicon layer 29.
Is formed to a thickness of 800 mm. Then, after a silicon oxide film 32 is formed to a thickness of 10 to 20 mm on the surface of the second polysilicon layer 31, a third polysilicon layer 33 is formed to a thickness of 800 mm on the second polysilicon layer 31. the third arsenic in the polysilicon layer 33 ⁽⁷⁵ As ⁺⁾ the dose 1E16ions / cm ^2, the accelerating voltage
Ion implantation is performed at 20 KeV, and a silicon oxide film 34 is
After being formed to a thickness of 0 °, a fourth polysilicon layer 35 is formed on this third polysilicon layer 33 to a thickness of 800 °. Here, when the polysilicon layers 29, 31, 33, and 35 are formed in a stacked structure, the silicon oxide films 30, 32, and 34 are converted from the arsenic-doped polysilicon layers 29 and 33 to non-doped polysilicon. It acts as a mask to prevent arsenic from diffusing into layers 31,35.

Next, as shown in FIG. 1 (d), a resist pattern 36 was formed on the laminated structure composed of the polysilicon layers 29, 31, 33, 35 and the silicon oxide films 30, 32, 34, and the resist pattern 36 was used as a mask. By patterning the laminated structure, the charge storage electrode 37 of the capacitor having the remaining pattern of the laminated structure is formed.

Thereafter, using the resist pattern 36 and the exposed silicon nitride film 27 as a mask, the side surfaces of the charge storage electrode 37 are wet-etched with a mixed solution of, for example, nitric acid (HNO ₃ ) and hydrofluoric acid (HF). Then, at this time, the polysilicon layers 29 and 33 doped with arsenic at a high concentration are etched about 5 to 10 times faster than the polysilicon layers 31 and 35 not doped with the impurities. electrode
The side surface of 37 has an uneven structure as shown in FIG.

Next, heat treatment is performed in a nitrogen atmosphere at 950 to 1000 ° C. for about 30 minutes. By this heat treatment, the silicon oxide films 30, 32, and 34 between the polysilicon layers 29, 31, 33, and 35 of the charge storage electrode 37 are aggregated and broken, and accordingly, the respective polysilicon layers 29, 31, 33, and 3
As shown in FIG. 1 (f), 5 is tightly integrated. In addition, arsenic diffuses from the arsenic-doped polysilicon layers 29 and 33 to the non-doped polysilicon layers 31 and 35, and the entire polysilicon layers 29, 31, 33, and 35 are doped with impurities to provide conductivity. Becomes

The coagulation / destruction and the impurity diffusion of the silicon oxide film can be performed by the following method. First of all,
Rapid annealing in nitrogen atmosphere at 1050-1100 ° C for 20 seconds (RT
A; Rapid Thermal Anneal or arsenic ( ⁷⁵
The as ⁺⁾ acceleration voltage 100 KeV, and ion-implanted at a dose 5E14ions / cm ² about the silicon oxide film 30, 32, 34 are aggregated, destroyed, after which subjected to about 30 minutes thermal treatment in a nitrogen atmosphere at 850 to 900 ° C. Then, arsenic is diffused from the polysilicon layers 29 and 33 into the non-doped polysilicon layers 31 and 35. According to this method, a heat treatment at a high temperature of about 1000 ° C. or more is not necessary for a short time, so that there is an advantage that the influence on the element can be reduced.

Next, as shown in FIG. 1 (f), a 100 nm thick silicon nitride film 38 serving as a capacitor insulating film is formed on the entire surface of the substrate 21 including the concave and convex side surfaces and the upper surface of the charge storage electrode 37 by a CVD method. Further, the charge storage electrode is sandwiched between the silicon nitride films 38.
A polysilicon layer 39 for forming a plate electrode of a capacitor is formed on the entire surface of the substrate 21 so as to cover 37 by a CVD method to a thickness of 2000 μm. Then, the polysilicon layer 39 is doped with phosphorus using POCl ₃ as a diffusion source to have conductivity. Thereafter, the polysilicon layer 39 is patterned by photolithography as shown in FIG. 1 (f) to leave a portion covering the charge storage electrode 37, thereby forming a capacitor plate electrode 39a. At this time, the silicon nitride film 38
Is also etched into the same pattern as the plate electrode 39a. Thus, a capacitor having a large capacity is completed by increasing the surface area of the charge storage electrode 37 by making the side surfaces of the charge storage electrode 37 uneven.

Thereafter, as shown in FIG. 1 (f), a BPSG film 40 as a second interlayer insulating film is grown to a thickness of 8000 mm over the entire surface of the substrate 21, and a flow for smoothing the surface is performed in a nitrogen atmosphere at 900 ° C. BPSG by photolitho etching
Film 40, silicon nitride film 27 and silicon oxide film 26
Next, a contact hole 41 is formed on the diffusion layer 25b. Further, a bit line 42 connected to the diffusion layer 25b through the contact hole 41 is formed by aluminum sputtering with a thickness of 7000 mm and photolithographic etching.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, the surface area of the charge storage electrode is increased by making the side surface of the charge storage electrode of the capacitor uneven, so that the capacitor formation area is small. It is possible to obtain a large capacitor capacity, and to prevent deterioration of device characteristics such as defective hold time in a DRAM memory cell, for example. Further, according to the manufacturing method of the present invention, the side surface of the charge storage electrode can be easily formed as described above by utilizing the difference in the etching rate of the polysilicon layer between the impurity doping and the non-doping, and the productivity is improved. Can be manufactured.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing a method of manufacturing a conventional stacked memory cell of a DRAM. 29, 31, 33, 35 ... polysilicon layer, 30, 32, 34 ... silicon oxide film, 37 ... charge storage electrode, 38 ... silicon nitride film, 39a ... plate electrode.

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 27/108 H01L 21/8242

Claims (1)

(57) [Claims] A step of forming a charge storage electrode of a capacitor having a structure in which an impurity-doped polysilicon layer and an impurity non-doped polysilicon layer are alternately stacked with a thin silicon oxide film interposed therebetween; A step of selectively etching the side surface by using impurity doping or non-doping, thereby forming the side surface with a concavo-convex structure; thereafter, the thin silicon oxide film between the polysilicon layers is aggregated and destroyed, and the impurity is doped. Doping an impurity from the polysilicon layer to the non-doped polysilicon layer, and thereafter forming a capacitor insulating film on the entire surface of the charge storage electrode and further forming a plate electrode of the capacitor so as to cover the entire surface A method for manufacturing a semiconductor device, comprising: