JPH0344068A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the area of a lower electrode, and increase the capacitance of a capacitor, by reflecting an uneven surface formed on the surface of a base oxide film, and forming a fine uneven surface on the surface of a polysilicon lower electrode of a capacitor. CONSTITUTION:An oxide film (BPSG film) 108 containing high concentration impurity is formed on a semiconductor substrate; said oxide film 108 is heat treated and deposition type particle is generated on the film surface, thereby forming fine unevenness on the oxide film surface. A contact hole 109 is bored by etching the BPSG film 108. Second layer polysilicon 110 is deposited on the whole surface of the BPSG film 108 containing the contact hole 109. The second layer polysilicon 110 is affected by the uneven surface of the base BPSG film 108, and the surface turns to a finely uneven surface. After that, impurity is introduced into the second layer polysilicon 110, which is heat-treated and patterned. Thereby the lower electrode of a stacked capacitor is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device.
Stack in transistor/1-capacitor type semiconductor dynamic random access memory (DRAM)
The present invention relates to a method for manufacturing a capacitor.

(Prior Art) In order to increase the density of DRAMs, many attempts have been made to increase the capacity of an information storage capacitor per unit cell area. For example, IEE Transactions on Electron Devices (I
EEE TRANSACTIONS 0NELECTR
ON nEvrcEs) ED-27(8) (198
0-8) As disclosed in P1596-1601, stacking capacitors on a field oxide film etc.
Stacked capacitors have been proposed to increase the capacitance, and are now becoming mainstream in capacitor structures for highly integrated DRAMs of 1 megabit or more.

FIG. 2 shows an example of a method for manufacturing a semiconductor device using a conventional stacked capacitor. This will be explained below with reference to FIGS. 2(A) to 2(E).

First, in FIG. 2(A), a channel stop layer 20 is formed by implanting impurity ions and selective oxidation into a P-type silicon substrate 201.
2, and a field oxide film 203 having a thickness of 600 nm has been formed.

Next, thermal oxidation is performed to form a gate oxide film 204 on the exposed surface of the substrate 201, and then the entire surface including the top is exposed to reduced pressure C.
A first layer polysilicon 205 with a film thickness of 300 nm is deposited by VD (chemical vapor deposition) method, and in order to give conductivity to this first layer polysilicon 205, 5XIO of phosphorus is deposited.
Next, a resist (not shown) is buttered on the first layer polysilicon 205, and using the resist as a mask, the first layer polysilicon 205 is doped with a plasma erature using CF4 gas. silicon 20
5 is etched as shown in FIG. 2(B). Furthermore, after removing the resist (not shown), the first layer polysilicon 2
05 as a mask, unnecessary portions of the gate oxide film 204 are removed with a hydrofluoric acid solution, as shown in FIG. 2(B).

This forms the gate electrode portion of the transfer gate transistor.

Next, using the first layer polysilicon 205 and field oxide film 203 as a mask, arsenic is applied to 6×IQIsCT11.
By implanting ions into the substrate 201 at a dose of about -2, the pair of N diffusion layers 206 as the source and drain of the transfer gate transistor are formed in the substrate in a self-aligned manner, as shown in FIG. 2(c). 201. Next, drive-in is performed in a dry oxygen atmosphere, and the junction depth of the N+ diffusion layer 206 is set to 0.2+ym.

At this time, a thermal oxide film 207 with a thickness of about 150 nm is formed on the exposed P-type silicon substrate 201 and first layer polysilicon 205, as shown in FIG. 2(c). Next, a resist (not shown) is patterned on the thermal oxide film 207 and the field oxide film 203, and a part of the thermal oxide film 207 is etched using a hydrofluoric acid solution or plasma elastomer using the resist as a mask.
A contact hole 208 for connecting one N diffusion layer 206 to a second layer of polysilicon, which will be described later, is shown in FIG.
As shown in c), holes are formed in the thermal oxide film 207.

Subsequently, after removing the resist (not shown), a second layer of polysilicon 209 is deposited to a thickness of 10° nl11 over the entire surface by low pressure CVD. After that, in order to make the second layer polysilicon 209 conductive, phosphorus was added to
After doping at a concentration of about 20 cm-'', this second layer polysilicon 209 is patterned in the same manner as the first layer polysilicon 205, and as shown in FIG. 2(D), it is patterned on the substrate 201. Only a predetermined portion is left as the lower electrode of the stacked capacitor.

Thereafter, a 20 nm thick silicon nitride film 21Cj as a dielectric of the capacitor is first applied to the entire surface including the lower electrode.
Next, 1100 nm of third layer polysilicon 211 as the upper electrode of the capacitor is deposited by low pressure CVD. After that, phosphorus was added to the third layer polysilicon 211 by 5X.
After doping at a concentration of about 10"cm-', the third layer polysilicon 211 and silicon nitride film 210 are buttered again in the same manner as the first layer polysilicon 205, and the second layer polysilicon 211 and silicon nitride film 210 are buttered.
As shown in Figure (E), only the remaining second layer polysilicon layer 209 is left to complete the stacked capacitor.

(Problem to be Solved by the Invention) However, in the conventional method as described above, as the degree of integration of elements increases, the capacitor area, that is, the surface area of the second layer polysilicon 209 (lower electrode) becomes smaller, making it difficult to create a sufficient capacitor. There was a problem that capacity could not be obtained.

So, The 20th 1988 Solid State
Devices and Materials (THE 20TH
19885OLID 5TATE DEVICES A
ND MATERIALS (SSDM)) P581~5
As disclosed in No. 84, the storage node (lower electrode), which was conventionally formed with a layer of polysilicon, is formed by stacking two layers of polysilicon to increase the surface area and increase the capacitance. There are some improvement examples using this method, but the process is complicated and a gap is formed horizontally on the side of the storage node, so when forming the capacitor insulating film and plate electrode (upper electrode) in the later process, It is difficult to uniformly form these films deep into the voids without defects such as voids, and it has not been possible to obtain a film that is technically satisfactory.

This invention solves the problem of the prior art in that a sufficient capacitor capacity cannot be obtained due to an increase in the degree of integration and a decrease in the capacitor area, without complicating the process. The present invention provides a method.

(Means for Solving the Problems) In the present invention, an oxide film containing impurities at a high concentration is formed on a semiconductor substrate, and the oxide film is heat-treated to generate precipitated particles on the film surface. By forming fine irregularities on the oxide film surface, depositing polysilicon on the oxide film, doping with impurities, and buttering,
A lower electrode of a capacitor having an uneven surface similar to the oxide film is formed.

(Function) When an oxide film containing a high concentration of impurities such as poron or phosphorus is heat-treated in a dry oxygen atmosphere,
Precipitated particles are generated on the film surface, and the oxide film surface becomes a finely uneven surface. Then, if polysilicon is deposited on this oxide film to form the lower electrode of the capacitor, the surface of the lower electrode (polysilicon) will become uneven due to the influence of the oxide film surface, making it possible to increase the surface area of the lower electrode. . Therefore, if a dielectric film and further an upper electrode are formed on this lower electrode to complete a star-sock capacitor, the capacitor capacitance per unit area can be increased.

Note that the unevenness caused by the precipitated particles does not have acute angles;
Therefore, the unevenness on the lower electrode does not have acute angles, and there is no concern that the life of the capacitor dielectric film will be shortened due to electric field concentration.

Further, the lower electrode polysilicon is doped with impurities to make it conductive, but if there is an oxide film containing impurities at a high concentration as an underlying layer, impurities can be introduced from this oxide film. In other words, no other impurity diffusion source film is required.

Regarding the generation of precipitated particles due to heat treatment of BPSG films, please refer to the ``Proceedings of the 48th Autumn 1988 Japan Society of Applied Physics Conference, P545 18a-Q10 r B
As disclosed in ``Influence of Heat Treatment on the Generation of Precipitated Particles on the PSG Film Surface''.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to process cross-sectional views of FIGS.

First, as shown in FIG. 1(2), a P-type silicon substrate 10
1, a channel stop layer 102 and a field oxide film 103 with a thickness of 600 nm are formed by ion implantation and selective oxidation.

Subsequently, a gate oxide film 104 having a thickness of 25 nm is formed on the exposed surface of the substrate 101 by performing thermal oxidation in a dry oxygen atmosphere at 950°C. Furthermore, a film with a thickness of 30 mm was applied to the entire surface including the top using low-pressure CVD (chemical vapor deposition).
A first layer polysilicon 105 with a thickness of 0 nm is deposited, and in order to give conductivity to this first layer polysilicon 105, 50% of phosphorus is added.
Dope at a concentration of about XIO"cm-3. Then,
A resist I~ (not shown) is patterned on the first layer polysilicon 105, and using the resist as a mask, the first layer polysilicon 105 is formed by plasma etching using CF and gas as shown in FIG. 1(2). Etching.

Furthermore, after removing the resist, the remaining first layer polysilicon 10
5 as a mask, unnecessary portions of the gate oxide film 104 are removed with a hydrofluoric acid solution as shown in FIG. 1(2).

As a result, the data 1 of the transfer gate transistor
-An electrode part is formed.

Next, using the remaining first layer polysilicon 105 and field oxide film 103 as a mask, arsenic was applied at 6×l OI 5
By implanting ions into the substrate 101 at a dose of cm -2 , a pair of N'' diffusion layers 106 as the source and drain of the transfer gate transistor are formed in a self-aligned manner as shown in FIG. 1(c). is formed in the substrate 101.Next, drive-in is performed at 900°C in a dry oxygen atmosphere to reduce the junction depth of the N diffusion layer 106 to 0.
．． 2pm. At this time, a film with a thickness of 15 mm was applied on the exposed P-type silicon substrate 101 and first layer polysilicon 105.
A thermal oxide film 107 of about 0 nm is formed.

Next, a BPSG film 108 containing boron as an impurity at a relatively high concentration of 1Qwt% or more is deposited to a thickness of 200 nm over the entire surface of the substrate 101, as shown in FIG. 1(d).

Next, heat treatment is performed in a dry oxygen atmosphere at 900°C to 950°C. This heat treatment generates fine precipitated particles on the surface of the BPSG film 108, and the surface of the BPSG film 10B becomes a finely uneven surface as shown in FIG. 1(e).

Here, the diameter and height of each precipitated particle are 0 and 5 t.
It is about tm or less.

Next, a resist that is not on top of this BPSG film 10 is patterned, and BPS is formed using this resist as a mask.
By etching a part of the G film 10B and the oxide film 107 using a hydrofluoric acid solution or plasma erasure, a contact hole is formed in these to connect one of the N+ diffusion layers 106 to the second layer polysilicon described later. A hole 109 is opened as shown in FIG. 1(f).

After that, after removing the resist, the contact hole 1 is
A second layer polysilicon 110 of 1100 nm is deposited on the BPSG film 10 film 0B containing 0B by the reduced pressure (/D method. Then, this second layer polysilicon 110 is affected by the uneven surface of the base BPSC film 108. As a result, the surface becomes similarly minutely uneven as shown in FIG. 1(f).

After that, in order to make this second layer polysilicon 110 conductive, phosphorus was added in a layer of 5 XIO" to 1 x 1020 cm.
Dope at a concentration of −3. This phosphorus doping step is generally performed by forming a phosphorus glass film on polysilicon and phosphorus diffusion from the film, but in this embodiment, since the BPSG film 108 exists under the second layer polysilicon 110,
The concentration of impurity phosphorus in this BPSG film 108 is set to 2'Ow.
% or more and heat treatment at about 800°C to 900°C, this BPSC; film 108
The second layer polysilicon 110 has low resistance due to the introduction of phosphorus from
It is also possible to form In that case, steps such as deposition of the phosphor glass film and removal after use become unnecessary, thereby simplifying the process.

Thereafter, this second layer polysilicon 110 is patterned in the same manner as the first layer polysilicon 105 to form a first layer polysilicon 110.
As shown in Figure (f), only two predetermined portions on the substrate 101 are left as the lower electrode of the stacked capacitor.

Thereafter, a silicon nitride film 111 is deposited to a thickness of 2Q nm over the entire surface including the lower electrode by low pressure CVD as a dielectric film of the capacitor. Subsequently, thermal oxidation is performed in a 950° wet oxygen atmosphere to form an oxide film (not shown) with a thickness of 2 to 4 nm on the silicon nitride film 111. As a result, the leakage current of the silicon nitride film 111 is significantly reduced. After that, on the dielectric film of the capacitor to which the oxide film has been added, a third layer of polysilicon 112 as the upper electrode of the capacitor is deposited using a low pressure CVD method.
Deposit to n thickness. After that, this third layer polysilicon 1
After doping 12 with phosphorus at a concentration of about 5×102° cm −3 , the third polysilicon layer 112 and the dielectric film (oxide film and silicon nitride film 111) are patterned again in the same manner as the first polysilicon layer 105. Then, as shown in FIG. 1(2), the stacked capacitor is completed by leaving only on the remaining second layer polysilicon 110.

Although not shown in the drawings, the intermediate insulating film, metal pattern for wiring, and protective insulating film are shaped using normal process technology.
A semiconductor device with a stacked capacitor structure is completed.

(Effects of the Invention) As described above, according to the manufacturing method of the present invention, the surface of the polysilicon lower electrode of the capacitor is formed into a finely uneven surface reflecting the uneven surface of the underlying oxide film. The surface area of the lower electrode can be increased, and thus the capacitance per unit area can be increased.

Moreover, the surface of the base oxide film is uneven due to precipitated particles that are generated when an oxide film containing a high concentration of impurities is heat-treated. Since the unevenness on the surface of the silicon lower electrode does not have acute angles, it is possible to prevent a reduction in the life of the capacitor dielectric film due to electric field concentration. In addition, if the base oxide film contains impurities at a high concentration, conductivity will be imparted to the polysilicon lower electrode by impurity diffusion from the base oxide film. Also, the process of removing the film after use becomes unnecessary, which is advantageous for workability. Furthermore, unlike other improved examples, the manufacturing method of the present invention does not increase or complicate the steps, and can be expected to improve productivity.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing a conventional method. 101...P-type silicon substrate, 108...BPSG
Film, 110... Second layer polysilicon, 111... Silicon nitride film, 112... Third layer polysilicon. 4 o'clock Y 扛 ears Ichitora' Yo row O craftsman's previous negative map 1st country

Claims (1)

[Claims] (2) a step of forming an oxide film containing a high concentration of impurities on a semiconductor substrate; (2) heat-treating the oxide film to generate precipitated particles on the film surface; (c) Depositing polysilicon on the oxide film, doping it with impurities, and patterning it to form a capacitor with an uneven surface similar to the oxide film. Manufacturing a semiconductor device comprising the steps of: forming a lower electrode; (d) forming a dielectric film of a capacitor on the lower electrode; and further forming an upper electrode of the capacitor with polysilicon thereon. Method.