JP2750159B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a stacked capacitor in a one-transistor one-capacitor semiconductor dynamic random access memory (DRAM).

(Prior Art) Conventionally, in order to increase the density of a DRAM, many attempts have been made to increase the capacitance of an information storage capacitor per unit cell area. For example, IEE Transactions on Electron Devices (IEEE
TRANSACTIONS ON ELECTRON DEVICES) ED-27 [8] (1
980-8) As disclosed in P1596 to 1601, a stacked capacitor in which a capacitor is stacked on a field oxide film or the like to increase the capacity has been proposed. It is becoming mainstream.

FIG. 2 shows an example of a conventional method for manufacturing a semiconductor device using a stacked capacitor. This will be described below with reference to FIGS. 2 (A) to 2 (E).

First, FIG. 2A shows that a channel stop layer 20 is formed in a P-type silicon substrate 201 by impurity ion implantation and selective oxidation.
Second, a field oxide film 203 having a thickness of 600 nm has been formed.

Subsequently, thermal oxidation is performed to form a gate oxide film 204 on the exposed surface of the substrate 201.
A 30 nm-thick first-layer polysilicon 205 is deposited by a (chemical vapor deposition) method, and phosphorus is added to the first-layer polysilicon 205 at a concentration of about 5 × 10 ²⁰ cm ⁻³ to impart conductivity to the first-layer polysilicon 205. Dope. Next, although not shown, a resist is patterned on the first-layer polysilicon 205, and the first-layer polysilicon 205 is shown in FIG. 2B by a plasma etcher using CF ₄ gas using the resist as a mask. Etching as follows. Further, after removing the resist (not shown), the first-layer polysilicon 205 is used as a mask, and FIG.
As shown in FIG. 7, unnecessary portions of the gate oxide film 204 are removed with a hydrofluoric acid solution. Thereby, a gate electrode portion of the transfer gate transistor is formed.

Then, arsenic is ion-implanted into the substrate 201 at a dose of about 6 × 10 ¹⁵ cm ⁻² using the first-layer polysilicon 205 and the field oxide film 203 as a mask, as shown in FIG. Then, a pair of N ⁺ diffusion layers 206 as a source and a drain of the transfer gate transistor are formed in the substrate 201 in a self-aligned manner. Next, drive-in is performed in a dry oxygen atmosphere to set the junction depth of the N ⁺ diffusion layer 206 to 0.2 μm. At this time, as shown in FIG. 2C, a thermal oxide film 207 having a thickness of about 150 nm is formed on the exposed P-type silicon substrate 201 and the first layer polysilicon 205. Next, a resist (not shown) is patterned on the thermal oxide film 207 and the field oxide film 203, and a part of the thermal oxide film 207 is etched with a hydrofluoric acid solution or a plasma etcher using the resist as a mask.
A contact hole 208 for making a connection between one N ⁺ diffusion layer 206 and a second-layer polysilicon, which will be described later, is formed in the thermal oxide film 207 as shown in FIG. 2C.

Subsequently, after removing the resist (not shown), a second-layer polysilicon 209 is deposited on the entire surface to a thickness of 100 nm by a low pressure CVD method. Thereafter, phosphorus is doped at a concentration of about 5 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 to impart conductivity to the second layer polysilicon 209, and then the second layer polysilicon 209 is added to the first layer polysilicon 209. Patterning is performed in the same manner as the polysilicon 205, and is left as a lower electrode of the stacked capacitor only at a predetermined portion on the substrate 201 as shown in FIG.

Thereafter, on the entire surface including the lower electrode, a silicon nitride film 210 as a dielectric of the capacitor is first formed to a thickness of 20 nm, and then a third layer polysilicon 211 as an upper electrode of the capacitor is formed.
Are deposited at a thickness of 100 nm by a low pressure CVD method. Thereafter, the third polysilicon layer 211 is doped with phosphorus at a concentration of about 5 × 10 ²⁰ cm ⁻³ , and then the third polysilicon layer 211 and the silicon nitride film 210 are formed again in the same manner as the first polysilicon layer 205. Patterning is performed, and is left only on the remaining second-layer polysilicon 209 as shown in FIG. 2E, thereby completing the stacked capacitor.

(Problems to be Solved by the Invention) However, in the conventional method as described above, when the degree of integration of the element increases, the capacitor area, that is, the surface area of the second-layer polysilicon 209 (lower electrode) decreases, and a sufficient capacitor There was a problem that the capacity could not be obtained.

The 20th 1988 SOLID STATE DEVICES & MATERIALS (THE 20TH 1988 SOLID
STATE DEVICES AND MATERIALS (SSDM)) As disclosed in pages 581 to 584, a storage node (lower electrode) conventionally formed of one layer of polysilicon is formed by stacking two layers of polysilicon. Increase the surface area,
Although there is an improvement example in which a large capacitance can be obtained, the process becomes complicated and a void is formed in the lateral direction on the side surface of the storage node. When forming these films, it is difficult to form these films uniformly without any defects such as voids up to the deep portion of the voids, and it has not been technically satisfactory.

SUMMARY OF THE INVENTION The present invention solves the problem that the conventional technology has a problem that a sufficient capacitance cannot be obtained due to an increase in the degree of integration and a decrease in the capacitor area without complicating the process. Is provided.

(Means for Solving the Problems) According to the present invention, an oxide film containing a high concentration of impurities is formed on a semiconductor substrate, and the oxide film is heat-treated to generate precipitation-type particles on the film surface. By forming fine irregularities on the surface of the oxide film, depositing polysilicon on the oxide film, and patterning, a lower electrode of the capacitor having the irregularities on the surface is formed similarly to the oxide film.

(Operation) When an oxide film containing a high concentration of impurities such as boron and phosphorus is heat-treated in, for example, a dry oxygen atmosphere, precipitation type particles are generated on the film surface, and the oxide film surface has fine irregularities. Become. If polysilicon is deposited on this oxide film to form the lower electrode of the capacitor, the surface of the lower electrode (polysilicon) becomes uneven due to the influence of the oxide film surface, and the surface area of the lower electrode increases. I can take it. Therefore, if a dielectric film and an upper electrode are formed on the lower electrode to complete a stacked capacitor, the capacitance per unit area can be increased.

In addition, the unevenness due to the precipitation type particles does not become acute, and therefore, the unevenness on the lower electrode does not become acute, and there is no fear that the life of the capacitor dielectric film is shortened due to electric field concentration.

The lower electrode polysilicon is doped with impurities in order to have conductivity. If the underlying oxide film contains impurities at a high concentration, impurities can be introduced from the oxide film. That is, no other impurity diffusion source film is required.

The generation of precipitated particles by heat treatment of the BPSG film is described in “Preliminary Proceedings of the 48th JSAP Autumn Meeting, 1987, P545 18a-Q-10,” for the generation of precipitated particles on the BPSG film surface. Effect of Heat Treatment ”.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the process sectional views of FIGS. 1 (a) to 1 (g).

First, as shown in FIG.
First, a channel stop layer 102 and a 600 nm-thick field oxide film 103 are formed by ion implantation and selective oxidation.

Subsequently, a gate oxide film 104 having a thickness of 25 nm is formed on the exposed surface of the substrate 101 by performing thermal oxidation in a dry oxygen atmosphere at 950 ° C. In addition, the entire surface including the upper part, low pressure CVD
A 300 nm-thick first-layer polysilicon 105 is deposited by a (chemical vapor deposition) method, and phosphorus is added to the first-layer polysilicon 105 at a concentration of about 5 × 10 ²⁰ cm ⁻³ to impart conductivity to the first-layer polysilicon 105. Dope. Next, a resist (not shown) is patterned on the first-layer polysilicon 105, and the first-layer polysilicon 105 is formed as shown in FIG. 1B by a plasma etcher using CF ₄ gas using the resist as a mask. Etch. Further, after the resist is removed, unnecessary portions of the gate oxide film 104 are removed with a hydrofluoric acid solution using the remaining first layer polysilicon 105 as a mask, as shown in FIG. 1B.
Thereby, a gate electrode portion of the transfer gate transistor is formed.

Then, by ion implantation into the substrate 101 at a dose of residual first polysilicon layer 105 and the field oxide film 103 as a mask, arsenic 6 × 10 ¹⁵ cm ^-2, as shown in FIG. 1 (c) Next, a pair of N ⁺ diffusion layers 106 as a source and a drain of the transfer gate transistor are formed in the substrate 101 in a self-aligned manner. Next, drive-in is performed in a dry oxygen atmosphere at 900 ° C. to set the junction depth of the N ⁺ diffusion layer 106 to 0.2 μm. At this time, the film thickness is formed on the exposed P-type silicon substrate 101 and the first layer polysilicon 105.
A thermal oxide film 107 of about 150 nm is formed.

Next, a BPSG film 108 containing a relatively high concentration of impurity boron of 10 wt% or more is deposited on the entire surface of the substrate 101 to a thickness of 200 nm as shown in FIG.

Next, heat treatment is performed in a dry oxygen atmosphere at 900 ° C to 950 ° C. Due to this heat treatment, fine precipitation type particles are generated on the surface of the BPSG film 108, and the surface of the BPSG film 108 becomes a fine uneven surface as shown in FIG. Here, the diameter and height of each precipitation type particle are about 0.5 μm or less.

Next, a resist (not shown) is patterned on the BPSG film 108, and the BPSG film 108 is
And a part of the oxide film 107 are etched by a hydrofluoric acid solution or a plasma etcher, thereby forming a contact hole 109 for making a connection between one N ⁺ diffusion layer 106 and a second-layer polysilicon described later. Open holes as shown in FIG. 1 (f).

Then, after removing the resist, the contact hole is removed.
A second-layer polysilicon 110 is deposited to a thickness of 100 nm on the entire surface of the BPSG film 108 including the 109 by a low pressure CVD method. Then, this second
As shown in FIG. 1 (f), the surface of the layer polysilicon 110 is also minutely uneven, as affected by the uneven surface of the base BPSG film.

Then, since to have conductivity to the second layer polysilicon 110 is doped at a concentration of from 5 × 10 ¹⁹ no phosphorus 1 × 10 ²⁰ cm ^-3. This phosphorus doping step is generally performed by forming a phosphorus glass film on polysilicon and diffusing phosphorus from the film. In this embodiment, since the BPSG film 108 exists under the second layer polysilicon 110, this BPSG The concentration of impurity phosphorus in the film 108 is set to a high concentration of 20 wt% or more,
By performing the heat treatment to the extent, it is possible to form the low-resistance second-layer polysilicon 110 by introducing phosphorus from the BPSG film 108. In that case, the steps of depositing the phosphorus glass membrane and removing it after use are unnecessary, and the steps are simplified.

Thereafter, the second-layer polysilicon 110 is patterned in the same manner as the first-layer polysilicon 105, and the lower electrode of the stacked capacitor is formed only on a predetermined portion of the substrate 101 as shown in FIG. Leave as.

Thereafter, a silicon nitride film 111 is deposited as a dielectric film of a capacitor to a thickness of 20 nm on the entire surface including the lower electrode by a low pressure CVD method. Subsequently, thermal oxidation is performed in a 950 ° wet oxygen atmosphere to form an oxide film (not shown) having a thickness of 2 to 4 nm on the silicon nitride film 111. Thereby, the leakage current of the silicon nitride film 111 is significantly reduced. Thereafter, on the dielectric film of the capacitor to which the oxide film has been added, a third-layer polysilicon 112 as an upper electrode of the capacitor is deposited to a thickness of 100 nm by a low pressure CVD method. Thereafter, phosphorus is applied to this third layer polysilicon 112 at 5 × 10 ²⁰ cm ^−3.
After doping at about the same concentration, the first layer polysilicon 10
The third-layer polysilicon 112 and the dielectric film (oxide film and silicon nitride film 111) are patterned in the same manner as in step 5, and are left only on the remaining second-layer polysilicon 110 as shown in FIG. 1 (g). Thus, a stacked capacitor is completed.

Although not shown, an intermediate insulating film, a metal pattern for wiring, and a protective insulating film are formed by a normal process technique to complete a semiconductor device having a stacked capacitor structure.

(Effects of the Invention) As described above, according to the manufacturing method of the present invention, the surface of the polysilicon lower electrode of the capacitor is formed into a similar fine uneven surface by reflecting the uneven surface of the underlying oxide film. The surface area of the lower electrode can be increased, and thus the capacitance of the capacitor per unit area can be increased. In addition, the surface of the underlying oxide film is uneven due to precipitation type particles generated when the oxide film containing impurities at a high concentration is heat-treated. In this case, the unevenness of the surface of the oxide film, and in Since the irregularities on the surface of the silicon lower electrode are not sharp, it is possible to prevent the life of the capacitor dielectric film from being shortened due to electric field concentration. Also, if the underlying oxide film contains impurities at a high concentration, conductivity can be given to the polysilicon lower electrode by impurity diffusion from the underlying oxide film, so that formation of another film such as phosphorus glass as an impurity diffusion source can be performed. A step of removing the film after use is not required, which is advantageous for workability. Furthermore, the manufacturing method of the present invention does not require additional steps and complications as in the other improved examples, and can be expected to improve productivity.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing a conventional method. 101 ... P-type silicon substrate, 108 ... BPSG film, 110 ... Second layer polysilicon, 111 ... Silicon nitride film, 112 ... Third layer polysilicon.

Claims (1)

(57) [Claims] (A) a step of forming an oxide film containing impurities at a high concentration on a semiconductor substrate; and (b) a heat treatment of the oxide film to generate precipitation type particles on the film surface, thereby oxidizing the oxide film. (C) depositing polysilicon on the oxide film and patterning the same to form a lower electrode of a capacitor having irregularities on the surface similarly to the oxide film. And (d) forming a dielectric film of the capacitor on the lower electrode, and further forming an upper electrode of the capacitor with polysilicon thereon.