JPH05343422A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To reduce a junction resistance between source and drain regions by forming a side wall spacer at the side surface of a polycrystalline silicon wiring layer in the width narrower than the width of the side wall spacer of the side surface of a gate electrode. CONSTITUTION:A side wall spacer 109 at the side surface of a polycrystalline silicon wiring layer 105 is formed narrower than the width of a side wall spacer at the side surface of a gate electrode. Since junction between a buried contact layer 107 and souce, drain region 110 by high concentration N type impurity is carried out without through souce, drain region 108 by a low concentration N type impurity, a junction resistance can be reduced. Thereby, cell operation of a semiconductor storage device having the junction between the buried contact layer and souce, drain region of a MOS transistor provided adjacent thereto within the storage cell can be stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor, and more particularly to a semiconductor device having a buried contact layer and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device having a MOS transistor having a buried contact layer and a sidewall spacer on a silicon substrate is as follows. As shown in FIG. 2, a silicon oxide film 202 is formed on the silicon substrate 201. Next, using photoresist, the photoresist is removed only in the region where the buried contact layer is to be formed, and the silicon oxide film 202 is removed using the photoresist as a mask to form the opening 203. After removing the photoresist, polycrystalline silicon is deposited and a first conductivity type impurity is introduced into the polycrystalline silicon by a thermal diffusion method. Next, patterning is performed using a photoresist, and the polycrystalline silicon is removed using the photoresist as a mask to form a polycrystalline silicon wiring layer 204 that is bonded to the silicon substrate through the opening and a gate electrode 205 of a MOS transistor. Form. Then by thermal annealing,
Impurities of the first conductivity type in the polycrystalline silicon layer are introduced into the silicon substrate 201 through the opening 203 to form a buried contact layer 206. Next, by using the polycrystalline silicon wiring layer 204 and the gate electrode 205 of the MOS transistor as a mask, ion implantation is performed to form the source / drain regions 207 of the MOS transistor by a low concentration first conductivity type impurity.

Next, a silicon oxide film is deposited and sidewall spacers 208 are formed by a method such as anisotropic dry etching. Finally, by ion implantation using the polycrystalline silicon wiring layer 204, the gate electrode 205 of the MOS transistor, and the sidewall spacer 208 as a mask, the MOS with the high-concentration first conductivity type impurity is formed.
The source and drain regions 209 of the type transistor are formed.

[0004]

When a MOS type transistor having a buried contact layer and a sidewall spacer is formed on a silicon substrate by the above-mentioned process, the MOS transistor is formed in the process of forming the sidewall spacer 208. Type transistor gate electrode 2
05, the sidewall spacers 208 are formed not only on the polycrystalline silicon wiring layer 204 but also on the polycrystalline silicon wiring layer 204. Therefore, the buried contact layer 206 and the source / drain regions 209 of the MOS type transistor due to the high-concentration first conductivity type impurity are formed under the sidewall spacers 208 formed on the side surfaces of the polycrystalline silicon wiring layer 204. Junctions are made through the source / drain regions 207 of the MOS type transistor due to the low-concentration first conductivity type impurity. Therefore, a high resistance is loaded on the above-mentioned joint portion.

Therefore, the buried contact layer 206 and the M due to the high concentration of the first conductivity type impurities are formed.
In a semiconductor memory device having a junction between the source and drain regions 209 of an OS transistor in a memory cell, the operation of the cell becomes unstable.

In order to reduce the resistance of the junction, the buried contact layer 206 is formed in the semiconductor substrate 20.
In the step of forming No. 1, a method in which the buried contact layer 206 is deeply diffused by high-temperature thermal annealing and is directly bonded without the source / drain region 207 of the MOS transistor by the low-concentration first conductivity type impurity. However, when trying to miniaturize the device, high-temperature thermal annealing has an adverse effect on the miniaturization of the device.

Therefore, in the present invention, the process temperature is reduced and the junction resistance of the buried contact layer and the source and drain regions of the MOS transistor formed adjacent to the buried contact layer is reduced. ..

[0008]

The semiconductor device of the present invention comprises:
A semiconductor wiring layer containing impurities of the first conductivity type on a surface of the semiconductor substrate; a buried contact layer containing impurities of the first conductivity type diffused into the semiconductor substrate by thermal diffusion from the semiconductor wiring layer containing impurities of the first conductivity type; And M having sidewall spacers adjacent to the buried contact layer
In a semiconductor device including an OS transistor, the sidewall spacer formed in the semiconductor wiring layer containing the first conductivity type impurity is narrower than the sidewall spacer formed in the gate electrode of the MOS transistor. It is characterized by

Further, the gate electrode of the MOS transistor has a laminated structure of the semiconductor wiring layer containing at least a first conductivity type impurity and a semiconductor thin film different from the semiconductor wiring layer.

[0010]

[Embodiment] Next, one embodiment of the present invention will be described in detail with reference to element cross-sectional views in each manufacturing process.

FIG. 1D is a sectional view of the final step of a buried contact layer formed by applying the present invention and a MOS transistor formed adjacent to the buried contact layer. In the figure, 101 is a P-type silicon substrate, 102 is a silicon oxide film layer, 103 is a lower gate electrode, 104 is an opening, 105 is a polycrystalline silicon wiring layer, 106 is an upper gate electrode, 107 Is a buried contact layer, 108 is a source / drain region of low concentration N-type impurity, 109 is a sidewall spacer, and 110 is a source / drain region of high concentration N-type impurity.

First, on a P-type semiconductor substrate having a specific resistance of 10 to 100Ω, in an oxidizing atmosphere at 1000 ° C. for 20 minutes, 20
A silicon oxide film layer 102 having a thickness of about nm is formed. Then C
Polycrystalline silicon is deposited to a thickness of about 100 to 300 nm by the VD method, a photoresist is applied, the photoresist is patterned by the projection exposure method, and dry etching is performed to form the lower gate electrode 103. Next, after applying a photoresist and patterning the photoresist using a projection exposure method, the silicon is subjected to wet etching for about 10 to 200 seconds with a mixed solution having a ratio of HF and H ₂₀ of 1:10, for example. The oxide film layer 102 is removed and an opening 104 is formed. This state is shown in FIG.

Next, the polycrystal silicon 10
Deposit about 0 to 300 nm. After that, phosphorus is diffused in the polycrystalline silicon by thermally diffusing in an atmosphere such as POCl ₃ . Then, after applying a photoresist, the photoresist is patterned by a projection exposure method and dry-etched to form a polycrystalline silicon wiring layer 105 and an upper gate electrode 106. This state is shown in FIG. In the following, the lower gate electrode 103 and the upper gate electrode 10 will be described.
6 are combined to form a gate electrode.

Next, by thermal annealing at about 800 to 900 ° C., phosphorus of the polycrystalline silicon wiring layer 105 is introduced into the P-type silicon substrate 101 through the openings to form a buried contact layer 107. Next, the gate electrode and the polycrystalline silicon wiring layer 10 are formed by an ion implantation method.
5 as a mask, for example, phosphorus with an energy of 40 to 200 Ke
By implanting V at about 1 × 10 ¹¹ to 1 × 10 ¹⁴ / cm ² , the source / drain regions 108 are formed by the low concentration N-type impurity. This state is shown in FIG.

Next, a silicon oxide film is formed by CVD to 1
A sidewall spacer 109 is formed on the side surface of the gate electrode and the side surface of the polycrystalline silicon wiring layer 105 by depositing about 00 nm to 1000 nm and performing anisotropic etching. Here, the width of the sidewall spacer 109 is formed narrower than the width of the sidewall spacer on the side surface of the gate electrode due to the difference in film thickness between the gate electrode and the polycrystalline silicon wiring layer 105.

Finally, with the gate electrode, the polycrystalline silicon wiring layer 105, and the sidewall spacers 109 as masks, for example, arsenic energy of 40 to 40 is applied.
By implanting 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ^{2 at} 100 KeV, the source / drain regions 110 are formed by the high concentration N-type impurity. This state is shown in FIG.

In the present invention, the gate electrode of the MOS transistor is formed of a two-layer structure of a polycrystalline silicon film,
Moreover, the polycrystalline silicon wiring 105 layer forming the buried contact layer 107 and the gate electrode upper layer portion of the MOS type transistor are formed in the same layer.
The gate electrode of the OS type transistor is not limited to two layers and may be any number of layers. The layer forming the gate electrode may be a stack of any semiconductor layers as long as it is not an insulating film layer. Further, the M layer is formed in the same layer as the polycrystalline silicon wiring layer 105 forming the buried contact layer 107.
The gate electrode of the OS transistor may form any layer in the electrode.

In the embodiment of the present invention, the width of the side wall spacer on the side surface of the polycrystalline silicon wiring layer 105 is narrower than the width of the side wall spacer on the side surface of the gate electrode. However, depending on conditions such as the ratio of the film thickness difference between the gate electrode and the polycrystalline silicon wiring layer 105 and the over-etching time in anisotropic etching, the sidewall spacers on the side surfaces of the polycrystalline silicon wiring layer 105 may be used. Can be completely eliminated.

In the embodiment of the present invention, the MO
Only the case where the gate electrode of the S-type transistor has a laminated structure is described, but even when the gate electrode of the MOS transistor is formed in the same layer as the polycrystalline silicon wiring layer, a photoresist or the like is used. By using the MOS type transistor as a mask and etching the side wall spacer formed on the side surface of the polycrystalline silicon wiring layer, the width of the side wall spacer on the side surface of the polycrystalline silicon wiring layer is set to the side surface of the gate electrode. It is possible to realize the semiconductor device of the present invention in which the sidewall spacer is formed narrower than the width of the sidewall spacer.

[0020]

As described above, according to the semiconductor device of the present invention, the sidewall spacer on the side surface of the polycrystalline silicon wiring layer 105 is formed narrower than the width of the sidewall spacer on the side surface of the gate electrode. The junction between the buried contact layer 107 and the source / drain region 110 made of the high-concentration N-type impurity is the source / drain region 108 made of the low-concentration N-type impurity.
Therefore, the junction resistance decreases. As a result, the cell operation of the semiconductor memory device having the junction between the buried contact layer and the source and drain regions of the MOS transistor adjacent to the buried contact layer in the memory cell is stabilized. Further, the thermal diffusion temperature at the time of forming the buried contact layer does not need to be raised as in the conventional manufacturing method, so that there is a great effect that the element can be miniaturized.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing an embodiment of the present invention.

FIG. 2 is a plan view showing a multilayer wiring structure of a conventional semiconductor device.

[Explanation of symbols]

101 ... P-type silicon substrate 102, 202 ... Silicon oxide film layer 103 ... Lower gate electrode 104, 203 ... Opening portion 105, 204 ... Polycrystalline silicon wiring layer 106 ... Upper-layer gate electrodes 107, 206 ... Embedded contact layer 108 ... Source with low-concentration N-type impurities, drain regions 109, 208 ... Sidewall spacer 110 ... Source with high-concentration N-type impurities, Drain region 201 ・ ・ ・ Silicon substrate 205 ・ ・ ・ Gate electrode 207 ・ ・ ・ Source and drain region 209 with low concentration first conductivity type impurities ・ ・ ・ Source and drain region 209 with high concentration first conductivity type impurities

Claims (3)

[Claims] 1. A semiconductor wiring layer containing an impurity of a first conductivity type and a first conductivity type impurity diffused into the semiconductor substrate by thermal diffusion from a semiconductor wiring layer containing an impurity of the first conductivity type on a surface of a semiconductor substrate. In a semiconductor device including a MOS transistor having a buried contact layer including a sidewall spacer and a sidewall spacer adjacent to the buried contact layer, the sidewall spacer formed in the semiconductor wiring layer including the first conductivity type impurity is MO
A semiconductor device characterized by being narrower than the width of the sidewall spacer formed on the gate electrode of the S-type transistor. 2. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein a gate electrode of the MOS transistor has a laminated structure of the semiconductor wiring layer containing at least a first conductivity type impurity and a semiconductor thin film different from the semiconductor wiring layer. 3. A multi-layer on a semiconductor substrate with a gate insulating film interposed therebetween.
MOS transistor having a gate electrode having a laminated structure of
A transistor and a pad adjacent to the MOS transistor
A method of manufacturing a semiconductor device having only a contact layer, comprising:
Form at least one thin film layer and the wiring layer on the buried contact layer in the same layer.
Forming, a gate electrode of the MOS type transistor, and the filling
Simultaneously pattern the wiring layer on the embedded contact layer
And the step of forming a buried contact layer by thermal diffusion
And a gate electrode of the MOS transistor and the embedding
Sidewall spaces on the sides of the wiring layer on the contact layer
And a semiconductor forming process.
Device manufacturing method.