JP3176422B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as a highly integrated DRAM or SRAM and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a highly integrated DRAM, the height of a capacitor electrode tends to increase in order to secure a storage capacity. Since the capacitor is formed only in the memory cell and not in the peripheral circuit portion, the height difference between the memory cell region and the peripheral circuit region increases. On the other hand, with high integration or miniaturization, the width of the wiring traversing from the memory cell area to the peripheral circuit area is inevitably reduced,
The margin of depth of focus at the time of exposure for forming a wiring pattern is reduced, and in addition to this, the increase in the height difference further reduces the margin.

Regarding this phenomenon, the present inventor has disclosed in Japanese Patent Application No.
285088. The present inventor has proposed in the above-mentioned application a method of designing a memory cell so as to match a margin of focus of an exposure apparatus. However, in this method, since the ECC is used to suppress the α-ray soft error, a reduction in operation speed due to this is inevitable.

On the other hand, Owada described "SEMICONDUCTOR WORLD", 1
The February issue, 1991, p186, points out that it is important to reduce the absolute step in the case of multilayer wiring technology, especially in the case of logic ICs. This is a problem common to the height difference between the memory cell and the peripheral circuit. However, in the case of a logic IC, since a height difference is generated by random wiring, the distribution of the height difference is much more complicated than in the case of a memory. However, the above document does not mention the solution.

[0005] Generally, as a method of flattening a wiring step, a process shown in FIGS. 1A to 1C is known (for example, Solid State Technology, Nov. 1991, p67-7).
1). First, as shown in FIG. 1A, after a wiring 11 is formed on a substrate 10, an insulating film 12 is formed thereon and covered. The formed insulating film 12 is in a state in which a portion where the distance between the wirings 11 is small is higher than a portion where the distance between the wirings 11 is large. In this state, the resist pattern 1
Form 3 Next, as shown in FIG. 1B, by etching the insulating film 12 using the resist 13 as a mask, the height of the resist 13 in a portion where the distance between the wirings 11 is small is reduced. At this time, if the amount of etching is too large, an abnormal step is generated. Conversely, if the amount of etching is small, planarization becomes insufficient, so that control of etching is important. Finally, as shown in FIG. 1C, after the resist 13 is removed, an upper insulating film 14 is formed, and the planarization required for forming the upper wiring is completed.

Here, as the insulating films 12 and 14, S
Using a composite film of OG (spin-on-glass) and a CVD oxide film is much more effective than using a CVD oxide film alone. As another method, a method of completely flattening wiring steps by combining a special polymer or a film with an etch-back is known (for example, Numazawa et al., Proceedings of SEMI Technology Symposium, p245-2).
55 or D. Wang et al., Proceedings, p257-265).

[0007] However, in the above-mentioned conventional technology, since it is intended to cope with all the height differences of a complicated pattern caused by random wiring, there is a great problem in etching control. That is, the need for extremely high-precision etching control, the use of a special polymer or the like is not only disadvantageous in itself, but also requires further etching control such that it does not remain, and the need for etch-back. In such a case, etching control for simultaneously etching different materials is also required.

Further, since a material having a low melting point, such as Al, is mainly used for the wiring, an extremely strict restriction is imposed on the heat treatment temperature. As described above, complete flattening of wiring is an extremely difficult technical problem, and the fact is that it is still under research and development, and it cannot be practically applied to a memory or the like as it is.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device such as a DRAM or an SRAM which crosses a memory cell region even if the height of the memory cell region is large and a large step is formed between the memory cell region and a peripheral circuit region. It is an object of the present invention to provide a structure of a semiconductor device and a method of manufacturing the same, which enable sufficient planarization for highly accurately patterning an upper wiring to be formed.

[0010]

A first means for achieving the above object is a semiconductor device having the following structure. The semiconductor device of the present invention includes a first element region, a second element region, and a boundary region between the first element region and the second element region on a semiconductor substrate, and at least some of the elements formed in the first element region are the first element region. An extending portion formed higher than an element formed in the two element region, wherein a part of the layer formed in the first element region extends to the boundary region;
A first insulating film covering a part of the extending portion and the second element region; and a second insulating film covering at least the extending portion. The surface of the insulating film formed by overlapping the second insulating film is substantially flat. Alternatively, the following configuration may be used. A first element region, a second element region, and a boundary region between the first and second element regions on the semiconductor substrate, and an extension part in which a part of the first element region extends to the boundary region; A first insulating film covering a part of the extending portion and the second element region; a second insulating film covering the first insulating film and the extending portion; Having a through-hole opened through the insulating film, and a conductive film electrically connected to the other through the through-hole and extending from the first element region to the second element region. Features.

The second means is a method of manufacturing a semiconductor device, and has, for example, the following structure. In the method of manufacturing a semiconductor device according to the present invention, a circuit element portion is formed on a semiconductor substrate at a height higher than the periphery, and a part of the circuit element portion extends outside the circuit element portion. Forming a first insulating film so as to cover the entire substrate including the circuit element portion and the extending portion; and then forming at least an end of the extending portion. Etching the first insulating film using a mask formed so as to cover the first insulating film above and not to cover the first insulating film over the circuit element portion; And a step of forming a second insulating film over the entire surface of the remaining structure up to the step, thereby flattening the surface.

According to the above-described structure, first, it is possible to easily planarize an interlayer insulating film without having a coating insulating film having a problem that moisture-containing gas is released as a gas during firing. Since the reflow time can be greatly reduced as compared with the flattening by the normal CVD insulating film reflow, the heat history can be shortened and the problem of thermal stress can be avoided. Furthermore, a small thermal history also prevents unnecessary thermal diffusion of impurities in the CVD insulating film into the conductive film, so that an improvement in reliability can be expected. If the silicon nitride film is used as the extension formed to extend from the memory cell portion, the silicon nitride film can be expected to function as a barrier for preventing diffusion of impurities due to heat, and the above-described effect is promoted. Further, at the time of etching for removing an extension portion (for example, a first conductor film) formed to extend from the memory cell portion by removing the first insulating film, the first conductor If the film functions as an etch stopper, the end point of the etching can be easily detected.

[0013]

A boundary region is provided between the memory cell region on the substrate and its peripheral circuit region, and the first conductor film covers the entire memory cell region from the boundary region. The first insulating film covers from a part of the portion on the region to the entire peripheral circuit region. That is, the first insulating film exists in the peripheral circuit region and in the portion of the boundary region near the peripheral circuit region, and does not exist in the memory cell region and in the portion of the boundary region near the memory cell region. Thereby, the height of the substrate region surrounding the memory cell region is increased by the thickness of the first insulating film, and the difference in height between the capacitor and the like formed in the memory cell region and the periphery thereof is canceled. Therefore, the thickness of the first insulating film is set to a thickness corresponding to the height of a capacitor or the like formed in the memory cell region. The presence of the second insulating film covering the first insulating film and the portion of the first conductive film where the first insulating film does not exist cancels the step due to the large memory cell, and achieves desired flattening. To achieve. Since the first insulating film does not exist and the capacitor and the like are not formed in a portion of the boundary region near the memory cell region, the portion is depressed from the surroundings before the second insulating film is formed. It is necessary to set the size of the boundary region so that the depression is sufficiently filled with the second insulating film.

Typically, a memory cell includes a transfer transistor and a capacitor. In the method of manufacturing a semiconductor device according to the present invention, the first region and the second region are formed on the semiconductor substrate.
A region and a boundary region therebetween are defined, a first element is formed in the first region and the second region, and a second element is formed only in the first region. Typically, the first element is a small element such as a MOS transistor, and the second element is a large element such as a capacitor.

A first conductor film extending from the first region to the boundary region is formed. Typically, the first conductor film is formed as one electrode of a capacitor. First on the entire surface of the substrate
After forming the insulating film, a portion of the first insulating film covering the first region is removed to expose the first conductor film. In this step, the etching for removing the first insulating film includes:
Since the end point is easily controlled by the first conductor film, no complicated etching control is required. This is one major advantage of the method of the present invention.

It is desirable that a third insulating film having an etching characteristic different from that of the first insulating film is laminated on the first conductor film. As the material of the third insulating film, a material is selected that does not cause an undesired substance to diffuse into the first insulating film by heating for reflow of the first and second insulating films. Thereby, in the step of exposing the first conductive film by removing the first insulating film, the end point of the etching can be easily detected by the third insulating film on the first conductive film, and the third insulating film on the first conductive film can be easily detected by heating at the time of reflow. The first insulating film and / or the second insulating film may function as a protective film that prevents undesired substances from diffusing into the first insulating film.

In the present invention, typically, a first conductor film is formed by laminating a polycrystalline silicon film and a silicon nitride film in this order, and the first and second insulating films contain impurities. Forming a silicon oxide film, removing a portion of the first insulating film covering the first region by etching with a solution containing hydrofluoric acid to expose the first conductor film,
The first and second insulating films are reflowed by performing a heat treatment after the formation of the second insulating film.

In the case of a memory, the difference in elevation occurs only between the memory cell area and the peripheral circuit area, so that the pattern is relatively simple. loose. In the present invention, the problem at the time of flattening the wiring is solved by utilizing this fact. In a preferred embodiment, a memory cell region, a peripheral circuit region, and a boundary region therebetween are defined, and a conductor film pattern covering the memory cell region and extending to the boundary region is formed. Is formed, the portion from the boundary region to the memory cell region is removed, and then, for example, a BPSG film is formed again on the entire surface, and both BPSG films are heat-treated and reflowed.

At the time of the first BPSG film removal, since the conductor film pattern exists under the BPSG film, the etching may be continued until the conductor film pattern is exposed. Therefore, the etching control is extremely easy. By the formation and etching of the BPSG film, local irregularities are easily flattened, and SO
The required planarization is achieved over the entire substrate without using a special material such as G.

Now, the present invention will be described in further detail with reference to Examples.

[0021]

Embodiment 1 According to the present invention, a semiconductor device having a DRAM cell was manufactured by the procedure shown in FIGS. Step 1 (FIG. 2) A DRAM cell 210 having a fin-type capacitor and a peripheral circuit 220 were formed on a silicon substrate 201 by a procedure similar to the conventional one . However, the counter electrode pattern 211 of the cell 210 is changed to the boundary region 230 between the regions 210 and 220.
Is different from the conventional one. The width (W) of the boundary region was 10 μm.

Here, the structure shown in FIG. 2 is configured as follows. A field oxide film 202 for element isolation is provided on the surface of a p-type silicon semiconductor substrate 201. In the active region defined by the field oxide film 202, a gate oxide film 203 is formed.
3, a gate electrode 204 made of first-layer polysilicon extending over the field oxide film 202 is formed. The gate electrode 204 simultaneously forms the gate electrode of the transfer transistor of the memory cell and the lead line, and forms the gate electrode of the MOSFET in the peripheral circuit region 220.

Gate electrode 204 and field oxide film 20
2 as a mask, the n-type diffusion layer 205 is formed by a transfer transistor of a memory cell and a peripheral circuit MOS.
Constructs the source and drain of the FET. Gate electrode 20
4 and insulating film 2 of SiO ₂ covering n-type diffusion layer 205
06 through the contact hole 206A formed in
Second-layer polysilicon 207 is in contact with n-type diffusion layer 205. The second-layer polysilicon 207 forms a bit line in the memory cell region 210 and the peripheral circuit region 22
A value of 0 constitutes a cushion (pad layer) described later.

SiO 2 covering the second-layer polysilicon 207
₂ and the storage electrode 2 of the fin through the contact hole 208A formed in the insulating film 208 consisting of a stack of SiN
09 is connected to the drain 205 of the transfer transistor of the memory cell. The storage electrode 209 is formed only in the memory cell region 210. Further, a counter electrode 211 is formed so as to cover a dielectric film (not shown) covering the storage electrode 209.

The gate electrode 204 has a thickness of 1000 mm, the bit line 207 has a thickness of 1000 mm, and the storage electrode 209 has a total height of 3 mm.
000 ° (a 500 ° fin and a 500 ° gap are repeated three times each), and the counter electrode 211
Is formed with a thickness of 800 °, so that the height difference between the portion of the peripheral circuit region 220 where there is no pattern and the memory cell region 210 is about 5800 °.

In FIG. 3 to FIG. 9 below, for simplicity of the drawings, reference numerals 202 to 2 denote components which are not directly related to the features of the present invention.
09 avoided dare to attach it. These are shown in FIG.
Will be referred to. Step 2 (FIG. 3) A BPSG film 241 was grown on the entire surface of the substrate by the CVD method by the difference in height between the memory cell region 210 and the peripheral circuit region 220 (5800 ° in this embodiment). The entire surface of the peripheral circuit 220 and the boundary region 23 are formed by photolithography technology.
A resist pattern 242 was formed to cover a part of 0.
At this time, the resist pattern 24 in the boundary region 230 is
The edge 242 </ b> P of the second electrode 242 </ b> P
So that it is located above Step 3 (FIG. 4) CHPS the BPSG film 241 using the resist 242 as a mask
After anisotropically etching with F ₃ / He, resist 24
2 was removed. Thereby, the portion 230P of the boundary region 230 closer to the peripheral circuit region 220 from the peripheral circuit region 220
The BPSG film 241 was patterned so as to cover Here, anisotropic etching is performed, but isotropic etching such as an HF solution may be performed. In any case, the counter electrode 211 (for example, made of polycrystalline silicon)
Since the etching is automatically stopped at the extending portion 211P, the end point of the etching can be easily controlled.

When etching is performed by the RIE method, the emission spectrum of the plasma changes when the counter electrode 211 is exposed, and this is preferably used for detecting the etching end point. Since the counter electrode 211 covers the entire memory cell 210 and accounts for a large proportion of the substrate area,
Such end point detection can be easily performed. Also, the boundary area 2
Since the width (W) of 30 can be set appropriately large, isotropic etching using HF or the like can be used. In this case, since the opposite electrode 211 made of, for example, polycrystalline silicon is hardly etched, no problem occurs even if the etching time is excessive.

As described above, one of the great advantages of the present invention is that the etching control can be performed extremely easily, as compared with the conventional technique of flattening the wiring step. Step 4 (FIG. 5) A new BPSG film 243 is
The end 241P of the SG pattern 241 and the memory cell 210
And a thickness just enough to fill the depression between
500 °). However, in the present embodiment, since the reflow is performed in the next step, it is not necessary to bury the recesses strictly. Step 5 (FIG. 6) A heat treatment is performed at 850 ° C. for 20 minutes in a nitrogen atmosphere .
The BPSG films 241 and 242 were reflowed. As a result, although some shallow irregularities remained locally, a large difference in height between the memory cell 210 and the periphery 220 was substantially eliminated. Also, the remaining local irregularities can be sufficiently smoothed depending on the reflow conditions.

Since the reflow process can be used as described above, there is no need to use a special material such as SOG,
Normal material such as BPSG can be sufficiently flattened, and extremely stable production becomes possible. This is also one of the great advantages of the present invention over the conventional planarization technology. Step 6 (FIG. 7) Through holes 244 for making electrical connection with the upper layer wiring were formed by lithography technology. Normally, since this through hole 244 is formed in the peripheral circuit as shown, it penetrates through the thick BPSG film, so that the through hole 244 becomes deeper than the conventional one. In consideration of this point, the pad layer 22 made of the same material as the bit line is provided at a portion where the diffusion layer 205 and the wiring are connected.
2 (so-called "Zamadan") is inserted. Regarding this pad layer or seat cushion, see Japanese Patent Application Laid-Open No. 1-120863.
In detail. By providing this pad layer, advantages such as the fact that a relatively large through hole can be realized, and that even if there is a subtle change in the shape, a short circuit does not occur between adjacent gate electrodes are obtained.

Next, after the Ti-TiN-W was continuously grown by the CVD method to fill the through holes 244, a wiring pattern 245 was formed by lithography. Since the wiring pattern can be formed in a flat state with almost no difference in height, the problem of the depth of focus in the related art is solved, and the wiring pattern can be formed with extremely high precision. Embodiment 2 According to the present invention, a semiconductor device having a DRAM cell was manufactured in the same procedure as in Embodiment 1. However,
The following points are different from the first embodiment. Step 1 (FIG. 8) The same operation as in Example 1 was performed. However, the upper surface of the counter electrode 211 made of polycrystalline silicon is
To form a laminated structure. Step 2 (FIG. 9) A silicon oxide film 216 is formed on the entire surface of the substrate, and a BPSG film 241 is formed on the silicon oxide film 216 by the CVD method in the same manner as in the first embodiment by the difference in height (5800 °) between the memory cell region 210 and the peripheral circuit region 220. Grew. A resist pattern 242 covering the entire peripheral circuit 220 and a part of the boundary region 230 was formed by photolithography. At this time, the edge 242P of the resist pattern 242 in the boundary region 230 is located above the extending portion 211P of the counter electrode 211.

After the BPSG film 241 and the silicon oxide film 216 were isotropically etched in an HF solution using the resist 242 as a mask, the resist 242 was removed. Thus, the BPSG film 241 is patterned so as to cover from the peripheral circuit region 220 to the portion 230P of the boundary region 230 near the peripheral circuit region 220. During this etching, the silicon nitride film 215 acts as an etching stopper, and the surface of the polycrystalline silicon 211 is not exposed.

Thereafter, flattening, formation of through holes, and formation of wiring were performed in the same procedure as in Example 1. In this embodiment, since the polycrystalline silicon 211 of the counter electrode is protected by the silicon nitride film 215, it does not directly contact the BPSG films 241 and 243 formed thereon.
Therefore, depending on the heat treatment for reflow,
B and P do not diffuse into the polycrystalline silicon 211 from the G film. Since the impurity concentration in the counter electrode has a large effect on the resistance and the growth of crystal grains, if the impurity concentration fluctuates, these characteristics will fluctuate greatly. This point is described in detail in JP-A-1-186655. In this embodiment, such an undesirable phenomenon can be prevented by a simple method.

The present invention has the following advantages in connection with the diffusion of impurities. That is, when the first BPSG pattern is not formed on the counter electrode as in the present invention, if the etching is excessive, the silicon substrate 201 in the transistor region is exposed, and there is a danger that the transistor will be destroyed by impurity diffusion from the BPSG. is there. In order to avoid such danger, a planarization method for performing reflow according to the present invention is very advantageous.

[0034]

As described above, according to the present invention,
In a semiconductor device such as a DRAM or an SRAM, even if the height of a memory cell region is large and a large step is formed between the memory cell region and a peripheral circuit region, it is sufficient to pattern an upper layer wiring crossing over these regions with high precision. Flattening can be performed. As a result, the height difference between the memory cell region and the peripheral circuit region can be eliminated, and a fine wiring pattern can be formed. Further, since α-ray soft errors can be prevented by increasing the memory cell capacity, high-speed operation can be sufficiently ensured as compared with the conventional case using ECC.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views showing the procedure of a conventional planarization method.

FIG. 2 is a cross-sectional view showing a step in an example of a manufacturing procedure of a semiconductor device which performs planarization according to the present invention, and shows a stage in which a counter electrode extending from a memory cell region to a boundary region is formed.

FIG. 3 is a cross-sectional view showing a step in an example of a manufacturing procedure of a semiconductor device for performing planarization according to the present invention. After the step of FIG. 2, a first insulating film covering the entire surface of the substrate and a resist pattern thereon Shows the stage at which was formed.

FIG. 4 is a cross-sectional view showing a step in an example of a manufacturing procedure of a semiconductor device for performing planarization according to the present invention, in which a first insulating film is etched using a resist as a mask, following the step of FIG. 3; Is shown.

5 is a cross-sectional view showing a step in an example of a manufacturing procedure of a semiconductor device that performs planarization according to the present invention. After the step of FIG. 4, a second insulating film is further formed on the entire surface of the substrate, Shows the stage in which the remaining depression is embedded.

FIG. 6 is a cross-sectional view showing a step in an example of a manufacturing procedure of a semiconductor device which performs planarization according to the present invention. After the step of FIG. 5, a flat surface is formed by reflowing the first and second insulating films. The step of forming an insulating film having the following is shown.

FIG. 7 is a cross-sectional view showing a step in an example of a manufacturing procedure of a semiconductor device which performs planarization according to the present invention. After the step of FIG. 5, after forming a through-hole in an insulating film, embedding of the through-hole and The stage at which the wiring pattern is formed is shown.

FIG. 8 is a cross-sectional view showing a step in another example of a manufacturing procedure of a semiconductor device for performing planarization according to the present invention, in which a counter electrode extending from a memory cell region to a boundary region and a nitride film covering the counter electrode; Shows the stage at which is formed.

9 is a cross-sectional view showing a step in another example of the manufacturing procedure of the semiconductor device for performing the planarization according to the present invention, and shows a stage in which a first insulating film is formed and patterned, following the stage in FIG. 8; .

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Wiring 12 ... Insulating film 13 ... Resist pattern 14 ... Insulating film 201 ... P-type silicon substrate 202 ... Field oxide film for element isolation 203 ... Gate oxide film 204 ... Gate electrode 205 made of first layer polysilicon 205 insulating film 206A ... contact hole 207 ... second layer polysilicon 208 ... comprised a laminate of SiO ₂ and SiN insulating film 208A ... contact hole 209 ... fin type storage electrode 210 ... memory cells ... made of n-type diffusion layer 206 ... SiO ₂ Area 211 ... Counter electrode (polycrystalline silicon) 211P ... Extension of the counter electrode 215 ... Silicon nitride film 216 ... Silicon oxide film 220 ... Peripheral circuit area 222 ... Pad layer or "Zamadan" 230 ... Boundary area 230P ... Boundary area 230 241 near the memory cell region 220 of the first Enmaku (BPSG film) 242 ... resist pattern 243: second insulating film (BPSG film) 244 ... through hole 245 ... wire

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (28)

(57) [Claims] 1. A first element region and a second element on a semiconductor substrate.
Region and a boundary region between the two, and
At least some of the elements formed in one element region are
Should not be formed higher than the elements formed in the two element region
And Part of the layer formed in the first element region is
An extending portion that extends, First insulation covering a part of the extension and the second element region;
Membrane and A second insulating film covering at least the extension portion.
And The first insulating film and the second insulating film overlap each other;
Characterized in that the surface of the insulating film formed is substantially flat
Semiconductor device. 2. A first element region and a second element on a semiconductor substrate.
An area and a boundary area between the two, Part of the first element region extends to the boundary region
An extension, First insulation covering a part of the extension and the second element region;
Membrane and A second insulating film covering the first insulating film and the extension, A through hole opened through the first and second insulating films
And Electrically connected to the other through the through hole and the first
A conductive film extending from the element region to the second element region.
A semiconductor device comprising: 3. The first element region is a memory cell region.
And the second element region is a peripheral circuit region.
The semiconductor device according to claim 1, wherein: 4. The first element region is a memory cell region.
And the second element region is a peripheral circuit region.
3. The semiconductor device according to claim 2, wherein: 5. The method according to claim 1, wherein the first insulating film has a thickness equal to that of the first element.
That corresponds to the height difference between the element region and the second element region.
5. The semiconductor device according to claim 1, wherein: 6. A method according to claim 1, wherein a part of the first element region has a layer
One of the memory capacitors included in the first element region;
6. The semiconductor according to claim 3, which is a pole.
apparatus. 7. The extended portion of the first and second insulating films
Insulation films with different etching characteristics
7. The semiconductor device according to claim 1, wherein: 8. The first insulating film is a chemical vapor deposition film.
8. The semiconductor device according to claim 1, wherein:
Place. 9. The method according to claim 1, wherein the first insulating film contains an impurity.
And heating and reflowing.
13. The semiconductor device according to claim 1. 10. The second insulating film is a chemical vapor deposition film.
10. The semiconductor device according to claim 1, wherein:
Place. 11. The second insulating film contains an impurity.
And being heated and reflowed.
11. The semiconductor device according to item 10. 12. A circuit on a semiconductor substrate higher than the surroundings.
The element part is formed, and a part of the layer forming the circuit element part is
A step of extending outside the element part to become an extension part, Next, the entire substrate including the circuit element portion and the extension portion is covered.
Forming a first insulating film, Then, at least over the end of the extension, the first
Covering the insulating film, and forming the first insulating film on the circuit element portion;
Using a mask formed so as not to cover, the first insulating
Etching and removing the film; Next, a second insulating layer is formed on the entire remaining structure up to the above step.
Step of flattening the surface by forming an edge film
A method for manufacturing a semiconductor device comprising: 13. A circuit element formed in the circuit element portion
Is a memory cell.
A method for manufacturing a semiconductor device. 14. The circuit according to claim 1, wherein a thickness of said first insulating film is equal to said circuit thickness.
Claim corresponding to the height difference between the element part and the other
Item 14. The method for manufacturing a semiconductor device according to Item 12 or 13. 15. The semiconductor device according to claim 15, wherein a part of the circuit element portion is
One electrode of the memory capacitor included in the
15. The semiconductor device according to claim 12, wherein:
Manufacturing method of the device. 16. The semiconductor device according to claim 16, wherein said extending portion is etched during said etching.
2. The film according to claim 1, wherein the film functions as a chucking stopper film.
16. A method for manufacturing a semiconductor device according to any one of Items 2 to 15. 17. The extension part is made of a silicon nitride film.
17. The semiconductor device according to claim 12, wherein:
Manufacturing method. 18. The method according to claim 18, wherein the first insulating film is formed by chemical vapor deposition.
18. It is formed by this.
The manufacturing method of the semiconductor device described in the above. 19. The first insulating film contains an impurity.
And formed after the formation.
19. Heat reflow is performed.
The manufacturing method of the semiconductor device described in the above. 20. The method according to claim 19, wherein the second insulating film is formed by chemical vapor deposition.
20. It is formed by this.
The manufacturing method of the semiconductor device described in the above. 21. The second insulating film contains an impurity.
And formed after the formation.
21. Heat reflow
The manufacturing method of the semiconductor device described in the above. 22. The first insulating film and the second insulating film
Wherein both are BPSG films.
22. The method of manufacturing a semiconductor device according to any one of 18 to 21. 23. After the step of flattening the surface,
Having a step of forming a conductive film on the remaining structure
23. Manufacturing of a semiconductor device according to claim 12, wherein
Method. 24. A first region and a second region on a semiconductor substrate.
Defining an area and a boundary area between the two, Forming a first element in the first and second regions; Forming a second element only in the first region; A first conductor extending from the first region to the boundary region
Forming a film, Forming a first insulating film on the entire surface of the substrate; Removing a portion of the first insulating film covering the first region;
Exposing the first conductor film by: Forming a second insulating film on the entire surface of the substrate; The first and second insulating films are selectively removed to form a through hole.
Forming a tool, And a second extending from the first region to the second region
A step of forming a conductive film of the semiconductor
Manufacturing method of body device. 25. The method according to claim 25, wherein the first insulating film is removed to remove the first insulating film.
During the etching for exposing the conductive film of
Detecting the end point of the etching by the conductor film of 1.
The method for manufacturing a semiconductor device according to claim 24, wherein: 26. The device according to claim 26, wherein the first element is a MOS transistor.
And the second element is a capacitor.
26. The method of manufacturing a semiconductor device according to claim 24, wherein
Law. 27. The method according to claim 27, wherein the first conductor film is a capacitor.
27. The method according to claim 26, wherein one of the electrodes is formed.
Manufacturing method of the semiconductor device described above. 28. A polycrystalline silicon film and a silicon nitride film
Are laminated in this order to form the first conductive film.
And As the first and second insulating films, a silicon-containing insulating film
Forming a silicon oxide film, The first isolation is performed by etching with a solution containing hydrofluoric acid.
Removing a portion of the rim covering the first region to remove the first region;
Exposing the conductor film, After forming the second insulating film, heat treatment is performed.
And reflowing the first and second insulating films.
28. The method according to any one of claims 24 to 27, wherein
A method for manufacturing a semiconductor device.