KR970003635A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
KR970003635A
KR970003635A KR1019950018882A KR19950018882A KR970003635A KR 970003635 A KR970003635 A KR 970003635A KR 1019950018882 A KR1019950018882 A KR 1019950018882A KR 19950018882 A KR19950018882 A KR 19950018882A KR 970003635 A KR970003635 A KR 970003635A
Authority
KR
South Korea
Prior art keywords
forming
photoresist pattern
insulating layer
etching process
semiconductor device
Prior art date
Application number
KR1019950018882A
Other languages
Korean (ko)
Inventor
이상규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950018882A priority Critical patent/KR970003635A/en
Publication of KR970003635A publication Critical patent/KR970003635A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자 제조방법에 관한 것으로, 하부절연층이 형성된 반도체기판 상부에 비트라인과 캐패시터를 형성하고 전체표면상부에 플로우가 잘되는 제1절연막을 형성한 다음, 고온열공정으로 플로우시키고 단차가 낮은 부분에 감광막패턴을 형성하고 상기 감광막패턴을 마스크로하여 상기 제1절연막의 하부에 형성된 최상부의 구조물이 노출될 때까지 식각한 다음, 상기 감광막패턴을 제거하고 전체표면상부에 플로우가 잘되는 제2절연막을 일정두께 형성한 다음, 고온 열공정으로 플로우시켜 상부구조를 평탄화시킴으로써 후속공정을 용이하게 하여 반도체소자의 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, comprising forming a bit line and a capacitor on an upper surface of a semiconductor substrate on which a lower insulating layer is formed, and forming a first insulating film having a good flow on the entire surface thereof, and then flowing it in a high temperature heat process and Forming a photoresist pattern at a lower portion and etching the uppermost structure formed under the first insulating layer using the photoresist pattern as a mask until the top structure is exposed, and then removing the photoresist pattern and having a good flow on the entire surface; The insulating film is formed to a predetermined thickness, and then flows in a high temperature thermal process to planarize the upper structure, thereby facilitating subsequent processes, thereby improving the reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 실시예에 따른 반도체소자 제조방법을 도시한 단면도.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (7)

단차가 높은 셀부와 단차가 낮은 주변회로부의 단차를 완화시키는 반도체소자 제조방법에 있어서, 반도체 기판 상부에 하부절연층, 비트라인 및 캐패시터를 형성하는 공정과, 전체표면상부에 플로우가 잘되는 제1절연막을 증착하고 플로우시키는 공정과, 상기 주변회로부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 제1절연막 하부의 구조물이 노출될 때까지 식각하는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면상부에 플로우가 잘되는 제2절연막을 증착하고 이를 플로우시켜 평탄화층을 형성하는 공정을 포함하는 반도체소자 제조방법.A semiconductor device manufacturing method for alleviating the step difference between a high stepped cell portion and a low stepped peripheral circuit portion, comprising: forming a lower insulating layer, a bit line, and a capacitor on an upper surface of a semiconductor substrate, and a first insulating film having a good flow on the entire surface. Forming a photoresist pattern and forming a photoresist pattern; forming a photoresist pattern; forming a photoresist pattern; forming a photoresist pattern; forming a photoresist pattern; Forming a planarization layer by depositing a second insulating film having a good flow on the entire surface and flowing the same; 제1항에 있어서, 상기 제1,2절연막은 BPSG 산화막으로 형성되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the first and second insulating layers are formed of a BPSG oxide film. 제1항에 있어서, 상기 감광막패턴은 캐패시터를 형성하는 플레이트전극 마스크를 이용한 식각공정으로 형성되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the photoresist pattern is formed by an etching process using a plate electrode mask to form a capacitor. 제1항에 있어서, 상기 제1절연막은 상기 셀부와 주변회로부의 단차만큼 두껍게 형성되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the first insulating layer is formed as thick as a step between the cell portion and the peripheral circuit portion. 제1항에 있어서, 상기 제1절연막 식각공정은 CF4, C2F6, O2가스들을 이용한 플라즈마식각공정으로 실시되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the first insulating layer etching process is performed by a plasma etching process using CF 4 , C 2 F 6 , and O 2 gases. 제1항에 있어서, 상기 제1절연막 식각공정은 BOE 용액을 이용하여 실시되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the first insulating layer etching process is performed using a BOE solution. 제1항에 있어서, 상기 제1절연막 식각공정은 희석 불산용액을 이용하여 실시되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the first insulating layer etching process is performed using a dilute hydrofluoric acid solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018882A 1995-06-30 1995-06-30 Semiconductor device manufacturing method KR970003635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950018882A KR970003635A (en) 1995-06-30 1995-06-30 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950018882A KR970003635A (en) 1995-06-30 1995-06-30 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
KR970003635A true KR970003635A (en) 1997-01-28

Family

ID=66526135

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950018882A KR970003635A (en) 1995-06-30 1995-06-30 Semiconductor device manufacturing method

Country Status (1)

Country Link
KR (1) KR970003635A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200071339A (en) * 2018-12-11 2020-06-19 주식회사 포스코 Apparatus and method for dust recyle

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299599A (en) * 1992-04-16 1993-11-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH0697159A (en) * 1992-09-14 1994-04-08 Sanyo Electric Co Ltd Fabrication of semiconductor device
JPH06177351A (en) * 1992-12-02 1994-06-24 Toshiba Corp Manufacture of semiconductor device
KR950001926A (en) * 1993-06-22 1995-01-04 김주용 Semiconductor device manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299599A (en) * 1992-04-16 1993-11-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH0697159A (en) * 1992-09-14 1994-04-08 Sanyo Electric Co Ltd Fabrication of semiconductor device
JPH06177351A (en) * 1992-12-02 1994-06-24 Toshiba Corp Manufacture of semiconductor device
KR950001926A (en) * 1993-06-22 1995-01-04 김주용 Semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200071339A (en) * 2018-12-11 2020-06-19 주식회사 포스코 Apparatus and method for dust recyle

Similar Documents

Publication Publication Date Title
JPH0685086A (en) Formation method of fine contact for high- integration element
KR940022801A (en) Contact formation method of semiconductor device
KR970003635A (en) Semiconductor device manufacturing method
JPH0313744B2 (en)
KR920007824B1 (en) Contacting device of semiconductor elements
JPS583252A (en) Semiconductor integrated circuit device
KR100268896B1 (en) method for manufacturing of capactor
KR970030483A (en) Method of fabricating a semiconductor device
KR100190187B1 (en) Fabrication method of semiconductor device
KR960026835A (en) Capacitor Manufacturing Method of Semiconductor Device
KR19980030405A (en) Contact hole formation method of semiconductor device
JPH0287621A (en) Manufacture of semiconductor device
JPS6197946A (en) Manufacture of semiconductor device
KR20030002054A (en) Method of forming contact of semiconductor device using polysilicon hard mask
KR950019956A (en) Capacitor Manufacturing Method of Semiconductor Device
JPS6322067B2 (en)
KR950034630A (en) Method for forming storage electrode of semiconductor device
KR970054549A (en) Capacitor Manufacturing Method of Semiconductor Device
KR20040083758A (en) Method for forming a hard mask in semiconductor device
KR950034424A (en) Global flattening method
KR960026793A (en) Capacitor Manufacturing Method of Semiconductor Device
JPS6145859B2 (en)
KR20010061121A (en) A method for forming a conductive line of a semiconductor device
KR980005483A (en) Method for manufacturing charge storage electrode of semiconductor device
KR19980026459A (en) Semiconductor metal film etching process

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application