KR950034424A - Global flattening method - Google Patents

Global flattening method Download PDF

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Publication number
KR950034424A
KR950034424A KR1019940010460A KR19940010460A KR950034424A KR 950034424 A KR950034424 A KR 950034424A KR 1019940010460 A KR1019940010460 A KR 1019940010460A KR 19940010460 A KR19940010460 A KR 19940010460A KR 950034424 A KR950034424 A KR 950034424A
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KR
South Korea
Prior art keywords
insulating film
global flattening
flattening method
insulating layer
global
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KR1019940010460A
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Korean (ko)
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KR100361519B1 (en
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송승용
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문정환
금성일렉트론 주식회사
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Priority to KR1019940010460A priority Critical patent/KR100361519B1/en
Publication of KR950034424A publication Critical patent/KR950034424A/en
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Publication of KR100361519B1 publication Critical patent/KR100361519B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

Abstract

본 발명은 반도체소자의 제조공정 중에 발생하는 단차를 없애고 셀지역의 손상을 주지 않아서 고집적소자의 제조에 적합한 글로벌평탄화방법에 관한 것이다.The present invention relates to a global flattening method suitable for the manufacture of highly integrated devices by eliminating the steps generated during the manufacturing process of semiconductor devices and not damaging the cell area.

본 발명의 구성은 반도체기판의 표면에 높은지역과 낮은지역이 있어서 큰 단차를 나타낼때 후속공정을 위하여 이 단차를 없애는 글로벌평탄화방법에 있어서, 가)단차제거공정을 위하여 제1절연막을 증착하는 단계와, 나)상기 제1절연막 상에 유동성이 좋은 재질로 된 제2절연막을 증착하는 단계와, 다)웨이퍼의 낮은지역상의 상기 제2절연막위에 마스크패턴을 형성한 후, 이 마스크패턴을 이용하여 낮은지역 상에만 제2절연막이 잔류하도록 제2절연막을 식각하는 단계와, 라)평탄화공정을 실시하는 단계를 포함한다.The configuration of the present invention is a global flattening method that eliminates the step for the subsequent step when there are high and low areas on the surface of the semiconductor substrate to show a large step, a) depositing a first insulating film for the step removing step And b) depositing a second insulating film made of a material having good fluidity on the first insulating film; and c) forming a mask pattern on the second insulating film on the low region of the wafer, and then using the mask pattern. Etching the second insulating film so that the second insulating film remains only on the low region; and d) performing a planarization process.

Description

글로벌평탄화방법Global flattening method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 글로벌평탄화방법을 도시한 것이다.2 shows a global leveling method according to the present invention.

Claims (7)

반도체기판의 표면에 높은지역과 낮은지역이 있어서 큰 단차를 나타낼때 후속공정을 위하여 이 단차를 없애는 글로벌평탄화방법에 있어서, 가)단차제거공정을 위하여 제1절연막을 증착하는 단계와, 나)상기 제1절연막 상에 유동성이 좋은 재질로 된 제2절연막을 증착하는 단계와, 다)웨이퍼의 낮은 지역상의 상기 제2절연막위에 마스크패턴을 형성한 후, 이 마스크패턴을 이용하여 낮은지역 상에만 제2절연막이 잔류하도록 제2절연막을 식각하는 단계와, 라)평탄화공정을 실시하는 단계를 포함하는 것을 특징인 글로벌평탄화방법.In the global flattening method of eliminating this step for a subsequent process when there are high and low areas on the surface of the semiconductor substrate to show a large step, a) depositing a first insulating film for the step removing step; Depositing a second insulating film made of a material having good fluidity on the first insulating film; and c) forming a mask pattern on the second insulating film on the low region of the wafer, and then using only the mask pattern on the low region. 2) etching the second insulating film so that the insulating film remains; and d) performing a leveling process. 제1항에 있어서, 제1절연막은 ILD이고, 글로벌평탄화공정의 온도는 400℃ 내지 900℃의 범위에서 실시하는 것이 특징인 글로벌평탄화방법.The global flattening method according to claim 1, wherein the first insulating film is an ILD, and the temperature of the global flattening process is performed in a range of 400 ° C to 900 ° C. 제1항에 있어서, 제1절연막은 IMD이고, 글로벌평탄화공정의 플로우 온도는 상온에서 450℃까지의 범위에서 실시하는 것이 특징인 글로벌평탄화방법.The global flattening method according to claim 1, wherein the first insulating film is an IMD, and the flow temperature of the global flattening process is performed in a range from room temperature to 450 ° C. 제1항에 있어서, 상기 제2절연막은 유동성 산화막으로서 BPSG, PSG, BSG, 하이드로겐실시퀴옥산, 폴리머 중 어느 하나를 선택하여 사용하며, 제2절연막의 잔류면적 및 오버랩마진은 제1절연막의 슬로프 각도에 따라 조절하며, 제2절연막의 두께는 셀지역과 주변지역간의 단차를 고려하여 500Å 내지 5㎛범위로 하는 것이 특징인 글로벌평탄화방법.The method of claim 1, wherein the second insulating layer is selected from any one of BPSG, PSG, BSG, hydrogen acquiquioxane, and a polymer as a flowable oxide film, the remaining area and overlap margin of the second insulating film is Adjusting according to the slope angle, the thickness of the second insulating film is a global flattening method characterized in that the range of 500 ~ 5㎛ in consideration of the step between the cell region and the surrounding area. 제4항에 있어서, 상기 제2절연막은 단차가 높은 셀지역과 잔류하는 제2절연막의 오버랩마진을 0㎛ 내지 100㎛의 범위를 갖는 것이 특징인 글로벌평탄화방법.The global flattening method of claim 4, wherein the second insulating layer has an overlap margin between the cell region having a high level of difference and the remaining second insulating layer in a range of 0 μm to 100 μm. 제2항에 있어서, 상기 제2절연막은 BPSG인 것이 특징인 글로벌평탄화방법.The method of claim 2, wherein the second insulating layer is BPSG. 제3항에 있어서, 상기 제2절연막은 하이드로겐실시퀴옥산인 것이 특징인 글로벌평탄화방법.The method of claim 3, wherein the second insulating layer is hydrogen acquiquioxane. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010460A 1994-05-13 1994-05-13 Global planarization method KR100361519B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100477837B1 (en) * 1997-12-30 2005-07-07 주식회사 하이닉스반도체 Semiconductor Device Manufacturing Method for Planarization

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920010892A (en) * 1990-11-30 1992-06-27 김광호 Surface flattening method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100477837B1 (en) * 1997-12-30 2005-07-07 주식회사 하이닉스반도체 Semiconductor Device Manufacturing Method for Planarization

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