KR100361519B1 - Global planarization method - Google Patents
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- KR100361519B1 KR100361519B1 KR1019940010460A KR19940010460A KR100361519B1 KR 100361519 B1 KR100361519 B1 KR 100361519B1 KR 1019940010460 A KR1019940010460 A KR 1019940010460A KR 19940010460 A KR19940010460 A KR 19940010460A KR 100361519 B1 KR100361519 B1 KR 100361519B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- -1 (HSiO 3/ 2) n) Polymers 0.000 description 1
- RYHBNJHYFVUHQT-UHFFFAOYSA-N 1,4-Dioxane Chemical compound C1COCCO1 RYHBNJHYFVUHQT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은 반도체소자 제조시에 발생하는 단차를 최소화하는 글로벌평탄화방법에 관한 것으로서, 특히 국부적으로 단차를 조절하여 층간절연막 형성에 적당하도록 한 글로벌평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a global flattening method for minimizing the level difference generated during semiconductor device manufacturing, and more particularly, to a global flattening method suitable for forming an interlayer insulating film by locally adjusting the level difference.
제 1 도는 종래의 글로벌평탄화방법을 도시한 것이다.1 shows a conventional global flattening method.
첨부한 도면을 참조하며 종래의 기술을 설명하면 다음과 같다.The prior art will be described with reference to the accompanying drawings.
먼저 제 1도의 (가)와 같이 반도체기판(14) 상에 집적도가 높은 셀영역(12)과 부수적 회로로 구성되는 주변(Periphery)영역(13)이 형성되고 두 영역간에는 구조차이에 의한 구조단차(15)가 존재하게 된다.First, as shown in (a) of FIG. 1, a highly integrated cell region 12 and a peripheral region 13 composed of ancillary circuits are formed on the semiconductor substrate 14, and structural differences between the two regions are caused by structural differences. (15) will exist.
종래에는 이러한 단차를 고려하지 않고 CVD또는 SOG 방법등을 이용하여 비정질 실리콘산화막 등으로 절연막(11)을 적층한다.Conventionally, without considering such a step, the insulating film 11 is laminated with an amorphous silicon oxide film or the like using a CVD or SOG method or the like.
이때 영역간의 절연막상에 발생하는 절연막단차(16)는 기본소자의 구조에 추가로 더 구성된 구조의 높이 만큼 발생한다.At this time, the insulating film step 16 generated on the insulating film between the regions is generated by the height of the structure further configured in addition to the structure of the basic element.
제 1 도의 (나)와 같이 절연막(11)상에 1층금속배선(19)을 형성한다.As shown in FIG. 1B, a one-layer metal wiring 19 is formed on the insulating film 11.
다음 제 1 도의 (다)와 같이 1층금속배선(19)과 2층금속배선과의 격리를 위한 층간절연막(17)을 증착한다.Next, as shown in FIG. 1C, an interlayer insulating film 17 is deposited to isolate the one-layer metal wiring 19 and the two-layer metal wiring.
이때 셀영역(12)과 주변영역(13)간의 층간절연막(17) 상에 형성되는 최종단차(18)는 하층에 이루어진 영역간의 구조 높이 차이에 의한 구조단차(15)보다 동일한 상태를 유지하거나 더 증가한 상태가 된다. 즉, 절연막의 증착 및 플로잉 후에는 그 토포로지를 부드럽게 연결시켜 줄 수 있으나, 궁극적으로 최종단차(18)는 최초의 단차 크기에 상응하는 만큼 존재한다.In this case, the final step 18 formed on the interlayer insulating film 17 between the cell region 12 and the peripheral region 13 may maintain or be the same as the structure step 15 due to the difference in structure height between the lower layers. It is in an increased state. That is, the topologies may be smoothly connected after the deposition and the flow of the insulating layer, but ultimately, the final step 18 exists as much as the initial step size.
특히 배선 디자인룰이 0.54㎛이상인 반도체소자 제조공정기술에서는 집적도가 높은 셀영역과 부수적 회로로 구성되는 주변영역간의 높이단차가 1㎛미만으로 형성되어 큰 문제로서 부각되지 않았다.In particular, in the semiconductor device manufacturing process technology having a wiring design rule of 0.54 µm or more, the height difference between the highly integrated cell region and the peripheral region composed of ancillary circuits is less than 1 µm, which is not a big problem.
상대적으로 집적도가 낮은 소자에서는 기본소자 구성시 3차원적구조에서 높이 방향의 추가구조가 필요하지 않고 X 및 Y 방향의 면적으로 확대가 가능하였다 .In the case of relatively low integration devices, the three-dimensional structure does not require the additional structure in the height direction and can be enlarged in the X and Y directions.
그러나, 초고집적소자에서는 일정한 하층의 면적에 보다 많은 수의 소자가 필수적 이므로 이러한 단차는 더욱 커지게 되어 문제가 되었다.However, in the ultra-high integrated device, since a larger number of devices are necessary for a constant lower layer area, the step becomes larger and becomes a problem.
즉, 고집적화 경향에 따라 배선디자인룰이 0.5㎛ 이하인 반도체소자들이 등장하게 되어 영역간의 단차는 1㎛ 이상으로 커지게 되었다.That is, according to the trend of high integration, semiconductor devices having a wiring design rule of 0.5 μm or less have appeared, and the step difference between regions has increased to 1 μm or more.
이와 같이 소자제조공정 중의 형성한 높은 단차로 인하여 이후의 패턴형성시 DOF(촛점심도)조절의 어려움, 배선신뢰성저하, 억세스타임(Access Time) 증가 등의 문제점이 발생하였다.As a result of the high step formed during the device manufacturing process, problems such as difficulty of DOF (depth of focus) control, reduced wiring reliability, and increased access time occurred in the subsequent pattern formation.
본 발명은 반도체소자의 제조공정 중에 발생하는 단차를 없애고 셀영역의 손상을 주지 않아서 고집적소자의 제조에 적합한 글로벌평탄화방법의 제공에 그 목적이 있다.It is an object of the present invention to provide a global flattening method suitable for the manufacture of highly integrated devices by eliminating the steps generated during the manufacturing process of semiconductor devices and not damaging the cell area.
상기 목적을 달성하기 위한 본 발명은 기판의 셀영역과 주변영역 사이의 단차를 제거하는 글로벌평탄화방법에 있어서, 가) 상기 기판의 상기 셀영역과 주변영역 상에 제 1 절연막을 증착하는 단계와, 나)상기 제 1절연막 상에 유동성이 좋은 절연물질인 BPSG, PSG, BSG, 하이드로겐실시퀴옥산, 폴리머중 어느 하나를 선택하여 증착하여 표면의 단차를 감소시키는 제 2절연막을 형성하는 단계 , 다) 상기 주변영역의 상기 제 2 절연막 상에 마스크패턴을 형성한 후, 이 마스크패턴을 이용하여 상기 제 2절연막을 식각하여 상기 주변영역 상에만 잔류하도록 제 2 절연막을 패터닝하는 단계와, 라) 상기 페터닝된 상기 제 2 절연막을 열처리하여 상기 셀영역과 주변영역의 표면을 평탄화하는 단계를 포함한다.The present invention for achieving the above object is a global flattening method for removing the step between the cell region and the peripheral region of the substrate, a) depositing a first insulating film on the cell region and the peripheral region of the substrate; B) forming a second insulating film on the first insulating film by selecting any one of BPSG, PSG, BSG, hydrogen oxyquioxane, and polymer which are highly fluid insulating materials, and depositing any one of them; Forming a mask pattern on the second insulating film in the peripheral area, and then etching the second insulating film using the mask pattern to pattern the second insulating film so as to remain only on the peripheral area; And heat-treating the patterned second insulating layer to planarize the surfaces of the cell region and the peripheral region.
제 2 도는 본 발명의 글로벌평탄화방법을 도시한 것이다.2 shows the global leveling method of the present invention.
첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
일반적으로 반도체소자는 제 2 도의 (가)에서와 같이 반도체기판(24) 상에 회로의 집적도가 높은 셀영역(22)과 보조회로로 구성된 주변영역(23)을 형성하게 되는데 이때 두영역간에는 구조적 차이로 인한 구조단차(25)가 형성된다. 그리고 이러한 단차(25)는 셀영역(22)에서의 회로의 집적도가 커질수록 증가한다.In general, a semiconductor device forms a cell region 22 having a high degree of integration of circuits and a peripheral region 23 composed of auxiliary circuits on the semiconductor substrate 24 as shown in FIG. 2A. Structural step 25 due to the difference is formed. The step 25 increases as the degree of integration of the circuit in the cell region 22 increases.
이와 같은 단차를 제거하는 글로벌평탄화공정을 위하여 도면에 도시한 바와 같이 셀영역(22)과 주변영역(23)상에 제 1절연막(21)을 증착한다.As shown in the drawing, the first insulating layer 21 is deposited on the cell region 22 and the peripheral region 23 to remove the step.
제 1 절연막(21)은 층간의 절연을 위하여는 ILD(Interlayer Dielectric)를, 금속배선간의 절연을 위하여는 IMD(Intermetal Dielectric)을 증착함으로서 형성한다.The first insulating film 21 is formed by depositing interlayer dielectric (ILD) for insulating between layers and intermetal dielectric (IMD) for insulating between metal wirings.
그러나 제 1 절연막(21)의 증착 후에도 제 1 절연막(21)에 절연막단차(26)가 발생한다.However, even after the deposition of the first insulating film 21, the insulating film step 26 is generated in the first insulating film 21.
다음으로 제 2 도의 (나)와 같이 제 1 절연막(21)상의 절연막단차(26)를 없애기 위하여 제 2 절연막(27)을 증착한다. 상기에서 제 2 절연막(27)으로는 유동성이 좋은 절연물질을 사용하여 형성할 수 있다. 예를 들어 BPSG, PSG, BSG, 하이드로겐실시퀴옥산(Hydrogen Silsesquioxane, (HSiO3/2)n), 폴리머등과 같은 물질중에서 어느하나를 선택하여 할 수 있다.Next, as shown in FIG. 2B, the second insulating film 27 is deposited in order to eliminate the insulating film step 26 on the first insulating film 21. The second insulating layer 27 may be formed using an insulating material having good fluidity. For example, it is possible to select the one of a material, such as BPSG, PSG, BSG, hydrogen exemplary rake dioxane (Hydrogen Silsesquioxane, (HSiO 3/ 2) n), polymer and the like.
즉 제 1 절연막(21)이 ILD인 경우에는 제 2 절연막(27)으로서 BPSG를, 제 1 절연막(21)이 IMD인 경우에는 하이드로겐실시퀴옥산을 도포하여 제 2 절연막(27)을 형성하면 된다.In other words, when the first insulating film 21 is an ILD, BPSG is applied as the second insulating film 27, and when the first insulating film 21 is an IMD, the hydrogen insulating polymer 27 is formed by applying the hydrogen succiquioxane. do.
그리고 제 2 절연막(27)의 두께는 셀영역(22)과 주변영역(23)간의 단차를 고려하여 결정하며 , 5000Å 내지 5㎛범위로 한다 이 때 , 제 2 절연막(27)은 유동성이 좋은 절연물질로 형성되므로 표면의 단차가 감소된다.The thickness of the second insulating film 27 is determined in consideration of the step difference between the cell region 22 and the peripheral region 23. The thickness of the second insulating film 27 is in the range of 5000 μm to 5 μm. Since it is formed of a material, the level difference of the surface is reduced.
다음, 제 2 도의 (다)와 같이 제 2 절연막(27) 상에 감광막을 도포한 후 주변영역(23)에만 잔류하도록 리소그래피공정으로 패터닝하여 마스크패턴(28)을 형성한다. 여기서 마스크패턴(28)의 마스킹 면적은 제 1 절연막(21)의 슬로프 각도에 따라 조절하며 , 마스킹되는 영역은 주변영역(23)의 모서리로 부터 0㎛ 내지 100㎛의 범위에서 셀영역(22)과 오버 랩 마진을 갖도록 설정한다.Next, as shown in FIG. 2C, after the photoresist is applied on the second insulating layer 27, the mask pattern 28 is formed by a lithography process so as to remain only in the peripheral region 23. The masking area of the mask pattern 28 is adjusted according to the slope angle of the first insulating layer 21, and the masked area is in the range of 0 μm to 100 μm from the edge of the peripheral area 23. And have an overlap margin.
제 2도의 (라)와 같이 위에서 형성한 마스크패턴(28)을 이용하여 단차가 낮은 주변영역(23)의 제 2 절연막(27-1)만이 잔류하도록 셀영역(22)위에 증착된 제 2 절연막은 에치하여 제거한다. 제 2 절연막(27-1)은 주변영역(23) 상만 잔류하며 , 셀영역(22)의 일부에 오버랩마진 만큼 중첩된 겹침부(29)를 갖는다.The second insulating film deposited on the cell region 22 so that only the second insulating film 27-1 of the peripheral region 23 having a low level of difference remains using the mask pattern 28 formed above as shown in FIG. Is removed by etching. The second insulating layer 27-1 remains only on the peripheral region 23 and has an overlap portion 29 overlapping a part of the cell region 22 by an overlap margin.
제 2 도의 (마)는 셀영역(22)의 제 2 절연막을 식각하고, 마스크팬턴(28)을 제거한 뒤에 주변영역(23)위에 제 2 절연막(27-1)이 잔류한 모양이다.In FIG. 2E, the second insulating film 27-1 remains on the peripheral area 23 after the second insulating film of the cell region 22 is etched and the mask platen 28 is removed.
주변영역(23)에 남은 제 2절연막(27-1)의 단차를 완전히 없애기 위하여 열처리하여 제 2도의 (바)와 같이 평탄화공정을 실시하므로 단차가 없는 제 2절연막(27-2)을 형성한다.In order to completely eliminate the step difference of the second insulating film 27-1 remaining in the peripheral region 23, the planarization process is performed as shown in FIG. 2B to form a second insulating film 27-2 having no step. .
평탄화공정은 제 1절연막의 종류에 따라 다음과 같이 실시한다.The planarization process is performed as follows according to the type of the first insulating film.
제 1 절연막이 ILD인 경우의 글로벌 평판화는 제 2 절연막을 어닐플로잉하여 수행되며, 400℃ 내지 900℃의 범위에서 실시하고, 제 1 절연막 IMD인 경우에는 하부의 금속배선 고려하여 400℃ 미만으로 제 2 절연막을 열처리하여 상온에서 450℃ 까지의 범위에서 플로잉하여 평탄화한다.Global flattening when the first insulating film is an ILD is performed by annealing the second insulating film, and is performed in the range of 400 ° C. to 900 ° C., and in the case of the first insulating film IMD, it is less than 400 ° C. considering the lower metal wiring. The second insulating film is then heat-treated to flow in a range from room temperature to 450 ° C. for flattening.
이와 같이 본 발명의 글로벌평탄화방법을 적용한 효과는 다음과 같다.Thus, the effects of applying the global flattening method of the present invention are as follows.
고도가 특별히 낮은 영역만을 단차 높이만큼 국부적으로 높혀 글로벌평탄화를 이룰 수 있으므로 셀영역의 절연막의 두께에 영향을 주지않으므로 셀영역에 대한 손상이 없다.Since only a region with a particularly low altitude can be locally raised by the height of the step, global flattening can be achieved, and thus there is no damage to the cell region since it does not affect the thickness of the insulating layer of the cell region.
에치백 공정 또는 CMP공정에서 글로벌평탄화시 문제가 되는 셀영역의 모서리(22-1)에서의 구조손상을 방지하는 효과가 있다.In the etch back process or the CMP process, there is an effect of preventing structural damage at the edge 22-1 of the cell region, which is a problem in global flattening.
적용공정에 따라 온도를 조절할 수 있으므로 하층에 대한 손상을 방지할 수 있다.The temperature can be adjusted according to the application process to prevent damage to the lower layer.
제 1도는 종래의 기술을 도시한 것이고,1 shows a conventional technique,
제 2 도는 본 발명에 의한 글로벌평탄화방법을 도시한 것이다.2 shows a global leveling method according to the present invention.
※ 도면 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
14,24. 반도체기판 21. 제 1절연막14,24. Semiconductor Substrate 21. First Insulation Film
12,22. 셀영역 13,23. 주변영역12,22. Cell area 13,23. Surrounding area
15,25. 구조단차 16,26. 절연막단차15,25. Structure step 16,26. Insulation film
27,27-1,27-2. 제 2절연막 28. 마스크패턴27,27-1,27-2. Second insulating film 28. Mask pattern
29. 겹침부위 22-1. 셀영역모서리29. Overlap 22-1. Cell Area Corner
11. 절연막 17. 층간절연막11. insulating film 17. interlayer insulating film
18. 최종단가 19. 1층금속배선18. Final Unit Cost 19. Single Layer Metal Wiring
Claims (5)
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| KR1019940010460A KR100361519B1 (en) | 1994-05-13 | 1994-05-13 | Global planarization method |
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