KR100340858B1 - Method for fabricating metal interconnection of semiconductor device - Google Patents
Method for fabricating metal interconnection of semiconductor device Download PDFInfo
- Publication number
- KR100340858B1 KR100340858B1 KR1019950069537A KR19950069537A KR100340858B1 KR 100340858 B1 KR100340858 B1 KR 100340858B1 KR 1019950069537 A KR1019950069537 A KR 1019950069537A KR 19950069537 A KR19950069537 A KR 19950069537A KR 100340858 B1 KR100340858 B1 KR 100340858B1
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- South Korea
- Prior art keywords
- film
- metal wiring
- forming
- interlayer insulating
- lower electrode
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 더욱 상세하게는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
일반적으로, 반도체 기판상에서 소자와 소자간을 전기적으로 연결하기 위해 금속배선이 형성된다. 이것을 위한 종래의 방법은 우선, 게이트 전극, 소오스/드레인 전극 또는 하층 금속배선과 같은 하부 전극이 형성된 반도체 기판의 상부에 층간 절연막을 형성하고, 상기의 하부 전극이 노출되도록 사진식각법으로 식각을 실시하므로써 콘택홀을 형성한다. 그런 다음, 상기 콘택홀에 텅스텐등의 금속을 매립하여 콘택을 형성한 다음, 전체 구조 상부에 금속막을 적층하고 식각을 실시하여 소정의 금속배선을 형성하는 것으로 이루어진다.Generally, metal wirings are formed on the semiconductor substrate to electrically connect the devices with the devices. In the conventional method for this, first, an interlayer insulating film is formed on a semiconductor substrate on which a lower electrode such as a gate electrode, a source / drain electrode, or a lower metal wiring is formed, and etching is performed by photolithography to expose the lower electrode. This forms a contact hole. Then, a contact is formed by embedding a metal such as tungsten in the contact hole, and then a metal film is stacked and etched on the entire structure to form a predetermined metal wiring.
그러나 상기의 금속막을 적층할 때, 금속막은 콘택을 완전히 오버랩(overlap)해야 하며, 그렇지 않은 경우 금속배선을 형성하는 과정에서 콘택 하부의 하부 전극이 손상을 입게 되어 소자의 신뢰도에 악영향을 미치게 된다.However, when the metal film is stacked, the metal film must completely overlap the contact, otherwise the lower electrode under the contact is damaged in the process of forming the metal wiring, which adversely affects the reliability of the device.
그러므로, 접속 소자 설계시 콘택 마스크와 전극 마스크는 일정한 설계 규칙에 따라야 한다. 즉, 상부 전극을 하부 전극에 접속시키기 위한 콘택 마스크와 상부 금속배선을 설계하기 위하여 상부 전극이 항상 콘택을 오버랩해야 하므로 콘택과 상부 전극 마스크 사이에는 마스크 제작시 발생되는 레지스트레이션(registration), CD 편차, 그리고 웨이퍼상에 패턴을 형성할 때 발생되는 미스얼라인먼트(mis-alignment) 허용오차, 렌즈 디스토션(lenz distortion), CD 편차가 고려되어야 하며, 또한 마스크 작업시 전극의 폭이나 간격에 비해 콘택의 최소 크기가 0.05 내지 0.1㎛ 정도 더 크게 되어야 한다. 따라서, 이러한 항목이 고려된 만큼 접속 소자의 크기가 증가된다는 문제점이 있었다.Therefore, the contact mask and the electrode mask should follow certain design rules when designing the connection element. That is, in order to design the contact mask and upper metal wiring for connecting the upper electrode to the lower electrode, the upper electrode should always overlap the contact, so that the registration, CD deviation, In addition, the mis-alignment tolerance, lens distortion, and CD deviation that occur when forming patterns on the wafer should be taken into account, and the minimum size of the contact compared to the width or spacing of the electrodes when masking. Should be larger than 0.05 to 0.1 mu m. Therefore, there has been a problem that the size of the connection element is increased by considering these items.
따라서, 본 발명의 목적은 상기의 문제점을 해결하기 위하여 안출된 것으로서, 상부의 금속배선과 콘택의 오버랩을 최소화하여 접속부분의 면적을 현저히 감소시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to solve the above problems, to provide a method for forming a metal wiring of the semiconductor device that can significantly reduce the area of the connection portion by minimizing the overlap of the upper metal wiring and the contact. .
상기의 목적을 달성하기 위하여, 본 발명의 반도체 소자의 금속배선 형성방법은,In order to achieve the above object, the metal wiring forming method of the semiconductor device of the present invention,
(가) 하부 전극이 형성된 반도체 기판상에 층간 절연막을 형성한 후, 평탄화하는 단계;(A) forming an interlayer insulating film on the semiconductor substrate on which the lower electrode is formed, and then planarizing it;
(나) 상기의 층간 절연막상에 접착 보조막을 형성하는 단계;(B) forming an adhesive auxiliary film on the interlayer insulating film;
(다) 상기의 하부 전극이 노출되도록 상기의 접착 보조막 및 층간 절연막을 사진식각법으로 선택적으로 식각하여 콘택홀을 형성하는 단계;(C) forming a contact hole by selectively etching the adhesive auxiliary layer and the interlayer insulating layer by photolithography so as to expose the lower electrode;
(라) 상기의 콘택홀의 내부 및 주변부 전면에 식각장벽용 텅스텐막을 형성한 후, 에치백하여 텅스텐 플러그를 형성하는 단계; 및(D) forming a tungsten film for etching barrier on the inside of the contact hole and the entire surface of the contact portion, and then etching back to form a tungsten plug; And
(마) 상기 전체 구조 상부에 소정의 금속배선을 형성하는 단계를 포함하는 것을 특징으로 한다.(E) forming a predetermined metal wiring on the entire structure.
본 발명에 의하면, 층간 절연막에 형성되는 콘택홀내에 금속배선에 대한 식각장벽용 텅스텐을 형성하므로써, 금속배선과 콘텍의 오버랩을 최소화하여 접속 부분의 면적을 현저히 감소시킬 수 있다.According to the present invention, by forming the tungsten for the etching barrier against the metal wiring in the contact hole formed in the interlayer insulating film, the overlap between the metal wiring and the contact can be minimized and the area of the connection portion can be significantly reduced.
이하, 본 발명이 일실시예를 첨부도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 1 도의 (가) 내지 (다)는 본 발명의 일실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 도면이다.1 (a) to (c) are views for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
우선, 제 1 도의 (가)에서 도시된 바와같이, 반도체 기판(1)의 소정부분에 소자분리 절연막(2)을 형성한 후, 소오스/드레인 전극(3)을 형성한 다음, 전체 구조 상부에 BPSG막과 같은 층간 절연막(4)을 형성하고, 비스코스 플로우가 일어나는온도 이상에서 열처리하거나, 화학기계적 연마법으로 연마하여 평탄화시킨다. 그런 다음, 실리콘막 또는 Ti, TiN, 또는 Ti/TiN 이중구조의 접착 보조막을 형성하고, 소오스/드레인 전극(3)의 소정부분이 노출되도록 접착 보조막(5) 및 층간 절연막(4)을 사진식각법으로 식각하여 콘택홀(10)을 형성한 다음, 콘택홀의 내부 및 주변부 전면에 식각장벽막으로서 텅스텐막(6)을 형성한다.First, as shown in FIG. 1A, a device isolation insulating film 2 is formed on a predetermined portion of the semiconductor substrate 1, and then a source / drain electrode 3 is formed. An interlayer insulating film 4, such as a BPSG film, is formed and heat-treated above the temperature at which the viscose flow occurs, or it is ground by polishing by chemical mechanical polishing. Then, an adhesion auxiliary film 5 and an interlayer insulating film 4 are formed to form a silicon film or an adhesion auxiliary film having a Ti, TiN, or Ti / TiN double structure, and to expose a predetermined portion of the source / drain electrode 3. After etching by etching, the contact hole 10 is formed, and then a tungsten film 6 is formed as an etch barrier film on the inside of the contact hole and the entire surface of the periphery.
그리고나서, (나)에서 도시된 바와같이, 텅스텐막을 에치백시켜서 텅스텐 플러그(6A)를 형성한 다음, 전체 구조 상부에 Al, Ti/Al의 이중 구조, 또는 Ti/TiN/Al의 3중 구조의 금속막(7)을 형성한다.Then, as shown in (b), the tungsten film is etched back to form a tungsten plug 6A, and then a double structure of Al, Ti / Al, or a triple structure of Ti / TiN / Al is formed over the entire structure. A metal film 7 is formed.
이어서, 상기 금속막(7)의 상부에 콘택을 완전히 오버랩시키지 않은 소정의 마스크 패턴(8)을 형성한 다음에, 그의 형태로 식각을 실시하고 마스크 패턴(8)을 제거하여 (다)에서 도시된 바와같이, 소정의 금속배선(7A)을 형성한다. 이때, 금속배선 마스크(8)에 의해 노출된 콘택홀내에서는 텅스텐 플러그(6A)에 의해 식각되지 않으므로써 소오스/드레인 전극(3)이 손상되지 않는다.Subsequently, a predetermined mask pattern 8 is formed on the upper portion of the metal film 7 without completely overlapping the contact, and then etched in the form thereof, and the mask pattern 8 is removed, as shown in (C). As shown, the predetermined metal wiring 7A is formed. At this time, the source / drain electrodes 3 are not damaged by being not etched by the tungsten plug 6A in the contact holes exposed by the metal wiring mask 8.
이상에서와 같이 본 실시예에 의하면, 금속배선과 콘택의 오버랩을 최소화하므로써 접속부분의 면적을 현저히 감소시킬 수 있다.As described above, according to the present embodiment, the area of the connection portion can be significantly reduced by minimizing the overlap between the metal wiring and the contact.
또한, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention is not limited to said Example, It can variously change and implement in the range which does not deviate from the summary.
제 1 도의 (가) 내지 (다)는 본 발명의 일실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 도면1A to 1C are views for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 소자분리 절연막1 semiconductor substrate 2 device isolation insulating film
3 : 소오스/드레인 전극 4 : 층간 절연막3: source / drain electrode 4: interlayer insulating film
5 : 접착 보조막 6 : 텅스텐막5: adhesion auxiliary film 6: tungsten film
6A : 텅스텐 플러그 7 : 금속막6A: tungsten plug 7: metal film
7A : 금속배선 8 : 마스크 패턴7A: Metal Wiring 8: Mask Pattern
10 : 콘택홀10: contact hole
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069537A KR100340858B1 (en) | 1995-12-30 | 1995-12-30 | Method for fabricating metal interconnection of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069537A KR100340858B1 (en) | 1995-12-30 | 1995-12-30 | Method for fabricating metal interconnection of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970052505A KR970052505A (en) | 1997-07-29 |
| KR100340858B1 true KR100340858B1 (en) | 2002-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950069537A KR100340858B1 (en) | 1995-12-30 | 1995-12-30 | Method for fabricating metal interconnection of semiconductor device |
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| KR (1) | KR100340858B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100894769B1 (en) * | 2006-09-29 | 2009-04-24 | 주식회사 하이닉스반도체 | Method of forming a metal wire in a semiconductor device |
-
1995
- 1995-12-30 KR KR1019950069537A patent/KR100340858B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100894769B1 (en) * | 2006-09-29 | 2009-04-24 | 주식회사 하이닉스반도체 | Method of forming a metal wire in a semiconductor device |
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| Publication number | Publication date |
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| KR970052505A (en) | 1997-07-29 |
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