JPH0287621A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0287621A JPH0287621A JP24147088A JP24147088A JPH0287621A JP H0287621 A JPH0287621 A JP H0287621A JP 24147088 A JP24147088 A JP 24147088A JP 24147088 A JP24147088 A JP 24147088A JP H0287621 A JPH0287621 A JP H0287621A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- forming
- interlayer insulating
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 14
- 239000011229 interlayer Substances 0.000 abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に電極配線
用のコンタクト孔の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming contact holes for electrode wiring.
従来、多層配線構造の半導体装置の製造においては、下
部配線と上部配線との間に層間絶縁膜を設け、層間絶縁
膜にコンタクト孔を設けて、下部配線と上部配線の接続
を行っている。Conventionally, in manufacturing a semiconductor device with a multilayer wiring structure, an interlayer insulating film is provided between a lower wiring and an upper wiring, and a contact hole is provided in the interlayer insulating film to connect the lower wiring and the upper wiring.
第２図（ａ）〜（ｄ）は従来の半導体装置の製造方法を
説明するための工程順に配置した半導体チップの断面図
である。FIGS. 2(a) to 2(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a conventional method of manufacturing a semiconductor device.
まず、第２図（ａ）に示すように、Ｐ型シリコ基板１の
一主表面に熱酸化法により酸化シリコン膜２を形成し、
次に、多結晶シリコン膜を所定の形状にパターニングし
てゲート電極３を形成する。次に、この多結晶シリコン
膜をマスクにして酸化シリコン膜２を通してイオン注入
法により基板と反対導電型、即ちＮ型を与える不純物を
基板に導入して拡散層領域４−１．４−２ （ソース・
ドレイン領域）を形成する。First, as shown in FIG. 2(a), a silicon oxide film 2 is formed on one main surface of a P-type silicon substrate 1 by a thermal oxidation method.
Next, the gate electrode 3 is formed by patterning the polycrystalline silicon film into a predetermined shape. Next, using this polycrystalline silicon film as a mask, an impurity that gives conductivity type opposite to that of the substrate, that is, N type, is introduced into the substrate by ion implantation through the silicon oxide film 2, and the diffusion layer region 4-1.4-2 ( sauce·
drain region).
次に酸化シリコン膜２と多結晶シリコン膜（３）上に気
相成長法によりリンを含有したＰＳＧからなる層間絶縁
膜５を形成する。Next, an interlayer insulating film 5 made of PSG containing phosphorus is formed on the silicon oxide film 2 and the polycrystalline silicon film (3) by vapor phase growth.
次に第２図（ｂ）に示すように、眉間絶縁膜５上にホト
レジスト膜で所定のパターンのホトレジストマスク６を
形成する。Next, as shown in FIG. 2(b), a photoresist mask 6 having a predetermined pattern is formed on the glabella insulating film 5 using a photoresist film.
次に、第２図（ｃ）に示すように、眉間絶縁膜５、酸化
シリコン膜２に異方性エツチングでコンタクト孔７−１
．７−２を設けたのちホトレジストマスク６を除去する
。Next, as shown in FIG. 2(c), contact holes 7-1 are formed in the glabella insulating film 5 and the silicon oxide film 2 by anisotropic etching.
．． After providing the photoresist mask 7-2, the photoresist mask 6 is removed.
次に、第２図（ｄ）に示すように、その上にアルミニウ
ム電極８−１．８−２を形成する。Next, as shown in FIG. 2(d), aluminum electrodes 8-1, 8-2 are formed thereon.
上述した従来の半導体装置の製造方法において、眉間絶
縁膜をホトレジストマスクを用いて、異方性エツチング
するとＰ型シリコン基板および多結晶シリコン膜が第２
図（ｄ）のようにオーバーエッチされ、異方性エツチン
グにより表面がダメージをうけるので、アルミニウム電
極との接触が悪くなり、トランジスター特性が不安定に
なるという問題がある。In the conventional semiconductor device manufacturing method described above, when the glabella insulating film is anisotropically etched using a photoresist mask, the P-type silicon substrate and the polycrystalline silicon film are
As shown in Figure (d), the surface is overetched and damaged by anisotropic etching, resulting in poor contact with the aluminum electrode and unstable transistor characteristics.
本発明の目的は、良好なコンタクト特性の得られる半導
体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that provides good contact characteristics.
本発明の半導体装置の製造方法は 半導体基板の一生表
面に第１の絶縁膜を形成する工程と、前記第１の絶縁膜
上に多結晶シリコン膜のゲート電極を形成する工程と、
前記ゲート電極をマスクとしてイオン注入を行ない前記
半導体基板の所定の部分にソース・ドレイン領域を形成
する工程と、前記第１の絶縁膜と前記多結晶シリコン股
上に第２の絶縁膜を形成する工程と、前記第２の絶縁膜
上に第３の絶縁膜を形成する工程と、前記第２の絶縁膜
をエツチング阻止層として選択的に前記第３の絶縁膜を
除去したのち、底部に残った前記第２の絶縁膜及び第１
の絶縁膜を除去してコンタクト孔を形成する工程と、そ
の後電極配線を設ける工程とを含むというものである。The method for manufacturing a semiconductor device of the present invention includes: forming a first insulating film on the entire surface of a semiconductor substrate; forming a gate electrode of a polycrystalline silicon film on the first insulating film;
A step of performing ion implantation using the gate electrode as a mask to form a source/drain region in a predetermined portion of the semiconductor substrate, and a step of forming a second insulating film on the first insulating film and the polycrystalline silicon crotch. forming a third insulating film on the second insulating film; selectively removing the third insulating film using the second insulating film as an etching stopper layer; the second insulating film and the first
The method includes a step of removing the insulating film to form a contact hole, and then a step of providing electrode wiring.
次に本発明の実施例について図面を用いて説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図である。FIGS. 1A to 1E are cross-sectional views of semiconductor chips arranged in the order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｐ型シリコン基板１
の一生表面に熱酸化法により酸化シリコン膜１２（第１
の絶縁膜）を形成し、次に多結晶シリコン膜を被着し所
定の形状にパターニングしてゲート電極１３を形成する
。First, as shown in FIG. 1(a), a P-type silicon substrate 1
A silicon oxide film 12 (first
(insulating film) is formed, and then a polycrystalline silicon film is deposited and patterned into a predetermined shape to form the gate electrode 13.
次に多結晶シリコン膜（１３）をマスクにして酸化シリ
コン膜１２を通してイオン注入法により基板と反対導電
型、即ちＮ型を与える不純物を基板に導入して拡散層領
域１．４−１．１４−２を形成する。Next, using the polycrystalline silicon film (13) as a mask, an impurity that provides conductivity type opposite to that of the substrate, that is, N type, is introduced into the substrate through the silicon oxide film 12 by ion implantation to form diffusion layer regions 1.4-1.14. -2 is formed.
次に酸化シリコン膜１２と多結晶シリコン膜（１３）上
に気相成長法により酸化シリコン膜１９（第２の絶縁膜
）を形成した後、第１図（ｂ）に示すように、気相成長
法によりリンを含有しなＰＳＧ（リンケイ酸ガラス）か
らなる眉間絶縁膜１５（第３の絶縁膜）を形成する。Next, after forming a silicon oxide film 19 (second insulating film) on the silicon oxide film 12 and the polycrystalline silicon film (13) by vapor phase growth, as shown in FIG. A glabellar insulating film 15 (third insulating film) made of PSG (phosphosilicate glass) that does not contain phosphorus is formed by a growth method.
次に第１図（Ｃ）に示すように、眉間絶縁膜１５上にホ
トレジスト膜からなる所定のパターンのホトレジストマ
スク１６を形成する。Next, as shown in FIG. 1C, a photoresist mask 16 of a predetermined pattern made of a photoresist film is formed on the glabellar insulating film 15.
次に第１図（ｄ）に示すように眉間絶縁膜１５に異方性
ドライエツチング（プラズマエツチング）により開孔を
設ける。この時、エツチングガスとしてＣＦ４を使用す
ると酸化シリコン膜１つがエツチング素子層となり、多
結晶シリコン膜およびＰ型シリコン基板を保護する役目
を行う。Next, as shown in FIG. 1(d), holes are formed in the glabellar insulating film 15 by anisotropic dry etching (plasma etching). At this time, if CF4 is used as the etching gas, one silicon oxide film becomes an etching element layer and serves to protect the polycrystalline silicon film and the P-type silicon substrate.
次に、第１図（ｅ）に示すように、開口部の底に残った
窒化コンタクト膜１９と酸化シリコン膜１２を除去して
コンタクト孔を完成した後アルミニウム電極１８−１．
１８−２を形成する。Next, as shown in FIG. 1(e), the nitride contact film 19 and silicon oxide film 12 remaining at the bottom of the opening are removed to complete the contact hole, and then the aluminum electrode 18-1.
18-2 is formed.
〔発明の効果〕
以上説明したように本発明は、層間絶縁膜にコンタクト
開孔を形成する時に異方性ドライエツチングのエツチン
グ阻止層を層間絶縁膜の下に予め設けておくことにより
、多結晶シリコン膜からなるゲート電極およびシリコン
基板にダメージを与えないので電極配線のコンタクト特
性の良好な半導体装置を製造することができる効果があ
る。[Effects of the Invention] As explained above, the present invention provides an etching prevention layer for anisotropic dry etching under the interlayer insulating film in advance when forming contact holes in the interlayer insulating film. Since the gate electrode made of a silicon film and the silicon substrate are not damaged, it is possible to manufacture a semiconductor device with good electrode wiring contact characteristics.
第１図（ａ）〜（ｅ＞は、本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図、第２図（
ａ）〜（ｄ）は従来例を説明するための製造工程順に示
した半導体チップの断面図である。
１．１１・・・Ｐ型車結晶シリコン基板、２，１２・・
・酸化シリコン膜、３．１３・・・ゲート電極（多結晶
シリコン膜）、４−１．４−２．１４−１゜１４−２・
・・Ｎ４型不純物領域、５，１５・・・層間絶縁膜、６
，１６・・・ホトレジストマスク、７−１゜７−２・・
・コンタクト孔、８−１．８−２，１８１．１８−２・
・・アルミニウム電極、１９・・・酸化シリコン膜。FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG.
1A to 1D are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps to explain a conventional example. 1.11...P-type wheel crystal silicon substrate, 2,12...
・Silicon oxide film, 3.13... Gate electrode (polycrystalline silicon film), 4-1.4-2.14-1°14-2・
...N4 type impurity region, 5, 15... Interlayer insulating film, 6
, 16... Photoresist mask, 7-1゜7-2...
・Contact hole, 8-1.8-2, 181.18-2・
...Aluminum electrode, 19...Silicon oxide film.
Claims (1)
、前記第１の絶縁膜上に多結晶シリコン膜のゲート電極
を形成する工程と、前記ゲート電極をマスクとしてイオ
ン注入を行ない前記半導体基板の所定の部分にソース・
ドレイン領域を形成する工程と、前記第１の絶縁膜と前
記多結晶シリコン膜上に第２の絶縁膜を形成する工程と
、前記第２の絶縁膜上に第３の絶縁膜を形成する工程と
、前記第２の絶縁膜をエッチング阻止層として選択的に
前記第３の絶縁膜を除去したのち、底部に残つた前記第
２の絶縁膜及び第１の絶縁膜を除去してコンタクト孔を
形成する工程と、その後電極配線を設ける工程とを含む
ことを特徴とする半導体装置の製造方法。a step of forming a first insulating film on one main surface of a semiconductor substrate; a step of forming a gate electrode of a polycrystalline silicon film on the first insulating film; and performing ion implantation using the gate electrode as a mask. A source and a specified part of the semiconductor substrate
a step of forming a drain region, a step of forming a second insulating film on the first insulating film and the polycrystalline silicon film, and a step of forming a third insulating film on the second insulating film. After selectively removing the third insulating film using the second insulating film as an etching stopper layer, the second insulating film and the first insulating film remaining at the bottom are removed to form a contact hole. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device and a step of subsequently providing an electrode wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24147088A JPH0287621A (en) | 1988-09-26 | 1988-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24147088A JPH0287621A (en) | 1988-09-26 | 1988-09-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0287621A true JPH0287621A (en) | 1990-03-28 |
Family
ID=17074792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24147088A Pending JPH0287621A (en) | 1988-09-26 | 1988-09-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0287621A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5827778A (en) * | 1995-11-28 | 1998-10-27 | Nec Corporation | Method of manufacturing a semiconductor device using a silicon fluoride oxide film |
| JP2007048837A (en) * | 2005-08-08 | 2007-02-22 | Sharp Corp | Manufacturing method of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61247073A (en) * | 1985-04-24 | 1986-11-04 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
-
1988
- 1988-09-26 JP JP24147088A patent/JPH0287621A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61247073A (en) * | 1985-04-24 | 1986-11-04 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5827778A (en) * | 1995-11-28 | 1998-10-27 | Nec Corporation | Method of manufacturing a semiconductor device using a silicon fluoride oxide film |
| JP2007048837A (en) * | 2005-08-08 | 2007-02-22 | Sharp Corp | Manufacturing method of semiconductor device |
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