KR920007824B1 - Contacting device of semiconductor elements - Google Patents

Contacting device of semiconductor elements Download PDF

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KR920007824B1
KR920007824B1 KR1019890001968A KR890001968A KR920007824B1 KR 920007824 B1 KR920007824 B1 KR 920007824B1 KR 1019890001968 A KR1019890001968 A KR 1019890001968A KR 890001968 A KR890001968 A KR 890001968A KR 920007824 B1 KR920007824 B1 KR 920007824B1
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conductive layer
layer
conductive
insulating
contact hole
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KR900013583A (en
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정인술
김진형
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현대전자산업 주식회사
정몽헌
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

The connection device for forming an insulation spacer to insulate an upper conduction layer from a middle conduction layer and to connect the upper layer to a lower conduction layer to reduce the cell size is manufactured by forming a first conduction region (2) with a high concentration diffusion layer on a Si substrate (1), laminating a first insulation layer (3), a second conduction layer (4) and a second insulation layer (5) thereon, removing the predetermined portions of the layers (5)(4)(3) to expose the region (2) to form contact hole (20), forming an insulation spacer (8A) on the side wall of the contact hole, and forming a third conduction layer (6) on the layer (5).

Description

반도체 소자의 접속장치Semiconductor device connection device

제1a도 내지 제1f도는 본 발명의 제1실시예에 의해 반도체 소자의 접속장치를 제조하는 단계를 도시한 단면도.1A to 1F are cross-sectional views showing steps for manufacturing a semiconductor device connection device according to a first embodiment of the present invention.

제2a도 및 제2b도는 본 발명의 제2실시예에 의해 반도체 소자의 접속장치를 제조하는 단계를 도시한 단면도.2A and 2B are sectional views showing the steps of manufacturing a connection device of a semiconductor device according to a second embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 제1전도영역1 silicon substrate 2 first conductive region

3 : 제1절연층 4 : 제2전도층3: first insulating layer 4: second conductive layer

5 : 제2절연층 6 : 제3전도층5: second insulating layer 6: third conductive layer

7 : 감광막 패턴 8 : 스페이서용 절연층7: photosensitive film pattern 8: insulating layer for spacer

9 : 식각베리어층 8A : 절연스페이서9: etching barrier layer 8A: insulation spacer

10 : 제4전도층 20 : 콘택홀10: fourth conductive layer 20: contact hole

본 발명은 고접적 반도체 소자의 접속장치에 관한 것으로, 특히 상부의 전도층을 중앙부의 전도층과는 절연시키고 하부의 전도층 접속시키기 위하여 절연스페이서를 형성한 반도체 소자의 접속장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a connection device for a highly integrated semiconductor device, and more particularly, to a semiconductor device connection device in which an insulating spacer is formed to insulate an upper conductive layer from a conductive layer in a center and to connect a lower conductive layer.

종래의 기술로 이루어진 다층전도층의 접속장치에서, 상부의 전도층을 중앙부의 전도층과는 절연시키고 하부의 전도층에 접속하기 위해서는 상부의 전도층과 하부의 전도층이 접속되는 접속영역이 중앙부의 전도층과는 겹치지 않도록 형성해야 하므로 셀의 크기가 증대되는 문제점이 있었다.In the connection apparatus of the conventional multilayer conductive layer, in order to insulate the upper conductive layer from the conductive layer in the center and to connect the conductive layer in the lower portion, the connection area where the upper conductive layer and the lower conductive layer are connected is the central portion. It should be formed so as not to overlap with the conductive layer of there was a problem that the size of the cell is increased.

따라서, 본 발명은 상기의 셀의 크기가 증대되는 문제점을 해결하기 위해 상부, 중앙부, 하부에 형성되는 각각의 전도층을 중첩시키게 하되, 상기 접속영역의 상부, 중앙부의 전도층을 제거하여 콘택홀을 형성하고 콘택홀 측벽에 절연스페이서를 형성한후 전도층을 중착하여 상부의 전도층을 중앙부 전도층과 절연시키고 하부의 전도층에 접속시킨 반도체 접속장치를 제공하는 그 목적이 있다.Accordingly, in order to solve the problem of increasing the size of the cell, the present invention overlaps the conductive layers formed on the upper, middle, and lower portions, but removes the conductive layers on the upper and center portions of the connection region. The purpose of the present invention is to provide a semiconductor connecting device in which a conductive spacer is formed by insulating the spacer layer on the sidewalls of the contact hole, and the upper conductive layer is insulated from the central conductive layer and connected to the lower conductive layer.

이하, 첩부된 도면을 참고하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the attached drawings.

제1a도 내지 제1b도는 본 발명의 제1실시예에 의해 다층전도층의 제3전도층을 제2전도층과는 절연시키고 제1전도층에 접속시킨 접속장치의 제조방법을 도시한 단면도이다.1A to 1B are cross-sectional views illustrating a method for manufacturing a connecting device in which a third conductive layer of a multilayer conductive layer is insulated from a second conductive layer and connected to a first conductive layer according to a first embodiment of the present invention. .

제1a도는 실리콘 기판(1)내의 예정된 부분에 고농도 확산영역인 제1전도영역(2)을 형성하고, 실리콘 기판(1) 상부에 제1절연층(3), 제2전도층(4), 제2절연층(5) 및 식각베리어층(9)을 순차적으로 형성한 상태로 단면도로서, 상기 제1절연층 및 제2절연층(3 및 5)은 예를들어 산화막, 제2전도층(4)은 예를들어 도프된 폴리실리콘층, 식각베리어층(9)은 제2절연층(5)과 식각선택비가 다른 예를들어 질화막으로 각각 형성 할 수 있다.FIG. 1A shows a first conductive region 2, which is a high concentration diffusion region, in a predetermined portion of the silicon substrate 1, and the first insulating layer 3, the second conductive layer 4, A cross-sectional view of the second insulating layer 5 and the etching barrier layer 9 sequentially formed, wherein the first insulating layer and the second insulating layers 3 and 5 are formed of, for example, an oxide film and a second conductive layer ( 4), for example, the doped polysilicon layer and the etching barrier layer 9 may be formed of nitride films, for example, in which the etching selectivity is different from that of the second insulating layer 5.

제1b도는 상기 식각베리어층(9)에 콘택마스크용 감광막 패턴(7)을 형성한 상태의 단면도이다.1B is a cross-sectional view of the contact barrier photosensitive film pattern 7 formed on the etch barrier layer 9.

제1c도는 감광막 패턴(7)을 이용하여 노출되는 식각베리어층(9), 제2절연층(5), 제2전도층(4), 제1절연층(3)을 순차적으로 식각하여 하부의 제1전도영역(2)이 노출된 콘택홀(20)을 형성하고, 상부의 감광막 패턴(7)을 완전히 제거한 상태의 단면도이다FIG. 1C illustrates the etching barrier layer 9, the second insulating layer 5, the second conductive layer 4, and the first insulating layer 3 which are exposed using the photoresist pattern 7. A cross-sectional view of a state in which the contact hole 20 exposing the first conductive region 2 is formed and the upper photoresist pattern 7 is completely removed.

제1d도는 전체구조 상부에 스페이서용 절연층(8)을 일정두께로 형성한 상태의 단면도이다.FIG. 1D is a cross-sectional view of a spacer with an insulating layer 8 formed on the entire structure at a predetermined thickness.

제1e도는 상기 스페이서용 절연층(8)을 비등방성 식각으로 콘택홀(20)의 측면벽에 절연스페이서(8A)를 형성한 상태의 단면도이다. 여기서 스페이서용 절연층(8)을 식각할때 식각베리어층(9)이 식각정지층으로 사용된다.FIG. 1E is a cross-sectional view of an insulating spacer 8A formed on the sidewall of the contact hole 20 by anisotropic etching of the spacer insulating layer 8. The etching barrier layer 9 is used as an etching stop layer when the spacer insulating layer 8 is etched.

제1f도는 상기 식각베리이층(9)을 제거하고, 콘택홀(20)과 제2절연층(5) 상부에 제3전도층(6)을 중착하여 제3전도층(6)을 제1전도영역(2)에 접속시키되, 제3전도층(6)이 제2전도층(4)과는 절연스페이서(8A)에 의해 절연된 상태를 도시한 단면도이다.FIG. 1f illustrates that the etch barrier layer 9 is removed, and the third conductive layer 6 is deposited on the contact hole 20 and the second insulating layer 5 so that the third conductive layer 6 is first conductive. Although it is connected to the area | region 2, it is sectional drawing which shows the state in which the 3rd conductive layer 6 was insulated from the 2nd conductive layer 4 by the insulation spacer 8A.

제2a도 및 제2b도는 본 발명의 제2실시예에 의해 다층전도층의 제3전도층을 제2전도층과는 절연시키고 제1전도층에 접속시킨 제조방법을 도시한 단면도이다.2A and 2B are sectional views showing the manufacturing method in which the third conductive layer of the multilayer conductive layer is insulated from the second conductive layer and connected to the first conductive layer according to the second embodiment of the present invention.

제2a도는 실리콘 기판(1)내의 예정된 부분에 고농도 확산영역인 제1전도영역(2)을 형성하고, 실리콘 기판(1) 상부에 제1절연층(3), 제2전도층(4), 제2절연층(5) 및 제3전도층(6)을 순차적으로 형성한 후에 콘택마스크용 감광막 패턴(도시안됨)을 이용하여 제3전도층(6), 제2절연층(5), 제2전도층(4), 제1절연층(3)을 제거한 콘택홀(20)을 형성한 후, 콘택홀(20) 측벽에 절연스페이서(8A)를 형성한 상태의 단면도로서, 제1a 내지 제1b도와 유사한 공정으로 진행하나 식각베리어층(9) 대신에 제3전도층(6)을 형성한 것이 다른점이다.2A shows a first conductive region 2, which is a high concentration diffusion region, in a predetermined portion of the silicon substrate 1, and the first insulating layer 3, the second conductive layer 4, After the second insulating layer 5 and the third conductive layer 6 are sequentially formed, the third conductive layer 6, the second insulating layer 5, and the second conductive layer are formed by using a photoresist pattern (not shown) for the contact mask. A cross-sectional view of a state where the insulating spacer 8A is formed on the sidewall of the contact hole 20 after forming the contact hole 20 from which the second conductive layer 4 and the first insulating layer 3 are removed. The process is similar to that of FIG. 1b, except that the third conductive layer 6 is formed instead of the etching barrier layer 9.

제2b도는 전체구조 상부에 제4전도층(10)을 예정된 두께로 중착하여 상기의 제3전도층(6)과 콘택홀(20) 저부의 제1전도영역(2)을 상호접속시킨 상태의 단면도이다.FIG. 2B shows a state in which the fourth conductive layer 10 is stacked to a predetermined thickness on the entire structure to interconnect the first conductive region 2 of the bottom of the third conductive layer 6 and the contact hole 20. It is a cross section.

또한, 상기한 본 발명의 제1및 제2실시예를 기초로 하여 본 발명의 제3실시예를 나타낼 수 있는데, 즉 다층구조의 전도층을 제1전도층, 제1절연층, 제2전도층, 제2절연층, 제3전도층, 제3절연층, 제4전도층, 제4절연층, 제5전도층을 순차적으로 적층시킨 제5전도층을 접속하고자 하는 전도층(예를들어 제3, 제2또는 제1전도층)이 노출되도록 콘택홀을 형성한 후, 콘택홀 측벽에 절연스페이서를 형성하고, 제6전도층을 증착하여 제5전도층을 예정된 전도층에 접속할 수 있다.Further, on the basis of the first and second embodiments of the present invention described above, the third embodiment of the present invention can be represented, that is, the conductive layer having the multilayer structure is formed of the first conductive layer, the first insulating layer, and the second conductive layer. Conductive layer (for example, to connect a fifth conductive layer in which a layer, a second insulating layer, a third conductive layer, a third insulating layer, a fourth conductive layer, a fourth insulating layer, and a fifth conductive layer are sequentially stacked) After forming the contact hole to expose the third, second or first conductive layer, an insulating spacer may be formed on the sidewall of the contact hole, and the sixth conductive layer may be deposited to connect the fifth conductive layer to the predetermined conductive layer. .

상기한 바와 같이 본 발명은 다층구조의 전도층을 중첩되도록 적층한 후 상부의 전도층을 중앙부의 전도층과는 절연시키면서 하부의 전도층에 선택적으로 접속시킬 수 있으므로 고접적 반도체 소자에서 셀의 면적을 줄일 수 있는 효과가 있다.As described above, the present invention can stack the conductive layers of a multi-layer structure so that the upper conductive layer can be selectively connected to the lower conductive layer while the upper conductive layer is insulated from the conductive layer in the center. There is an effect to reduce.

Claims (5)

반도체 소자의 접속장치에 있어서, 실리콘 시판의 예정된 부분에 고농도 확산영역의 제1전도영역이 형성되고, 상부에서 제1절연층, 제2전도층, 제3절연층이 적층되고, 제2절연층, 제2전도층, 제1절연층의 일정부분이 제거되어 제1전도영역이 노출된 콘택홀이 형성되고, 콘택홀 측벽에 절연스페이서가 형성되고, 제2절연층 상부에 형성되는 제3전도층이 콘택홀을 통해 제1전도영역과는 접속되되, 절연스페이서에 의해 제2전도층과는 절연되는 것을 특징으로 하는 반도체 소자의 접속장치.In a device for connecting a semiconductor device, a first conductive region having a high concentration diffusion region is formed in a predetermined portion of a commercially available silicon, and a first insulating layer, a second conductive layer, and a third insulating layer are stacked on the upper portion, and a second insulating layer. A portion of the second conductive layer and the first insulating layer is removed to form a contact hole exposing the first conductive region, an insulating spacer is formed on the sidewall of the contact hole, and a third conductive layer is formed on the second insulating layer. And the layer is connected to the first conductive region through the contact hole, and is insulated from the second conductive layer by the insulating spacer. 제1항에 있어서, 상기 제2절연층 상부에 제3전도층이 적층되고, 제3전도층, 제2절연층, 제2전도층, 제1절연층이 일정부분이 제거되어 제1전도영역이 노출된 콘택홀이 형성되고, 콘택홀 측벽에 절연스페이서가 형성되고, 제3전도층 상부에 형성되는 제4전도층이 콘택홀을 통하여 노출된 제1전도영역에 접속되되, 제4전도층이 콘택홀 측벽에 형성된 절연스페이서에 의해 제2전도층과는 절연된 것을 포함하는 것을 특징으로 하는 반도체 소자의 접속장치.The first conductive region of claim 1, wherein a third conductive layer is stacked on the second insulating layer, and a portion of the third conductive layer, the second insulating layer, the second conductive layer, and the first insulating layer is removed. The exposed contact hole is formed, an insulating spacer is formed on the sidewall of the contact hole, and a fourth conductive layer formed on the third conductive layer is connected to the exposed first conductive region through the contact hole. And a second conductive layer insulated from the second conductive layer by an insulating spacer formed on the sidewalls of the contact holes. 제1항에 있어서, 제2절연층, 상부에 제3전도층, 제3절연층, 제4전도층, 제4절연층, 제5전도층을 순차적으로 적층한 다음, 상기 제5도층, 제4절연층, 제4전도층,제3절연층, 제3전도층, 제2절연층, 제2전도층, 제2절연층의 일정부분이 제거되어 제1전도영역이 노출된 콘택홀이 형성되고, 콘택홀 측벽에 절연스페이서가 형성되고, 제5전도층 상부에 형성되는 제6전도층이 콘택홀을 통하여 노출된 제1전도영역에 접속되되, 제6전도층이 콘택홀 측벽에 형성된 절연스페이서에 의해 제2, 제3및 제4전도층과는 절연된것을 포함하는 것을 특징으로 하는 반도체 소자의 접속장치.The method of claim 1, wherein the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer are sequentially stacked on the second insulating layer, and then the fifth conductive layer and the fifth conductive layer are stacked. 4, a portion of the fourth conductive layer, the third conductive layer, the third conductive layer, the third conductive layer, the second insulating layer, the second conductive layer, and the second insulating layer is removed to form a contact hole exposing the first conductive region. Insulation spacers are formed on the sidewalls of the contact holes, and a sixth conductive layer formed on the fifth conductive layer is connected to the first conductive region exposed through the contact holes, and the sixth conductive layer is formed on the sidewalls of the contact holes. And the second, third, and fourth conductive layers are insulated by the spacers. 제1항에 있어서, 제2절연층, 상부에 제2전도층, 제3절연층, 제4전도층, 제4절연층, 제5전도층을 순차적으로 적층한 다음, 상기 제5전도층, 제4절연층, 제4전도층, 제3절연층의 일정부분이 제거되어 제2전도층이 노출된 콘택홀이 형성되고, 콘택홀 측벽에 절연스페이서가 형성되고 제5전도층 상부에 형성되는 제6전도층이 콘택홀을 통해 노출된 제2전도층에 접속되되, 제6전도층이 콘택홀 측벽에 형성된 절연스페이서에 의해 제3및 제4전도층과는 절연된 것을 포함하는 것을 특징으로 하는 반도체 소자의 접속장치.The method of claim 1, wherein a second insulating layer, a second conductive layer, a third insulating layer, a fourth conductive layer, a fourth insulating layer, and a fifth conductive layer are sequentially stacked on the second insulating layer, and then the fifth conductive layer, A portion of the fourth insulating layer, the fourth conductive layer, and the third insulating layer is removed to form a contact hole exposing the second conductive layer, an insulating spacer is formed on the sidewall of the contact hole, and is formed on the fifth conductive layer. And a sixth conductive layer connected to the second conductive layer exposed through the contact hole, wherein the sixth conductive layer is insulated from the third and fourth conductive layers by an insulating spacer formed on the sidewall of the contact hole. A semiconductor device connecting device. 제1항에 있어서, 제2절연층 상부에 제3전도층, 제3절연층, 제4전도층, 제4절연층, 제5전도층을 순차적으로 적층한 다음, 상기 제5전도층, 제4절연층의 일정부분이 제거되어 제3전도층이 노출된 콘택홀이 형성되고, 콘택홀 측벽에 절연스페이서가 형성되고 제5전도층 상부에 형성되는 제6전도층이 콘택홀을 통해 노출된 제3전도층에 접속되되, 제6전도층이 콘택홀 측벽에 형성된 절연스페이서에 의해 제4전도층과는 절연된 것을 포함하는 것을 특징으로 하는 반도체 소자의 접속장치.The method of claim 1, wherein the third conductive layer, the third insulating layer, the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer are sequentially stacked on the second insulating layer, and then the fifth conductive layer and the fifth conductive layer are stacked. A portion of the insulating layer is removed to form a contact hole exposing the third conductive layer, and an insulating spacer is formed on the sidewall of the contact hole, and a sixth conductive layer formed on the fifth conductive layer is exposed through the contact hole. And a sixth conductive layer insulated from the fourth conductive layer by an insulating spacer formed on the sidewalls of the contact holes, wherein the sixth conductive layer is insulated from the fourth conductive layer.
KR1019890001968A 1989-02-20 1989-02-20 Contacting device of semiconductor elements KR920007824B1 (en)

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