US20050072993A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- US20050072993A1 US20050072993A1 US10/904,496 US90449604A US2005072993A1 US 20050072993 A1 US20050072993 A1 US 20050072993A1 US 90449604 A US90449604 A US 90449604A US 2005072993 A1 US2005072993 A1 US 2005072993A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims description 53
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 47
- 239000012535 impurity Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims 41
- 239000011229 interlayer Substances 0.000 claims 5
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 49
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 49
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- 238000005229 chemical vapour deposition Methods 0.000 description 8
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- 229910052785 arsenic Inorganic materials 0.000 description 5
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- 230000003213 activating effect Effects 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Definitions
- the present invention relates to a semiconductor device and to a method for manufacturing the same. More particularly, it relates to a semiconductor device having a buried conductive layer which is connected to a source/drain of MOS transistor and extends over a gate electrode of the MOS transistor, and to a method for manufacturing the same.
- the alignment margin in the photolithographic process for a contact hole, formed to connect a source/drain of a MOS transistor and a wiring layer to each other is decreasing.
- the aspect ratio of the contact hole is also increasing.
- the aspect ratio is defined by the ratio of depth to diameter of the contact hole.
- a gate oxide film 103 is formed in an active region surrounded by the field oxide film 102 by the thermal oxidation method.
- a polycrystalline silicon containing phosphorus or arsenic, and a silicon oxide film 104 are formed in this order by the CVD method, and those films are then subjected to anisotropic etching with a photo resist film (not shown), formed to have a gate electrode patterned by photolithographic technology, as an etching mask, thereby forming a gate electrode 105 formed of the polycrystalline silicon film.
- the impurity ions are implanted into the unmasked region with the gate electrode 105 as a mask, thereby forming a pair of lightly doped impurity diffusion layers 106 in surface portions of the silicon substrate 101 on both sides of the gate electrode.
- the silicon oxide film is selectively etched away by anisotropic etching, thereby forming a side wall oxide film 107 on each of both side faces of the gate electrode 105 and the silicon oxide film 104 by anisotropic etching.
- a portion of the gate oxide film 103 formed on the region which is not covered with the gate electrode 105 or the side wall oxide film 107 is removed concurrently with the selective etching of the silicon oxide film.
- a polycrystalline silicon film 108 containing phosphorus or arsenic is formed on the whole surface of the silicon substrate 101 by the CVD method.
- This polycrystalline silicon film 108 will later become a buried conductive layer.
- the impurity ions are implanted into the unmasked region with both the gate electrode 105 and the side wall oxide film 107 as a mask, thereby forming a pair of highly doped impurity diffusion layers 109 as a source and a drain in the surface regions of the silicon substrate 101 on both sides of the gate electrode 105 .
- the photo resist film 110 is processed to have a pattern, of the buried conductive layer, having a slit 110 a on the gate electrode 105 by the photolithographic method. Thereafter, the polycrystalline silicon film 108 is selectively etched away by anisotropic dry etching with the photo resist film 110 as an etching mask, thereby processing the polycrystalline silicon film 108 to have a pattern which is separated into portions, located on both sides of the gate electrode 105 , with a width of the slit 110 a.
- the photo resist film 110 is removed.
- buried conductive layers 111 formed of the polycrystalline silicon film 108 which are respectively self-aligned with the pair of impurity diffusion layers 109 of the MOS transistor and each of which extends up to an upper portion of the gate electrode 105 .
- the buried conductive layers 111 are formed in such a way that the alignment margin of the contact hole for the wiring connection which is formed through the insulating film on the associated buried conductive layer 111 can be increased. Also, the substantial aspect ratio of that contact hole can be decreased by the thickness of the associated buried conductive layer 111 . As a result, it is possible to improve the reliability of the wiring connection in the contact hole portion. In addition, since the impurity diffusion layers 109 , each having a shallower junction, can also be formed, while suppressing occurrence of any crystal defect in the silicon substrate 101 , by thermal diffusion from the buried conductive layers 111 . Formation of the buried conductive layer 111 is also suitable for scaling down of the semiconductor device.
- the slit 110 a of the photo resist film 110 needs to be formed to reach the portion above the upper side of the gate electrode 105 , and also to have a width thereof much smaller than a width of the gate electrode 105 (a gate length).
- the central position of the slit of the photo resist film 110 is shifted in the direction of a width of the gate electrode by a distance X as shown in FIG. 2 , for example, so that the edge of the hole of the photo resist film 110 is located on the associated side wall oxide film 107 , under this condition, the polycrystalline silicon film 108 is subjected to the anisotropic etching.
- the buried conductive layer 111 in the boundary portion between the buried conductive layer 111 of interest and the associated side wall oxide film 107 will be selectively etched away during over-etching, but also the thin portion of the side wall oxide film 107 as well as the gate oxide film 103 will be etched away, and finally the surface of the silicon substrate 101 will be exposed.
- the width of the slit 110 a of the photo resist film 110 needs to be made much smaller than the gate length of the gate electrode 105 so that the hole edge of the photo resist film 110 is not located on the associated sidewall oxide film 107 even if the slight mismatch of alignment occurs.
- the gate length of the gate electrode 105 needs to be made much larger than the width of the slit 110 a of the photo resist film 110 .
- the gate length of the gate electrode 105 needs to be made much larger than the minimum processing size.
- JP-A-62-86715 there is described a method for manufacturing a semiconductor device wherein a contact hole is formed to be tapered in order to reduce the possibility of disconnection of the wiring layer.
- an insulating layer is formed to cover the contact region.
- a first photo resist mask is formed which is used to form a first contact hole.
- the insulating layer is etched to the depth of about one-half of the thickness of the insulating layer by anisotropic etching, thereby forming the first contact hole.
- the first photo resist mask is removed, and then a polycrystalline silicon layer is formed on the whole surface of the semiconductor substrate.
- the whole surface of the polycrystalline silicon layer is selectively etched away by gas plasma to leave a part of the polycrystalline silicon layer on both an edge portion of the first contact hole and a stepped portion of the insulating film.
- a second photo resist mask is formed which is used to form a second contact hole. Then a second contact hole is formed through the insulating film remaining in the first contact hole by etching.
- the etching, by which the first contact hole is perforated needs to be stopped at the time when the thickness of the insulating layer has been halved; hence, the control of the amount of etching is difficult to be carried out.
- an object of the present invention is, in a semiconductor device having a buried conductive layer connected to a source/drain of a MOS transistor and extending over a gate electrode of the MOS transistor, to enable manufacture of a finer transistor as compared with the prior art transistor while preventing damage to a semiconductor substrate without excessively complicating the manufacturing process.
- a method for manufacturing a semiconductor device includes the steps of: (a) forming a first insulating film on a semiconductor substrate; (b) forming a first conductive film as a gate electrode and a second insulating film on the first insulating film; (c) forming a third insulating film on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film and the second insulating film formed thereon; (d) selectively etching away the third insulating film to form a side wall insulating film including the third insulating film on each of both side faces of the first conductive film and the second insulating film and also to expose the semiconductor substrate in portions which are not covered with both the side wall insulating film and the first conductive film; (e) diffusing impurities into the exposed portions of the semiconductor substrate to form a source and a drain in the semiconductor substrate; (f) forming a second conductive film to be a part of a semiconductor substrate
- a semiconductor device including: (a) a semiconductor substrate having a source and a drain of a MOS transistor formed therein; (b) a first insulating film formed on a predetermined region of the semiconductor substrate; (c) a first conductive film as a gate electrode and a second insulating film formed on a predetermined region of the first insulating film; (d) a third insulating film, as a side wall insulating film, formed on each of both side faces of the first conductive film and the second insulating film; (e) a second conductive film connected to one of the source and the drain of the MOS transistor and extending up to an upper portion of the gate electrode of the MOS transistor, the second conductive film having a pattern in which the second conductive film is separated into both side portions with the second insulating film; (f) a first mask layer formed on a first region of the second conductive film; and (g) a second mask layer formed on a second region of the second insulating film
- the first mask layer may be removed so that the resultant second conductive film is used as a lower electrode of a capacitor.
- the interval of the patterns of the second conductive films which are adjacent to each other on the second insulating film can be made smaller than that of the patterns of the first mask layers by a width of the pattern of the second mask layer as compared with the interval.
- the interval of the patterns of the first mask layers is made a minimum processing size in the photolithographic technology
- the interval of the patterns of the second mask layers can be made smaller than the minimum processing size. Therefore, the width of the first conductive film, i.e., the gate electrode, can be made smaller than that of the prior art; e.g., it can be reduced to the minimum processing size.
- each of the first and second mask layers may be formed of either a conductive film or an insulating film.
- the mask layer of interest forms, together with the second conductive film, the buried conductive layer.
- FIGS. 1A to 1 E are, respectively, cross sectional views showing a conventional semiconductor device and a method for manufacturing the same in order of process;
- FIG. 2 is a cross sectional view useful in explaining the problems associated with the conventional semiconductor device and a method for manufacturing the same;
- FIGS. 3A to 3 I are, respectively, cross sectional views showing a semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same in order of process;
- FIG. 4 is a cross sectional view showing a structure of one modification of the semiconductor device according to the first embodiment of the present invention.
- FIG. 5 is a cross sectional view showing a structure of another modification of the semiconductor device according to the first embodiment of the present invention.
- FIGS. 6A to 6 E are respectively cross sectional views showing a semiconductor device according to a second embodiment of the present invention, and a method for manufacturing the same in order of process.
- FIGS. 3A to 3 I there are illustrated cross sectional views showing a semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same in order of process.
- a field oxide film 2 with about 400 nm thickness is formed in a region to be an isolation region of a P-type semiconductor silicon substrate 1 containing boron and having resistivity in the range of 1 to 12 ⁇ -cm by the well-known LOCOS method.
- a gate oxide film 3 with a thickness of 10 to 20 nm, or so is formed on an active region, which is surrounded by the field oxide film 2 , by the thermal oxidation method.
- a silicon oxide film 4 about 200 nm thick is formed on that polycrystalline silicon film by the CVD method.
- a photo resist film (not shown) is applied to the silicon oxide film 4 and then is processed to have a gate electrode pattern by utilizing the photolithographic technology.
- the silicon oxide film 4 is selectively etched away with that photo resist film as an etching mask by anisotropic etching, whereby the silicon oxide film 4 is processed to have a gate electrode shape.
- That polycrystalline silicon film is selectively etched away with the silicon oxide film 4 as an etching mask by anisotropic etching, thereby forming a gate electrode 5 formed of that polycrystalline silicon film.
- phosphorus ions are implanted into the unmasked region of the P type semiconductor silicon substrate 1 with the gate electrode 5 as a mask at acceleration energy of 30 to 150 keV with a dose of 5 ⁇ 10 12 to 5 ⁇ 10 13 ions/cm 2 , whereby a pair of lightly doped impurity diffusion layers 6 are formed in the surface portions of the silicon substrate 1 on both sides of the gate electrode 5 .
- the silicon oxide film is subjected to anisotropic etching, whereby a side wall oxide film 7 is formed on each of both side faces of the gate electrode 5 and the silicon oxide film 4 .
- a part of the gate oxide film 3 in the region, not covered with the gate electrode 5 or the side wall oxide film 7 is removed at the same time that the silicon oxide film is selectively etched away by the anisotropic etching, and as a result, a part of the silicon substrate 1 is exposed.
- arsenic ions are implanted into the unmasked region of the silicon substrate 1 with both the gate electrode 5 and the side wall oxide film 7 as a mask at acceleration energy of 50 to 100 keV with a dose of 5 ⁇ 10 15 to 5 ⁇ 10 16 ions/cm 2 , whereby a pair of highly doped impurity diffusion layers 9 as a source and a drain are formed in the surface portions of the silicon substrate 1 on both sides of gate electrode 5 .
- a polycrystalline silicon film 8 containing phosphorus or arsenic and having a thickness in the range of about 300 to 500 nm is formed on the whole surface of the silicon substrate 1 by the CVD method.
- This polycrystalline silicon film 8 thus formed will become a part of a buried conductive layer (an extraction electrode) later.
- a silicon oxide film (a first mask layer) 12 with about 200 nm thickness is formed on the whole surface of the polycrystalline silicon film 8 by the CVD method.
- the photo resist film 10 is processed by the photolithographic method to have a pattern having a slit 10 a above the gate electrode 5 , the pattern corresponding in a shape to the buried conductive layer
- the width of the slit 10 a of the photo resist film 10 is made substantially the same as the width of the gate electrode (a gate length) 5 . If the width of the slit 10 a is made to have a minimum processing size in the photolithographic technology, then the gate length may also be made substantially the same as the minimum processing size.
- the silicon oxide film 12 is selectively etched away with the photo resist film 10 as an etching mask by anisotropic dry etching to be separated into portions, located on both sides of the gate electrode 5 , with a distance corresponding to the width of the slit 10 a . Thereafter, the photo resist film 10 is removed by ashing.
- a polycrystalline silicon film (a second mask layer) 13 about 200 nm thick, which will be a part of the buried conductive layer later, is formed on the whole surface of the silicon substrate 1 by the CVD method.
- the thickness of the polycrystalline silicon film 13 is preferably one third of the distance between two portions of the silicon oxide film 12 as shown in FIG. 3E so that the area between the two portions is not completely filled with the polycrystalline silicon film 13 .
- the polycrystalline silicon film 13 is subjected to anisotropic dry etching to be left only on both side faces of the silicon oxide film 12 .
- the polycrystalline silicon film 8 is selectively etched away with both the silicon oxide film 12 and the polycrystalline silicon film 13 as an etching mask, whereby the polycrystalline silicon film 8 is removed except for its part underlying both the silicon oxide film 12 and the polycrystalline silicon film 13 so that the polycrystalline silicon film 8 is processed to have a pattern which is separated on the silicon oxide film 4 .
- a separation width of the polycrystalline silicon film 8 is smaller than the width of the slit 10 a by the width of the polycrystalline silicon film 13 remaining on both side faces of the silicon oxide film 12 .
- the buried conductive layer 11 including the remaining polycrystalline silicon films 8 and 13 is formed.
- a photo resist film 15 is applied to the BPSG film 14 .
- the photo resist film 15 is processed by photolithographic technology so as to have a pattern having a hole above the polycrystalline silicon film 8 .
- both the BPSG film 14 and the silicon oxide film 12 are selectively etched away with that photo resist 10 film 15 as an etching mask by anisotropic etching thereby forming a contact hole 16 reaching the polycrystalline silicon film 8 .
- the heat treatment process for activating the impurity diffusion layers 6 and 9 is carried out.
- an aluminum wiring layer 17 is formed which is connected to the polycrystalline silicon film 8 at the bottom of the contact hole 16 .
- a polycrystalline silicon wiring layer 17 is formed which is connected to the polycrystalline silicon film 8 at the bottom of the contact hole 16 and then the heat treatment process for activating the impurity diffusion layers 6 and 9 is carried out.
- the process for forming a passivation film is carried out, whereby a semiconductor device of the present embodiment is completed.
- the separation width of the polycrystalline silicon film 8 on the silicon oxide film 4 can be made smaller than the width of the slit 10 a by the width of the pattern of the polycrystalline silicon film 13 remaining on both sides of the silicon oxide film 12 since the polycrystalline silicon film 8 is selectively etched away with both the silicon oxide film 12 and the polycrystalline silicon film 13 as the etching mask.
- first mask layer is formed of the silicon oxide film 12 and also the second mask layer is formed of the polycrystalline silicon film 13 in the present embodiment, the present invention is not limited thereto.
- each of the first and second mask layers may be formed of either an insulating film or a conductive film.
- the present invention is not limited thereto. That is, in the case where the first mask layer is formed of conductive film, the contact hole 16 may be perforated to reach at least the first mask layer.
- the second mask layer is employed as the etching mask for the polycrystalline silicon film 8 containing the impurities, it preferably has a smaller etching rate than that of the polycrystalline silicon film 8 .
- the second mask layer is preferably formed of a polycrystalline silicon film containing no impurity since the etching rate is increased along with an increase in the content of impurities.
- the second mask layer will have its electric conductivity due to auto doping of the impurities from the polycrystalline silicon film 8 containing the impurities.
- the second mask layer may be formed of an insulating film which has a smaller etching rate than that of the polycrystalline silicon film 8 . The structure in this case will be described in detail later.
- the present invention is not limited thereto. That is, other well known isolation methods such as the field shielding isolation method may also be employed.
- FIG. 4 illustrates a cross sectional view showing a structure of an example designed in such a way that one of the source and the drain is connected to a wiring layer 24 through the buried conductive layer 11 , and the other is connected to a lower electrode 18 of a capacitor of a DRAM through the buried conductive layer 11 .
- a contact hole is formed through the silicon oxide film 22 to reach the polycrystalline silicon film 8 , and then the lower electrode 18 formed of a polycrystalline silicon film is formed by patterning. Then, after a capacitor dielectric film 19 formed of an ONO film and a upper electrode 20 formed of a polycrystalline silicon film are formed, in this order, to complete a DRAM capacitor 21 , a silicon oxide film 23 is formed on the whole surface of the silicon substrate 1 ; then a contact hole is perforated through the silicon oxide film 23 . A wiring layer 24 is then formed which is connected to the polycrystalline silicon film 8 of the films constituting the buried conductive layer 11 .
- FIG. 5 there is illustrated a cross sectional view showing a structure of another modification of the first embodiment which is designed in such a way that one of the source and the drain is connected to a wiring layer 30 through the buried conductive layer 11 , and the other is connected to the buried conductive layer 111 as a lower electrode of a DRAM capacitor.
- a DRAM memory cell As shown in FIG. 5 , after a photo resist film has been formed, which has a hole reaching the silicon oxide film 12 formed on one side, from the state shown in FIG. 3G , the silicon oxide film 12 is selectively removed with the photo resist film as an etching mask by wet etching. Then, the surface of the buried conductive layer 11 is coated with a capacitor dielectric film 26 after removal of the photo resist film, and a upper electrode 27 formed of a polycrystalline silicon film is formed, whereby it is possible to obtain a DRAM capacitor 28 in which the buried conductive layer 11 also serves as a lower electrode.
- a contact hole is formed through the silicon oxide film 29 , and then a wiring layer 30 is formed which is connected to the polycrystalline silicon film 8 on the other side.
- the effective surface area of the capacitor is increased; hence, the capacity of the capacitor is increased since the polycrystalline silicon film 13 , as a projection portion which projects upwardly in the vicinity of the edge portion of the buried conductive layer 11 , can be utilized as a part of the lower electrode.
- a silicon oxide film (a second mask layer) 51 about 200 nm thick is formed on the whole surface of the silicon substrate 1 by the CVD method.
- the silicon oxide film 51 is selectively etched away by the anisotropic dry etching so as to be left only on both side faces of the silicon oxide film 12 .
- the polycrystalline silicon film 8 is selectively etched away with both the silicon oxide films 12 and 51 as an etching mask, whereby the polycrystalline silicon film 8 is selectively removed except its part underlying both the silicon oxide films 12 and 51 so that the polycrystalline silicon film 8 is processed to have a pattern in which it is separated on the silicon oxide film 4 .
- the separation width of the polycrystalline silicon film 8 is smaller than the width of the slit 10 a , which was formed to have the same width as the gate length, by the width of the remaining silicon oxide film 51 .
- the buried conductive layer 11 formed of the remaining polycrystalline silicon film 8 is formed.
- a photo resist film 15 is applied to the BPSG film 14 .
- the photo resist film 15 is processed by photolithographic technology to have a pattern having a hole above the buried conductive layer 11 .
- both the BPSG film 14 and the silicon oxide film 12 are selectively etched away with the photo resist film 15 thus processed as an etching mask by anisotropic etching, thereby forming a contact hole 16 to reach the buried conductive layer 11 .
- the heat treatment for activating both the impurity diffusion layers 6 and 9 is carried out and then an aluminum wiring layer 17 is formed which is connected to the buried conductive layer 111 at the bottom of the contact hole 16 .
- a polycrystalline silicon wiring layer 17 is formed which is connected to the buried conductive layer 111 at the bottom of the contact hole 16 and then, the heat treatment for activating both the impurity diffusion layers 6 and 9 is carried out. Thereafter, the process for forming a passivation film is carried out, whereby the semiconductor device of the present embodiment is completed.
- the surface of the semiconductor substrate is partially etched away while etching the polycrystalline silicon film 8 , and the semiconductor substrate is damaged, e.g., a trench is formed in the semiconductor substrate.
- the reliability of the MOS transistor can be remarkably improved.
- the gate length of the gate electrode 5 can have a minimum processing size and hence a finer MOS transistor can be manufactured.
- the first and second mask layers are respectively formed of silicon oxide films 12 and 51 , each having an etching rate smaller than that of the polycrystalline silicon film 8 , the separation width of the polycrystalline silicon film 8 can be made smaller as compared with the case where the second mask layer is formed of a film having a large etching rate.
- the present embodiment may also be applied to the method for manufacturing a DRAM in the above-mentioned modifications as shown in FIG. 4 and FIG. 5 .
- the present invention is not limited thereto. That is, there may be employed other well known isolation methods such as the field shielding isolation method.
- the present invention it is possible to reduce the likelihood that the edge portion of the pattern of the second conductive film is located on the associated side wall insulating film since the separation width of the second conductive film constituting the buried conductive layer can be made smaller than the interval of the patterns of the first mask layers by the width of the pattern of the second mask layer. As a result, it is possible to solve the problem that while etching the second conductive film, even the semiconductor substrate is partially etched away and damaged. As a result, it is possible to remarkably improve the reliability of the MOS transistor without harming the advantage, resulting from the buried conductive layer, that the buried conductive layer can be formed to be self-aligned with the source/drain.
- the width (the gate length) of the first conductive film (the gate electrode) can be reduced to the minimum processing size since the separation width of the second conductive film can be smaller than the minimum processing size. Therefore, it is possible to manufacture a MOS transistor finer than that by the prior art.
Abstract
In a semiconductor device in which a source/drain and a wiring layer are connected to each other through an associated buried conductive layer, a separation width of the buried conductive layer on a upper portion of a gate electrode is made small to manufacture a highly reliable and fine MOS transistor. After a silicon oxide film has been formed on a first polycrystalline silicon film to be aligned with a width of a gate electrode, a second polycrystalline silicon film formed on the whole surface of a substrate is selectively etched away so as to be left only on both side faces of a pattern of the silicon oxide film. Thereafter, the first polycrystalline silicon film is selectively etched away with both the silicon oxide film and the second polycrystalline silicon film as an etching mask so that the first polycrystalline film is separated with a width which is smaller than that of the gate electrode by a width of a pattern of the second polycrystalline silicon film. As a result, the buried conductive layer including the first and second polycrystalline silicon films is formed.
Description
- This application is a Continuation of application Ser. No. 09/008,497 filed on Jan. 16, 1998. application Ser. No. 09/008,497 claims priority to Japanese Application 07-319482 filed on Nov. 14, 1995. application Ser. No. 09/008,497 is a Division of application Ser. No. 08/747,928 filed on Nov. 12, 1996. The contents of each of these applications are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device and to a method for manufacturing the same. More particularly, it relates to a semiconductor device having a buried conductive layer which is connected to a source/drain of MOS transistor and extends over a gate electrode of the MOS transistor, and to a method for manufacturing the same.
- 2. Description of the Related Art
- In recent years, as high integration and scale-down (i.e., shrinking) of a semiconductor device have progressed, the alignment margin in the photolithographic process for a contact hole, formed to connect a source/drain of a MOS transistor and a wiring layer to each other, is decreasing. In addition, the aspect ratio of the contact hole is also increasing. Now, the aspect ratio is defined by the ratio of depth to diameter of the contact hole. From the foregoing, a technique has been adopted in which the source/drain of the MOS transistor and the wiring layer are not directly connected to each other, but instead are indirectly connected to each other through a buried conductive layer (an extraction electrode) formed on the source/drain.
- Now, the process of manufacturing a MOS transistor employing that buried conductive layer will herein below be described with reference to
FIGS. 1A to 1E. - Firstly, as shown in
FIG. 1A , after afield oxide film 102 has been formed in a region to be an isolation region of asilicon substrate 101 by utilizing the well known LOCOS (Local Oxidation of Silicon) method, agate oxide film 103 is formed in an active region surrounded by thefield oxide film 102 by the thermal oxidation method. Thereafter, a polycrystalline silicon containing phosphorus or arsenic, and asilicon oxide film 104, are formed in this order by the CVD method, and those films are then subjected to anisotropic etching with a photo resist film (not shown), formed to have a gate electrode patterned by photolithographic technology, as an etching mask, thereby forming agate electrode 105 formed of the polycrystalline silicon film. In addition, the impurity ions are implanted into the unmasked region with thegate electrode 105 as a mask, thereby forming a pair of lightly dopedimpurity diffusion layers 106 in surface portions of thesilicon substrate 101 on both sides of the gate electrode. - Next, as shown in
FIG. 1B , after a silicon oxide film has been formed on the whole surface of thesilicon substrate 101, the silicon oxide film is selectively etched away by anisotropic etching, thereby forming a sidewall oxide film 107 on each of both side faces of thegate electrode 105 and thesilicon oxide film 104 by anisotropic etching. Incidentally, a portion of thegate oxide film 103 formed on the region which is not covered with thegate electrode 105 or the sidewall oxide film 107 is removed concurrently with the selective etching of the silicon oxide film. - Next, as shown in
FIG. 1C , apolycrystalline silicon film 108 containing phosphorus or arsenic is formed on the whole surface of thesilicon substrate 101 by the CVD method. Thispolycrystalline silicon film 108 will later become a buried conductive layer. Thereafter, the impurity ions are implanted into the unmasked region with both thegate electrode 105 and the sidewall oxide film 107 as a mask, thereby forming a pair of highly dopedimpurity diffusion layers 109 as a source and a drain in the surface regions of thesilicon substrate 101 on both sides of thegate electrode 105. - Next, as shown in
FIG. 1D , after aphoto resist film 110 has been applied to thepolycrystalline silicon film 108, thephoto resist film 110 is processed to have a pattern, of the buried conductive layer, having aslit 110 a on thegate electrode 105 by the photolithographic method. Thereafter, thepolycrystalline silicon film 108 is selectively etched away by anisotropic dry etching with thephoto resist film 110 as an etching mask, thereby processing thepolycrystalline silicon film 108 to have a pattern which is separated into portions, located on both sides of thegate electrode 105, with a width of theslit 110 a. - Next, as shown in
FIG. 1E , thephoto resist film 110 is removed. By carrying out the above-mentioned process, it is possible to form buriedconductive layers 111 formed of thepolycrystalline silicon film 108, which are respectively self-aligned with the pair ofimpurity diffusion layers 109 of the MOS transistor and each of which extends up to an upper portion of thegate electrode 105. - The buried
conductive layers 111 are formed in such a way that the alignment margin of the contact hole for the wiring connection which is formed through the insulating film on the associated buriedconductive layer 111 can be increased. Also, the substantial aspect ratio of that contact hole can be decreased by the thickness of the associated buriedconductive layer 111. As a result, it is possible to improve the reliability of the wiring connection in the contact hole portion. In addition, since theimpurity diffusion layers 109, each having a shallower junction, can also be formed, while suppressing occurrence of any crystal defect in thesilicon substrate 101, by thermal diffusion from the buriedconductive layers 111. Formation of the buriedconductive layer 111 is also suitable for scaling down of the semiconductor device. - Now, when forming the above-mentioned buried
conductive layer 111, in the process shown inFIG. 1D , theslit 110 a of thephoto resist film 110 needs to be formed to reach the portion above the upper side of thegate electrode 105, and also to have a width thereof much smaller than a width of the gate electrode 105 (a gate length). - If, due to the mismatch of alignment in the photolithography process, the central position of the slit of the
photo resist film 110 is shifted in the direction of a width of the gate electrode by a distance X as shown inFIG. 2 , for example, so that the edge of the hole of thephoto resist film 110 is located on the associated sidewall oxide film 107, under this condition, thepolycrystalline silicon film 108 is subjected to the anisotropic etching. Then not only the buriedconductive layer 111 in the boundary portion between the buriedconductive layer 111 of interest and the associated sidewall oxide film 107 will be selectively etched away during over-etching, but also the thin portion of the sidewall oxide film 107 as well as thegate oxide film 103 will be etched away, and finally the surface of thesilicon substrate 101 will be exposed. - Then, if the surface of the
silicon substrate 101 is exposed, since the etch selectivity of thesilicon substrate 101 to the buriedconductive layer 111 formed of a polycrystalline silicon film is remarkably small, even the surface of thesilicon substrate 101 will be partially etched away. As a result, atrench 120 will be formed in thesilicon substrate 101 by the etching. In such a way, thesilicon substrate 101 will be damaged. Such damage of thesilicon substrate 101 results in the performance of the MOS transistor being remarkably degraded. - To avoid that situation, the width of the
slit 110 a of thephoto resist film 110 needs to be made much smaller than the gate length of thegate electrode 105 so that the hole edge of thephoto resist film 110 is not located on the associatedsidewall oxide film 107 even if the slight mismatch of alignment occurs. This means that the gate length of thegate electrode 105 needs to be made much larger than the width of theslit 110 a of thephoto resist film 110. Thus, even if the width of theslit 110 a of thephoto resist film 110 should be made a minimum processing size provided by the photolithographic technology, the gate length of thegate electrode 105 needs to be made much larger than the minimum processing size. As a result, in the above-mentioned method of forming the buriedconductive layer 111, there is a limit in scale-down (i.e., shrinking) of the transistor. - To prevent damage of the
silicon substrate 101 due to the exposure of the surface of thesilicon substrate 101, there are considered (a) a method including the step of forming a polycrystalline silicon film, which will form a buried conductive layer later, after further forming an insulating film on the side wall oxide films, or (b) a method including the step of forming a thicker sidewall oxide film 107. However, in the former method, by the fine pattern technology, a hole needs to be formed through the insulating film formed on the associated sidewall oxide film 107 so that contact is made between the buried conductive layer and the source/drain. As a result, the advantage, resulting from the buried conductive layer, of being able to form the buried conductive layer to be self-aligned with the source/drain, is lost. In addition, in the latter method, the width of each sidewall oxide film 107 becomes necessarily large. Hence, this results in the fine transistor not being able to be formed. Therefore, the above-mentioned two methods for preventing the damage of thesilicon substrate 101 are not suitable for practical use. - In addition, in JP-A-62-86715, there is described a method for manufacturing a semiconductor device wherein a contact hole is formed to be tapered in order to reduce the possibility of disconnection of the wiring layer.
- The manufacturing method described in JP-A-62-86715 will herein below be described.
- After a contact region, having a predetermined pattern, has been formed on a semiconductor substrate, an insulating layer is formed to cover the contact region. Next, a first photo resist mask is formed which is used to form a first contact hole. Thereafter, the insulating layer is etched to the depth of about one-half of the thickness of the insulating layer by anisotropic etching, thereby forming the first contact hole. Thereafter, the first photo resist mask is removed, and then a polycrystalline silicon layer is formed on the whole surface of the semiconductor substrate. Next, the whole surface of the polycrystalline silicon layer is selectively etched away by gas plasma to leave a part of the polycrystalline silicon layer on both an edge portion of the first contact hole and a stepped portion of the insulating film. Subsequently, a second photo resist mask is formed which is used to form a second contact hole. Then a second contact hole is formed through the insulating film remaining in the first contact hole by etching.
- While the above-mentioned manufacturing method is suitable for the scale-down of the semiconductor device, the etching, by which the first contact hole is perforated, needs to be stopped at the time when the thickness of the insulating layer has been halved; hence, the control of the amount of etching is difficult to be carried out.
- In view of the foregoing problems associated with the prior art, an object of the present invention is, in a semiconductor device having a buried conductive layer connected to a source/drain of a MOS transistor and extending over a gate electrode of the MOS transistor, to enable manufacture of a finer transistor as compared with the prior art transistor while preventing damage to a semiconductor substrate without excessively complicating the manufacturing process.
- To attain the above-mentioned object, according to the present invention, a method for manufacturing a semiconductor device includes the steps of: (a) forming a first insulating film on a semiconductor substrate; (b) forming a first conductive film as a gate electrode and a second insulating film on the first insulating film; (c) forming a third insulating film on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film and the second insulating film formed thereon; (d) selectively etching away the third insulating film to form a side wall insulating film including the third insulating film on each of both side faces of the first conductive film and the second insulating film and also to expose the semiconductor substrate in portions which are not covered with both the side wall insulating film and the first conductive film; (e) diffusing impurities into the exposed portions of the semiconductor substrate to form a source and a drain in the semiconductor substrate; (f) forming a second conductive film to be a part of a buried conductive layer on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film, the second insulating film and the side wall insulating film formed thereon; (g) forming a first mask layer on the second conductive film; (h) processing the first layer so as for the first mask layer to have a pattern which is separated into both side portions with the first conductive film; (i) forming a second mask layer on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film, the second insulating film, the side wall insulating film, the second conductive film and the first mask layer formed thereon; (j) selectively etching away the second mask layer to leave a pattern of the second mask layer on each of both side faces of the pattern of the first mask layer; and (k) selectively etching away the second conductive film with the patterns of the first and second mask layers as a mask so as to process the second conductive film into a pattern in which the second conductive film is separated on the second insulating film.
- In addition, according to the present invention, there is provided a semiconductor device including: (a) a semiconductor substrate having a source and a drain of a MOS transistor formed therein; (b) a first insulating film formed on a predetermined region of the semiconductor substrate; (c) a first conductive film as a gate electrode and a second insulating film formed on a predetermined region of the first insulating film; (d) a third insulating film, as a side wall insulating film, formed on each of both side faces of the first conductive film and the second insulating film; (e) a second conductive film connected to one of the source and the drain of the MOS transistor and extending up to an upper portion of the gate electrode of the MOS transistor, the second conductive film having a pattern in which the second conductive film is separated into both side portions with the second insulating film; (f) a first mask layer formed on a first region of the second conductive film; and (g) a second mask layer formed on a second region of the second conductive film along each of side faces of the first mask layer.
- After the second conductive film has been selectively etched away to be processed into a predetermined pattern, the first mask layer may be removed so that the resultant second conductive film is used as a lower electrode of a capacitor.
- According to the present invention, since the first mask layer is formed on a region of a part of the second conductive film, and the second conductive film is selectively etched away with both the pattern of the first mask layer and the pattern of the second mask layer formed on each of both side faces thereof as an etching mask, the interval of the patterns of the second conductive films which are adjacent to each other on the second insulating film can be made smaller than that of the patterns of the first mask layers by a width of the pattern of the second mask layer as compared with the interval. As a result, even if the position of the edge portion of the pattern of the first mask layer is slightly shifted, it is possible to reduce the probability that the edge portion of the pattern of the second conductive film is located on the associated side wall insulating film. Hence, it is possible to promote scale down (i.e., shrinking) of the semiconductor device.
- In addition, when the interval of the patterns of the first mask layers is made a minimum processing size in the photolithographic technology, the interval of the patterns of the second mask layers can be made smaller than the minimum processing size. Therefore, the width of the first conductive film, i.e., the gate electrode, can be made smaller than that of the prior art; e.g., it can be reduced to the minimum processing size.
- Incidentally, in the present invention, each of the first and second mask layers may be formed of either a conductive film or an insulating film. In the case where one or both of the first and second mask layers is a conductive film, the mask layer of interest forms, together with the second conductive film, the buried conductive layer.
- The above and other objects as well as advantages of the present invention will become clear by the following description of the preferred embodiments of the present invention with reference to the accompanying drawings, wherein:
-
FIGS. 1A to 1E are, respectively, cross sectional views showing a conventional semiconductor device and a method for manufacturing the same in order of process; -
FIG. 2 is a cross sectional view useful in explaining the problems associated with the conventional semiconductor device and a method for manufacturing the same; -
FIGS. 3A to 3I are, respectively, cross sectional views showing a semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same in order of process; -
FIG. 4 is a cross sectional view showing a structure of one modification of the semiconductor device according to the first embodiment of the present invention; -
FIG. 5 is a cross sectional view showing a structure of another modification of the semiconductor device according to the first embodiment of the present invention; and -
FIGS. 6A to 6E are respectively cross sectional views showing a semiconductor device according to a second embodiment of the present invention, and a method for manufacturing the same in order of process. - The preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.
- Referring first to
FIGS. 3A to 3I, there are illustrated cross sectional views showing a semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same in order of process. - Firstly, as shown in
FIG. 3A , afield oxide film 2 with about 400 nm thickness is formed in a region to be an isolation region of a P-typesemiconductor silicon substrate 1 containing boron and having resistivity in the range of 1 to 12 Ω-cm by the well-known LOCOS method. Thereafter, agate oxide film 3 with a thickness of 10 to 20 nm, or so, is formed on an active region, which is surrounded by thefield oxide film 2, by the thermal oxidation method. - Then, after a polycrystalline silicon film about 100 nm thick containing phosphorus or arsenic of 2×1020 to 6×1020 atoms/cm3 is formed by the CVD method, a
silicon oxide film 4 about 200 nm thick is formed on that polycrystalline silicon film by the CVD method. Thereafter, a photo resist film (not shown) is applied to thesilicon oxide film 4 and then is processed to have a gate electrode pattern by utilizing the photolithographic technology. Then, thesilicon oxide film 4 is selectively etched away with that photo resist film as an etching mask by anisotropic etching, whereby thesilicon oxide film 4 is processed to have a gate electrode shape. Subsequently, after the photo resist film has been removed by ashing, that polycrystalline silicon film is selectively etched away with thesilicon oxide film 4 as an etching mask by anisotropic etching, thereby forming agate electrode 5 formed of that polycrystalline silicon film. In addition, phosphorus ions are implanted into the unmasked region of the P typesemiconductor silicon substrate 1 with thegate electrode 5 as a mask at acceleration energy of 30 to 150 keV with a dose of 5×1012 to 5×1013 ions/cm2, whereby a pair of lightly doped impurity diffusion layers 6 are formed in the surface portions of thesilicon substrate 1 on both sides of thegate electrode 5. - Next, as shown in
FIG. 3B , after a silicon oxide film whose thickness is in the range of about 100 to 200 nm has been formed on the whole surface of thesilicon substrate 1, the silicon oxide film is subjected to anisotropic etching, whereby a sidewall oxide film 7 is formed on each of both side faces of thegate electrode 5 and thesilicon oxide film 4. A part of thegate oxide film 3 in the region, not covered with thegate electrode 5 or the sidewall oxide film 7, is removed at the same time that the silicon oxide film is selectively etched away by the anisotropic etching, and as a result, a part of thesilicon substrate 1 is exposed. Thereafter, arsenic ions are implanted into the unmasked region of thesilicon substrate 1 with both thegate electrode 5 and the sidewall oxide film 7 as a mask at acceleration energy of 50 to 100 keV with a dose of 5×1015 to 5×1016 ions/cm2, whereby a pair of highly doped impurity diffusion layers 9 as a source and a drain are formed in the surface portions of thesilicon substrate 1 on both sides ofgate electrode 5. - Next, as shown in
FIG. 3C , apolycrystalline silicon film 8 containing phosphorus or arsenic and having a thickness in the range of about 300 to 500 nm is formed on the whole surface of thesilicon substrate 1 by the CVD method. Thispolycrystalline silicon film 8 thus formed will become a part of a buried conductive layer (an extraction electrode) later. Thereafter, a silicon oxide film (a first mask layer) 12 with about 200 nm thickness is formed on the whole surface of thepolycrystalline silicon film 8 by the CVD method. - Next, as shown in
FIG. 3D , after a photo resistfilm 10 has been applied to the whole surface of thesilicon oxide film 12, the photo resistfilm 10 is processed by the photolithographic method to have a pattern having aslit 10 a above thegate electrode 5, the pattern corresponding in a shape to the buried conductive layer In this connection, the width of theslit 10 a of the photo resistfilm 10 is made substantially the same as the width of the gate electrode (a gate length) 5. If the width of theslit 10 a is made to have a minimum processing size in the photolithographic technology, then the gate length may also be made substantially the same as the minimum processing size. - Next, as shown in
FIG. 3E , thesilicon oxide film 12 is selectively etched away with the photo resistfilm 10 as an etching mask by anisotropic dry etching to be separated into portions, located on both sides of thegate electrode 5, with a distance corresponding to the width of theslit 10 a. Thereafter, the photo resistfilm 10 is removed by ashing. - Next, as shown in
FIG. 3F , a polycrystalline silicon film (a second mask layer) 13 about 200 nm thick, which will be a part of the buried conductive layer later, is formed on the whole surface of thesilicon substrate 1 by the CVD method. The thickness of thepolycrystalline silicon film 13 is preferably one third of the distance between two portions of thesilicon oxide film 12 as shown inFIG. 3E so that the area between the two portions is not completely filled with thepolycrystalline silicon film 13. - Next, as shown in
FIG. 3G , thepolycrystalline silicon film 13 is subjected to anisotropic dry etching to be left only on both side faces of thesilicon oxide film 12. - Subsequently, the
polycrystalline silicon film 8 is selectively etched away with both thesilicon oxide film 12 and thepolycrystalline silicon film 13 as an etching mask, whereby thepolycrystalline silicon film 8 is removed except for its part underlying both thesilicon oxide film 12 and thepolycrystalline silicon film 13 so that thepolycrystalline silicon film 8 is processed to have a pattern which is separated on thesilicon oxide film 4. At this time, a separation width of thepolycrystalline silicon film 8 is smaller than the width of theslit 10 a by the width of thepolycrystalline silicon film 13 remaining on both side faces of thesilicon oxide film 12. As a result, the buriedconductive layer 11 including the remainingpolycrystalline silicon films - Next, as shown in
FIG. 3H , after a BPSG (Boro-Phospho Silicate Glass)film 14, a thickness of which is in the range of 500 to 1,000 nm or so, has been formed on the whole surface of thesilicon substrate 1, a photo resistfilm 15 is applied to theBPSG film 14. Thereafter, the photo resistfilm 15 is processed by photolithographic technology so as to have a pattern having a hole above thepolycrystalline silicon film 8. Then, both theBPSG film 14 and thesilicon oxide film 12 are selectively etched away with that photo resist 10film 15 as an etching mask by anisotropic etching thereby forming acontact hole 16 reaching thepolycrystalline silicon film 8. - Next, as shown in
FIG. 31 , after the photo resistfilm 15 has been removed, the heat treatment process for activating the impurity diffusion layers 6 and 9 is carried out. Then analuminum wiring layer 17 is formed which is connected to thepolycrystalline silicon film 8 at the bottom of thecontact hole 16. Alternatively, a polycrystallinesilicon wiring layer 17 is formed which is connected to thepolycrystalline silicon film 8 at the bottom of thecontact hole 16 and then the heat treatment process for activating the impurity diffusion layers 6 and 9 is carried out. Thereafter, the process for forming a passivation film is carried out, whereby a semiconductor device of the present embodiment is completed. - As described above, according to the present embodiment, the separation width of the
polycrystalline silicon film 8 on thesilicon oxide film 4 can be made smaller than the width of theslit 10 a by the width of the pattern of thepolycrystalline silicon film 13 remaining on both sides of thesilicon oxide film 12 since thepolycrystalline silicon film 8 is selectively etched away with both thesilicon oxide film 12 and thepolycrystalline silicon film 13 as the etching mask. - Although the first mask layer is formed of the
silicon oxide film 12 and also the second mask layer is formed of thepolycrystalline silicon film 13 in the present embodiment, the present invention is not limited thereto. Thus, it is to be understood that each of the first and second mask layers may be formed of either an insulating film or a conductive film. - In the case where the first mask layer is formed of a conductive layer, a value of a resistance developed between the source/drain of the MOS transistor and the
aluminum wiring layer 17 can be reduced since the area of the conductor contacting with thealuminum wiring 17 is increased. In addition, while thecontact hole 16 is perforated to reach thepolycrystalline silicon film 8 in the present embodiment, the present invention is not limited thereto. That is, in the case where the first mask layer is formed of conductive film, thecontact hole 16 may be perforated to reach at least the first mask layer. - Since the second mask layer is employed as the etching mask for the
polycrystalline silicon film 8 containing the impurities, it preferably has a smaller etching rate than that of thepolycrystalline silicon film 8. For example, the second mask layer is preferably formed of a polycrystalline silicon film containing no impurity since the etching rate is increased along with an increase in the content of impurities. In this case as well, the second mask layer will have its electric conductivity due to auto doping of the impurities from thepolycrystalline silicon film 8 containing the impurities. Alternatively, the second mask layer may be formed of an insulating film which has a smaller etching rate than that of thepolycrystalline silicon film 8. The structure in this case will be described in detail later. - In addition, while the LOCOS method is employed as the isolation method in the present embodiment, the present invention is not limited thereto. That is, other well known isolation methods such as the field shielding isolation method may also be employed.
- Next, a description will herein below be given with respect to a semiconductor device according to a modification of the first embodiment of the present invention with reference to
FIG. 4 . -
FIG. 4 , illustrates a cross sectional view showing a structure of an example designed in such a way that one of the source and the drain is connected to awiring layer 24 through the buriedconductive layer 11, and the other is connected to alower electrode 18 of a capacitor of a DRAM through the buriedconductive layer 11. - To manufacture a DRAM memory cell as shown in
FIG. 4 , after asilicon oxide film 22 has been formed on the whole surface of thesilicon substrate 1 from the state shown inFIG. 3G , a contact hole is formed through thesilicon oxide film 22 to reach thepolycrystalline silicon film 8, and then thelower electrode 18 formed of a polycrystalline silicon film is formed by patterning. Then, after acapacitor dielectric film 19 formed of an ONO film and aupper electrode 20 formed of a polycrystalline silicon film are formed, in this order, to complete aDRAM capacitor 21, asilicon oxide film 23 is formed on the whole surface of thesilicon substrate 1; then a contact hole is perforated through thesilicon oxide film 23. Awiring layer 24 is then formed which is connected to thepolycrystalline silicon film 8 of the films constituting the buriedconductive layer 11. - Referring to
FIG. 5 , there is illustrated a cross sectional view showing a structure of another modification of the first embodiment which is designed in such a way that one of the source and the drain is connected to awiring layer 30 through the buriedconductive layer 11, and the other is connected to the buriedconductive layer 111 as a lower electrode of a DRAM capacitor. - To manufacture a DRAM memory cell as shown in
FIG. 5 , after a photo resist film has been formed, which has a hole reaching thesilicon oxide film 12 formed on one side, from the state shown inFIG. 3G , thesilicon oxide film 12 is selectively removed with the photo resist film as an etching mask by wet etching. Then, the surface of the buriedconductive layer 11 is coated with acapacitor dielectric film 26 after removal of the photo resist film, and aupper electrode 27 formed of a polycrystalline silicon film is formed, whereby it is possible to obtain aDRAM capacitor 28 in which the buriedconductive layer 11 also serves as a lower electrode. After asilicon oxide film 29 has been formed on the whole surface of thesilicon substrate 1, a contact hole is formed through thesilicon oxide film 29, and then awiring layer 30 is formed which is connected to thepolycrystalline silicon film 8 on the other side. In this example, the effective surface area of the capacitor is increased; hence, the capacity of the capacitor is increased since thepolycrystalline silicon film 13, as a projection portion which projects upwardly in the vicinity of the edge portion of the buriedconductive layer 11, can be utilized as a part of the lower electrode. - Next, a description will be given with respect to a semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same with reference to
FIGS. 6A to 6E. - In the manufacturing process of the present embodiment, by carrying out the same process as that shown in
FIGS. 3A to 3E in the first embodiment of the present invention, there is obtained a structure, as shown inFIG. 6A , having a pattern in which the silicon oxide film (the first mask layer) 12 is separated into portions, located on both sides of thegate electrode 5, with the width of the gate length. - Next, as shown in
FIG. 6B , a silicon oxide film (a second mask layer) 51 about 200 nm thick is formed on the whole surface of thesilicon substrate 1 by the CVD method. - Next, as shown in
FIG. 6C , thesilicon oxide film 51 is selectively etched away by the anisotropic dry etching so as to be left only on both side faces of thesilicon oxide film 12. - Subsequently, the
polycrystalline silicon film 8 is selectively etched away with both thesilicon oxide films polycrystalline silicon film 8 is selectively removed except its part underlying both thesilicon oxide films polycrystalline silicon film 8 is processed to have a pattern in which it is separated on thesilicon oxide film 4. At this time, the separation width of thepolycrystalline silicon film 8 is smaller than the width of theslit 10 a, which was formed to have the same width as the gate length, by the width of the remainingsilicon oxide film 51. As a result, the buriedconductive layer 11 formed of the remainingpolycrystalline silicon film 8 is formed. - Next, as shown in
FIG. 6D , after a BPSG film the thickness of which is in the range of 500 to 1,000 nm or so, has been formed on the whole surface of thesilicon substrate 1, a photo resistfilm 15 is applied to theBPSG film 14. Thereafter, the photo resistfilm 15 is processed by photolithographic technology to have a pattern having a hole above the buriedconductive layer 11. Then, both theBPSG film 14 and thesilicon oxide film 12 are selectively etched away with the photo resistfilm 15 thus processed as an etching mask by anisotropic etching, thereby forming acontact hole 16 to reach the buriedconductive layer 11. - Next, as shown in
FIG. 6E , after the photo resistfilm 15 has been removed, the heat treatment for activating both the impurity diffusion layers 6 and 9 is carried out and then analuminum wiring layer 17 is formed which is connected to the buriedconductive layer 111 at the bottom of thecontact hole 16. Alternatively, a polycrystallinesilicon wiring layer 17 is formed which is connected to the buriedconductive layer 111 at the bottom of thecontact hole 16 and then, the heat treatment for activating both the impurity diffusion layers 6 and 9 is carried out. Thereafter, the process for forming a passivation film is carried out, whereby the semiconductor device of the present embodiment is completed. - In the present embodiment as well, similarly to the above-mentioned first embodiment, it is effectively avoided that the surface of the semiconductor substrate is partially etched away while etching the
polycrystalline silicon film 8, and the semiconductor substrate is damaged, e.g., a trench is formed in the semiconductor substrate. As a result, the reliability of the MOS transistor can be remarkably improved. In addition, since the separation width of thepolycrystalline silicon film 8 can be made smaller than the minimum processing size provided by the photolithographic technology, the gate length of thegate electrode 5 can have a minimum processing size and hence a finer MOS transistor can be manufactured. - In addition, since in the present embodiment, the first and second mask layers are respectively formed of
silicon oxide films polycrystalline silicon film 8, the separation width of thepolycrystalline silicon film 8 can be made smaller as compared with the case where the second mask layer is formed of a film having a large etching rate. - Incidentally, the present embodiment may also be applied to the method for manufacturing a DRAM in the above-mentioned modifications as shown in
FIG. 4 andFIG. 5 . - Further, while the LOCOS method is employed as the isolation method in the present embodiment, the present invention is not limited thereto. That is, there may be employed other well known isolation methods such as the field shielding isolation method.
- As set forth hereinabove, according to the present invention, it is possible to reduce the likelihood that the edge portion of the pattern of the second conductive film is located on the associated side wall insulating film since the separation width of the second conductive film constituting the buried conductive layer can be made smaller than the interval of the patterns of the first mask layers by the width of the pattern of the second mask layer. As a result, it is possible to solve the problem that while etching the second conductive film, even the semiconductor substrate is partially etched away and damaged. As a result, it is possible to remarkably improve the reliability of the MOS transistor without harming the advantage, resulting from the buried conductive layer, that the buried conductive layer can be formed to be self-aligned with the source/drain.
- In addition, according to the present invention, the width (the gate length) of the first conductive film (the gate electrode) can be reduced to the minimum processing size since the separation width of the second conductive film can be smaller than the minimum processing size. Therefore, it is possible to manufacture a MOS transistor finer than that by the prior art.
- While the present invention has been particularly shown and described with reference to the preferred embodiments of the specified modifications thereof, it will be understood that the various changes and other modifications will occur to those skilled in the art without departing from the scope and true spirit of the invention. The scope of the invention is therefore to be determined by the appended claims.
Claims (20)
1. A method for manufacturing a semiconductor device having a buried conductive layer which is connected to one of a source and a drain of a MOS transistor and extends over a gate electrode of said MOS transistor, said method comprising the steps of:
forming a first insulating film on a semiconductor substrate;
forming a first conductive film as said gate electrode and a second insulating film on said first insulating film;
forming a third insulating film on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film and said second insulating film formed thereon;
selectively etching away said third insulating film to form a side wall insulating film including said third insulating film on each of both side faces of said first conductive film and said second insulating film and also to expose said semiconductor substrate in portions which are not covered with said side wall insulating film and not covered with said first conductive film;
diffusing impurities into said exposed portions of said semiconductor substrate to form a source and a drain in said semiconductor substrate;
forming a second conductive film to be a part of said buried conductive layer on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film, said second insulating film and said side wall insulating film formed thereon;
forming a first mask layer on said second conductive film;
processing said first mask layer to have a pattern which is separated into both side portions as to said first conductive film;
forming a second mask layer on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film, said second insulating film, said side wall insulating film, said second conductive film and said first mask layer formed thereon;
selectively etching away said second mask layer to leave a pattern of said second mask layer on each of both side faces of the pattern of said first mask layer; and
selectively etching away said second conductive film with the patterns of said first and second mask layers as a mask so as to process said second conductive film into a pattern in which said second conductive film is separated on said second insulating film.
2. A method for manufacturing a semiconductor device according to claim 1 , wherein said first mask layer is formed of an insulating film, and said second mask layer is formed of a conductive film.
3. A method for manufacturing a semiconductor device according to claim 1 , wherein each of said first and second mask layers is formed of an insulating film.
4. A method for manufacturing a semiconductor device according to claim 1 , wherein said first mask layer Is formed of a conductive film, and said second mask layer is formed of an insulating film.
5. A method for manufacturing a semiconductor device according to claim 1 , wherein each of said first and second mask layers is formed of a conductive film.
6. A method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:
forming, after said step of selectively etching away said second conductive film, an interlayer insulating film on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film, said second insulating film, said side wall insulating film, said second conductive film, and said first and second mask layers formed thereon;
forming a contact hole through both said interlayer insulating film and said first mask layer so that said contact hole reaches said second conductive film; and forming a wiring layer which is connected to said second conductive film at the bottom of said contact hole.
7. A method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:
forming, after said step of selectively etching away said second conductive film, a fourth insulating film on the whole surface of said semi-conductor substrate having said first insulating film, said first conductive film, said second insulating film, said side wall insulating film, said second conductive film, and said first and second mask layers formed thereon;
forming a contact hole through both said fourth insulating film and said first mask layer so that said contact hole reaches said second conductive film;
forming a third conductive film in the inside of said contact hole so that said third conductive film reaches said second conductive film;
processing said third conductive film into an electrode pattern;
coating a surface of said third conductive film, which has been processed into the electrode pattern, with a dielectric film;
forming a fourth conductive film on said dielectric film; and
processing said fourth conductive film into an electrode pattern.
8. A method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:
removing said first mask layer after said step of selectively etching away said second conductive film;
coating at least a surface of said second conductive film with a dielectric film;
forming a third conductive film on said dielectric film; and
processing said third conductive film into an electrode pattern.
9. A method for manufacturing a semiconductor device according to claim 8 further comprising the step of coating a surface of said second mask layer with a dielectric film.
10. A semiconductor device comprising:
a semiconductor substrate having a source and a drain of a MOS transistor formed therein;
a first insulating film formed on a predetermined region of said semiconductor substrate;
a first conductive film as a gate electrode and a second insulating film formed on a predetermined region of said first insulating film;
a third insulating film, as a side wall insulating film, formed on each of both side faces of said first conductive film and said second insulating film;
a second conductive film connected to one of said source and said drain of said MOS transistor and extending over said gate electrode of said MOS transistor, said second conductive film having a pattern in which said second conductive film is separated into both side portions as to said second insulating film;
a first mask layer formed on a first region of said second conductive film; and
a second mask layer formed on a second region of said second conductive film along each of side faces of said first mask layer.
11. A semiconductor device according to claim 10 , wherein said first mask layer is formed of an insulating film, and said second mask layer is formed of a conductive film.
12. A semiconductor device according to claim 10 , wherein each of said first and second mask layers is formed of an insulating film.
13. A semiconductor device according to claim 10 , wherein said first mask layer is formed of a conductive film, and said second mask layer is formed of an insulating film.
14. A semiconductor device according to claim 10 , wherein each of said first and second mask layers is formed of a conductive film.
15. A semiconductor device according to claim 10 , further comprising:
an interlayer insulating film formed on said second insulating film, and said first and second mask layers, a contact hole being formed through both said interlayer insulating film and said first mask layer so as to reach said second conductive film; and
a wiring layer formed on said interlayer insulating film so as to fill in said contact hole, said wiring layer being connected to said second conductive film at the bottom of said contact hole.
16. A semiconductor device according to claim 10 , further comprising:
a fourth insulating film formed on said second insulating film, and said first and second mask layers, a contact hole being formed through both said fourth insulating film and said first mask layer so as to reach said second conductive film;
a first electrode formed on said fourth insulating film so as to fill in said contact hole, said first electrode being connected to said second conductive film at the bottom of said contact hole;
a dielectric film with which a surface of said first electrode is coated; and
a second electrode formed on said dielectric film.
17. A semiconductor device comprising:
a semiconductor substrate having a source and a drain of a MOS transistor formed therein;
a first insulating film formed on a predetermined region of said semiconductor substrate;
a first conductive film as a gate electrode and a second insulating film formed on a predetermined region of said first insulating film;
a side wall insulating film formed on each of both side faces of said first conductive film and said second insulating film;
a second conductive film connected to one of said source and said drain of said MOS transistor and extending over said gate electrode of said MOS transistor, said second conductive film having a pattern in which said second conductive film is separated into both side portions as to said second insulating film; and
a mask layer formed on an edge region of said second conductive film.
18. A semiconductor device according to claim 17 , wherein said mask layer is formed of a conductive film.
19. A semiconductor device according to claim 17 , wherein said mask layer is formed of an insulating film.
20. A semiconductor device according to claim 17 , further comprising:
a dielectric film with which at least a surface of said second conductive film is coated; and
an electrode formed on said dielectric film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/904,496 US20050072993A1 (en) | 1995-11-14 | 2004-11-12 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7319482A JPH09139495A (en) | 1995-11-14 | 1995-11-14 | Semiconductor device and its manufacture |
JP07-319482 | 1995-11-14 | ||
US08/747,928 US5744835A (en) | 1995-11-14 | 1996-11-12 | MOS semiconductor device with mask layers |
US09/008,497 US6833293B2 (en) | 1995-11-14 | 1998-01-16 | Semiconductor device and method for manufacturing the same |
US10/904,496 US20050072993A1 (en) | 1995-11-14 | 2004-11-12 | Semiconductor device and method for manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/008,497 Continuation US6833293B2 (en) | 1995-11-14 | 1998-01-16 | Semiconductor device and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050072993A1 true US20050072993A1 (en) | 2005-04-07 |
Family
ID=18110705
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/747,928 Expired - Lifetime US5744835A (en) | 1995-11-14 | 1996-11-12 | MOS semiconductor device with mask layers |
US09/008,497 Expired - Lifetime US6833293B2 (en) | 1995-11-14 | 1998-01-16 | Semiconductor device and method for manufacturing the same |
US10/904,496 Abandoned US20050072993A1 (en) | 1995-11-14 | 2004-11-12 | Semiconductor device and method for manufacturing the same |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/747,928 Expired - Lifetime US5744835A (en) | 1995-11-14 | 1996-11-12 | MOS semiconductor device with mask layers |
US09/008,497 Expired - Lifetime US6833293B2 (en) | 1995-11-14 | 1998-01-16 | Semiconductor device and method for manufacturing the same |
Country Status (2)
Country | Link |
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US (3) | US5744835A (en) |
JP (1) | JPH09139495A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060194390A1 (en) * | 2005-02-16 | 2006-08-31 | Yutaka Imai | Semiconductor device and method of manufacturing the same |
US20160214446A1 (en) * | 2013-09-25 | 2016-07-28 | Ste S.R.L. | Device and assembly for detecting tire parameters of transiting vehicles |
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TW387151B (en) * | 1998-02-07 | 2000-04-11 | United Microelectronics Corp | Field effect transistor structure of integrated circuit and the manufacturing method thereof |
US6063680A (en) * | 1998-02-19 | 2000-05-16 | Texas Instruments - Acer Incorporated | MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction |
US6420746B1 (en) * | 1998-10-29 | 2002-07-16 | International Business Machines Corporation | Three device DRAM cell with integrated capacitor and local interconnect |
US7377032B2 (en) * | 2003-11-21 | 2008-05-27 | Mitsui Mining & Smelting Co., Ltd. | Process for producing a printed wiring board for mounting electronic components |
JP2007067068A (en) * | 2005-08-30 | 2007-03-15 | Fujitsu Ltd | Method of manufacturing semiconductor device |
US7767099B2 (en) * | 2007-01-26 | 2010-08-03 | International Business Machines Corporaiton | Sub-lithographic interconnect patterning using self-assembling polymers |
JP5326405B2 (en) * | 2008-07-30 | 2013-10-30 | 株式会社デンソー | Wide band gap semiconductor device |
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US20160214446A1 (en) * | 2013-09-25 | 2016-07-28 | Ste S.R.L. | Device and assembly for detecting tire parameters of transiting vehicles |
Also Published As
Publication number | Publication date |
---|---|
US6833293B2 (en) | 2004-12-21 |
US20040212022A1 (en) | 2004-10-28 |
US5744835A (en) | 1998-04-28 |
JPH09139495A (en) | 1997-05-27 |
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